JPH1091272A - Clock supply circuit - Google Patents

Abstract

(57) [Problem] To provide a clock supply circuit capable of switching clocks and switching between an operation / stop state without breaking logic and achieving low power consumption. A control unit (10) controls a clock selection control signal (WL).
In response to the level changes of K ₀ , WLK ₁ and the clock stop signal DOSE, a state change instruction signal HDI is generated, and in response to this, the sequencer 121 holds the clock holding signal H for holding the clock when the output clock reaches a predetermined state.
The DC is output, the clock is switched by the output unit 20, the clock is switched, and when the switched clock reaches the same state as the retained clock, the output of the clock is restarted. In an operating logic circuit, clock switching can be realized without a logical breakdown or operation disorder, and by switching a clock in accordance with an operation state, power consumption of a device can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock supply circuit in a logic circuit capable of switching / stopping / re-operating a plurality of clocks.

[0002]

2. Description of the Related Art In a synchronous logic circuit which operates in response to a clock, a clock having a plurality of operating frequencies is switched and used, or a clock of a part of the block or the entire clock of the logic circuit is temporarily stopped / restarted. May operate. In order to realize this, a clock supply circuit that controls the timing of switching / stopping / re-operation of an output clock using a state machine in which an operation state transits is used.

[0003] As an example of a circuit in which clocks of a plurality of frequencies are switched and used, there is an example shown in US Patent No. 5083873. In this example, the output clock is generated by switching the three types of clocks serving as the original clocks and the clock stop state by the clock supply circuit in accordance with the timing of the original clocks.

As an example of a circuit for temporarily stopping / restarting a clock, there is an example shown in Japanese Patent Laid-Open No. Hei 5-11876. In this example, by using a three-state machine,
The output clock can be stopped and restarted accurately.

[0005]

The above-mentioned conventional clock supply circuits have respective problems. For example, in the example shown in US Pat. No. 5086387, since a delay occurs when a selection signal is generated from an original clock, a hazard corresponding to the delay time may be included in the output clock. In addition, Japanese Patent Application Laid-Open No. Hei 5-11876
In the example shown in (1), when a plurality of clocks having different frequencies are prepared for the input signal and the output signal, it is not possible to accurately control the phase relationship at the time of output. This phase shift poses a problem that when the clock is re-started from a stopped state, the operation of the circuit may be sequentially disrupted.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a logic circuit which operates with a plurality of clocks having different frequencies, including clock switching / stopping / re-operation including phase matching. Clock supply circuit that can perform accurate and accurate operation, and can switch and stop the operating frequency of each block for low power consumption, thereby reducing the power consumption of the entire circuit that operates with the clock provided by the clock supply circuit Is to provide.

[0007]

According to the present invention, there is provided a clock supply circuit capable of switching between a plurality of clocks and supplying the output clock as an output clock. A clock switching means for outputting a clock holding signal for holding the level and switching the clock after the output clock is held; and receiving the clock holding signal from the clock switching means, holding the output clock, and Output means for outputting the clock to the outside when the switched clock and the held clock are in the same state.

Further, in the present invention, it is determined whether or not the output clock of the output means is in a preset phase state, and when the output clock is in the preset phase state, the first timing A first determination circuit for outputting a signal; and determining whether or not the clock switched by the clock switching means is in the preset phase state. A second determination circuit that outputs a second timing signal when the phase state is reached.

Further, in the present invention, the clock switching means outputs a clock holding signal for causing the output means to hold the output clock in response to the first timing signal after receiving the clock switching instruction signal. In response to the second timing signal, the output means outputs a release signal for releasing the holding state of the output clock, and the output means receives the release signal from the clock switching means, and The clock switched by the means is output to the outside.

According to the present invention, the clock switching means causes the output means to hold the clock when the first determination circuit determines that the output clock has reached the predetermined state in response to the clock switching instruction signal. A clock holding signal is output, clock switching is performed with the output clock held, and the second determination circuit determines that the switched clock has reached a state similar to the held output clock. Then, the holding state of the output clock is released by the output means, and the output of the clock is restarted.

[0011] Thus, in a logic circuit operated by an output clock, clock switching can be realized without logic breakdown and operation disturbance, and by switching the clock in accordance with the operation state, the power consumption of the entire device is reduced. Can be reduced.

[0012]

FIG. 1 is a circuit diagram showing one embodiment of a clock supply circuit according to the present invention, and is a block diagram showing one configuration example of the present invention. As shown in the figure, the clock supply circuit of the present example includes a control unit 10, an output unit 20, and a clock generation unit 30, and the logic circuit 40 includes an output unit 20.
It operates on the clock supplied by.

[0013] The clock generator 30 is provided with a clock signal SC.
LK is generated and supplied to the control unit 10 and the output unit 20, respectively. The control unit 10 receives the clock signal SCLK from the clock generation unit 30 and outputs various control signals S10 to the selection unit 20. The output unit 20 receives the clock signal SCLK from the clock generation unit 30 and the control signal S10 from the control unit 10, selects a predetermined clock signal from a plurality of clock signals having different frequencies, and supplies the selected clock signal to the logic circuit 40. . A part of the clock signal output from the output unit 20 is supplied to the control unit 10.

In this embodiment, the clock generator 30
Is supplied to the control unit 10 and the output unit 20, and the control unit 10 generates a control signal for selecting a clock, and outputs the control signal to the output unit 20. Then, the output unit 20 selects a clock signal having a predetermined frequency from a plurality of clock signals having different frequencies generated based on the clock signal SCLK, and the selected clock signal is processed by, for example, an arithmetic processing unit such as a CPU. Supplied to the device.

FIG. 2 is a circuit diagram showing an example of the configuration of the control unit 10. As shown, the control unit 10 includes latches 100, 1
01, 102, exclusive OR gate 103, 1
04, 105, OR gate 106, NOR gate 10
7, NAND gate 108, buffer 1 with enable
09, 110, inverters 111, 112, 113, 1
14, 115, 116, AND gates 117, 118,
119, a latch 120 and a sequencer 121.

The latch 100 operates at the input terminals IN ₀ , I at the rising edge of the clock PCLK, for example.
Three signals WLK ₀ and WLK input to N ₁ and IN _2
1 and DOSE are latched and output terminals Q ₀ , Q ₁ and Q ₂ are latched.
Output to The input terminals IN ₀ , IN ₁ ,
IN ₂ are output terminals Q ₀ , Q ₁ ,
Because it is connected to the Q _2, the latch 101 on the rising edge of the inverted signal / PCLK clock PCLK, latches the three signals input from the latch 100, and outputs the latch 102. Since the input terminals IN ₀ , IN ₁ , and IN ₂ of the latch 102 are connected to the output terminals Q ₀ , Q ₁ , and Q ₂ of the latch 101, respectively, the latch 102 latches at the rising edge of the clock PCLK, for example. The three signals input from 101 are latched and output.

The input terminal of the exclusive OR gate 103 is connected to the output terminal Q _{0 of the} latch 100 and the latch 102.
It is connected to the output terminal Q ₀ of the output terminal OR gate 10
6 are connected to one input terminal. Input terminal of the exclusive OR gate 104 is connected to the output terminal to Q ₁ output terminals Q ₁ and latch 102 of the latch 100, the output terminal is connected to another input terminal of the OR gate 106. The input terminal of the exclusive OR gate 105 is connected to the output terminal Q _{2 of the} latch 100 and the latch 102.
It is connected to the output terminal Q _2, the output terminal OR gate 10
6 is connected to another input terminal.

The OR gate 106 has an exclusive O
Upon receiving the output signals of the R gates 103, 104 and 105,
A state change instruction signal HDI is generated, and the sequencer 121
Output to

The signals WLK ₀ and WLK ₁ input to the latch 100 are clock selection control signals for specifying the output clock of the clock supply circuit. Four types of output clocks are specified by a combination of the logic of these control signals. You. The signal DOSE input to the latch 100 is a clock stop signal designating stop of the clock signal. The clock supply circuit controls the operation / stop state of the output clock according to the level of the clock stop signal DOSE.

Latches 100, 101, 102, exclusive OR gates 103, 104, 105 and OR
The gate 106 forms a circuit for generating the state change instruction signal HDI. The clock selection control signals WLK ₀ ,
When any level change of WLK ₁ and the clock stop signal DOSE occurs, the state change instruction signal HDI is generated and input to the input terminal IN ₀ of the sequencer 121. The state change instruction signal HDI is, for example, a pulse signal that is held at a high level during one cycle of the clock PCLK.

The clock selection control signals WLK ₀ , W
LK ₁ is input to a NOR gate 107, a NAND gate 108, an AND gate 119, and a latch 120, respectively.

NOR gate 107 receives clock selection control signals WLK ₀ and WLK ₁ , generates a negative logical sum S 107 of these signals, and generates buffer 10 with enable.
9 enable signal input terminal en. NAN
The D gate 108 controls the clock selection control signals WLK ₀ , W
Receiving LK ₁ , a negative logical product S 108 of these signals is generated and input to the enable signal input terminal en of the buffer with enable 110.

The buffer with enable 109 outputs the external clock ECK input to the input terminal to the output terminal according to the level of the enable signal input to the enable signal input terminal en. For example, when a high-level enable signal is input to the enable signal input terminal en, the external clock ECK is output to the output terminal. At other times, the external clock ECK is not output. Similarly, the buffer with enable 110 outputs the control signal STP input to the input terminal to the output terminal according to the level of the enable signal input to the enable signal input terminal en. For example, when a high-level enable signal is input to the enable signal input terminal en, the control signal STP is output to the output terminal. At other times, the control signal STP is not output.

The external clock ECK output from the buffer with enable 109 is a latch signal ECK_LA
As T, it is output to the output unit 20 of the clock supply circuit,
The signal is inverted by the inverter 114 and the AND gate 119
Is input to The control signal STP output from the buffer with enable 110 is the latch signal STP_L.
The signal AT is output to the output unit 20 of the clock supply circuit, and is input to the AND gate 119.

The clock signal φ output from the output unit 20
₁Is inverted by the inverter 111, and the AND gate 1
17 and the clock signal output from the output unit 20.
No.φ _TwoIs input to the AND gate 117 as it is,
The clock signal φ output from the output unit 20_ThreeIs in
It is inverted by the barter 112 and enters the AND gate 117.
And the clock signal output from the output unit 20.
The signal CLK is inverted by the inverter 113, and
Is input to the gateway 117.

An AND gate 117 receives these signals, generates a timing signal HDT, and generates a timing signal HDT.
Is input to the input terminal IN _1. That is, when the clock signals φ ₁ , φ ₃ , and CLK output from the output unit 20 are all low and the clock signal φ ₂ is high,
The high-level timing signal HDT is output by the AND gate 117, and otherwise, the AND gate 11
7 outputs a low-level timing signal HDT.

The clock selector 201 in the output unit 20
From the clock BCLK via the inverter 115
The signal is input to the AND gate 118 and the clock selector 201
Is input to an AND gate 118 via an inverter 116. AND gate 1
18 generates a clock holding release signal HDR in response to these input signals, and generates an input terminal IN _{2 of the} sequencer 121.
To enter. That is, when the clocks BCLK and BCLK2X output from the clock selector 201 are both at a low level, the AND gate 118 outputs a high-level clock holding release signal HDR. At other times, the AND gate 118 outputs a low-level clock hold release signal HDR.

AND gate 119 receives clock selection control signals WLK ₀ , WLK ₁ , an inverted signal of external clock ECK from inverter 114 and control signal STP from buffer 110 with enable, and generates logical product S 119 of these signals. Then, the data is output to the latch 120.

The latch 120 outputs the signal input to the input side to the output side at the timing of the clock change signal CHG from the sequencer 121. The latch 120 is connected to the reset signal res input to the reset signal input terminal.
For example, when receiving a low-level reset signal reset according to the level of et, all the output terminals are reset.

At the rising edge of the clock change signal CHG from the sequencer 121, for example, at the rising edge, the latch 120 operates according to the levels of the clock selection control signals WLK ₀ and WLK ₁ input to the input terminals IN ₀ and IN _1.
Bit clock selection signal SEC to output terminals Q ₀ , Q ₁
Output to In addition, the latch 120 outputs the clock change signal C
At the rising edge of HG, depending on the level of S119 that is input to the input terminal IN _2, and outputs a control signal STP_LAT the output terminal Q _2. Also, the latch 120
Is the clock stop signal DO input to the input terminal IN ₃ at the rising edge of the clock change signal CHG.
It latches the level of the SE, and outputs the latch signal DOSE_LAT to the output terminal Q _3. Further, the latch 120
Is the CPU stop signal CPS input to the input terminal IN ₄ at the rising edge of the clock change signal CHG.
It latches the level of the latch signal C to the output terminal Q ₄
Output PS_LAT.

The sequencer 121 includes a state change instruction signal HDI input to the input terminal IN ₀ , a timing signal HDT input to the input terminal IN ₁ , a clock hold release signal HDR input to the input terminal IN ₂ , and a clock terminal CK. Clock holding signal HDC and clock change signal C according to the level of clock signal SCLK input to
Output HG.

FIG. 3 is a state transition diagram showing the state transition when the sequencer 121 operates. As shown, the sequencer 121 has six operation states S0 to S5. Hereinafter, the operation of the sequencer 121 will be described with reference to the state transition diagram of FIG.

During normal operation, the sequencer 121 is in the state S
0, and a predetermined clock signal is externally supplied by the clock supply circuit. At this time, the sequencer 121 monitors the level of the state change instruction signal HDI, and if the state change instruction signal HDI is held at a low level, the state transition from the state S0 does not occur, and the state change instruction signal HDI
When I switches from low level to high level, the sequencer 121 transitions to the state S1.

In the state S1, the sequencer 121 monitors the level of the timing signal HDT. When the timing signal HDT is held at the low level, no transition of the operation state occurs, and the timing signal HDT changes from the low level to the high level. When switched, the sequencer 121 transitions to the state S2.

In the state S2, the sequencer 121 switches the clock holding signal HDC to a high level,
Transition to the state S3. That is, the sequencer 121 is in the state S
The state is not held at 2, and the process unconditionally proceeds to the next state S3. When receiving the high-level clock holding signal HDC from the sequencer 121, the output unit 20 holds the clock signal to be output. That is, the output clock signal stops at a predetermined phase relationship.

In the state S3, the clock signal is changed. Further, it is possible to select a clock signal which is in a stopped state. However, in this state, although the clock change signal CHG is held at the high level by the sequencer 121, no change occurs in the output signal. State S
3 is not held, and unconditionally transits to the next state S4.

In the state S4, the sequencer 121 controls the timing of restarting the clock signal. The output clock signal is kept held until the phase relationship between the held output clock signal and the clock signals CLK and CLK2X output by the clock selector 201 becomes the same. A clock release signal H indicating that the phase of the output signal matches the phase of the output clock from the clock selector 201.
No transition from this state occurs until DR goes high. When the high-level clock hold release signal HDR is input, the state transits to the next state S5.

In the state S5, the sequencer 121 confirms that the phase relationship between the held output clock signal and the output clock from the clock selector 201 matches, then releases the holding of the clock signal and restarts the clock output. Then, the operating frequency is changed or stopped. At this time, the clock holding signal HDC is switched from the high level to the low level. State S5 is not held, and transits to state S0, which is a normal state.

The operations of the control unit 10 and the output unit 20 are controlled in accordance with the control signal output from the sequencer 121, so that the switching of the clock signal and the change in the state of the operation / stop / re-operation of the clock signal can be realized. In addition, the above-described sequencer 121 can prevent occurrence of a hazard and a phase shift when switching a clock signal and changing an operation / stop state.

The switching operation of the clock under the control of the sequencer 121 has been described above. The clock operation / stop / re-operation is controlled by a clock stop signal DOSE. Clock stop signal DOSE
Is at a low level during normal operation, for example, the ground potential GND.
Held on level. When stopping the supply of the clock, the clock stop signal DOSE is switched to a high level, for example, the power supply voltage V _CC level.

In response, the clock output by the output unit 20 is held. Then, the clock stop signal D
While the OSE is kept at the high level, the level of each clock signal does not change.

The switching of the clock from the stop state to the re-operation state is performed by switching the clock stop signal DOSE from a high level to a low level. At the falling edge of the clock stop signal DOSE, OR
The gate 106 generates a state change instruction signal HDI and inputs it to the sequencer 121. In response to this, a state transition occurs in the sequencer 121, and after switching of the designated clock signal after the restart, the clocks BCLK and BCLK2X output from the output unit 20 are output.
Is output, the output of the clock is restarted.

FIG. 4 is a circuit diagram showing an example of the configuration of the output section 20. As shown in the figure, the output unit 20 of this example is a frequency divider 20.
0, clock selector 201, NAND gates 202, 2
03,204, AND gates 205,206,207,
208, 225, 226, 227, 228, 229, selectors 209, 210, 211, 212, 213 and a latch 214.

The clock signal SCLK generated by the clock generator 30 is input to the input terminal IN of the frequency divider 200. The frequency divider 200 receives the input clock signal S
When the frequency of the CLK and f _S, the frequency f _S / 2 clock PCLK, clock PCLK ₁ frequency f _S / 4,
Clock PCLK ₂ of frequency f _s / 8, frequency f _s / 1
It generates a 6 five kinds of clock signals of the clock PCLK ₃ and the frequency f _S / 32 clock PCLK _4, and outputs the clock selector 201.

The clock selector 201 receives a signal from the control unit 10
According to the input 2-bit clock selection signal SEC
The clocks PCLK, P input from the frequency divider 200
CLK ₁, PCLK_Two, PCLK_Three, PCLK_FourInside
The frequency f_OClock signal BCLK and frequency 2
f_OAnd outputs the selected clock signal BCLK2X.
Note that the frequency f_OIs the frequency f_S/ 4, f_S/ 8, f_S/
16, f_S/ 32.

The NAND gate 202 receives the clock holding signal HDC from the control unit 10 and the latch signal CPS_LAT of the CPU stop signal CPS, and generates a negative logical product S202 of these signals.
04 and AND gates 205, 206, and 207, respectively.

The NAND gate 203 receives the clock BCLK2X from the clock selector 201 and the signal S202 from the NAND gate 202, generates a signal S203, and inputs the signal S203 to the input terminal H of the selector 209. The clock signal SCLK from the clock generator 30 is input to the input terminal L of the selector 209.

The AND gate 205 is connected to the clock selector 2
01 clock BCLK and NAND gate 20
In response to the signal S202 from the second, a signal S205 is generated and input to the input terminal H of the selector 210. Clock signal PCLK from frequency divider 200 is input to input terminal L of selector 210.

The selectors 209 and 210 are provided with a latch signal ECK_L of the external clock ECK input from the control unit 10.
The signal input to the input terminal H or the input terminal L is selected and output according to the level of the AT. For example, the signal EC
When K_LAT is held at the low level, the selector 209 outputs the clock signal SC input to the input terminal L.
LK is selected and output as the clock signal CLK2X. On the other hand, when the signal ECK_LAT is held at the high level, the selector 209 selects S203 input to the input terminal H and outputs the same as the clock signal CLK2X.

Similarly, when the signal ECK_LAT is held at the low level, the selector 210 sets the input terminal L
Is selected and output as a clock signal CLK. On the other hand, the signal ECK_LA
When T is held at a high level, the selector 210
Selects S205 input to the input terminal H and outputs it as the clock signal CLK.

The AND gate 206 is connected to the clock selector 2
01 clock BCLK and NAND gate 20
In response to the signal S202 from the second, a signal S206 is generated and input to the input terminal L of the selector 211. The input terminal H of the selector 211 is held at a low level, for example, at the ground potential GND level.

The NAND gate 204 receives the clock BCLK from the clock selector 201 and the NAND gate 2
In response to the signal S202 from the input device 02, a signal S204 is generated and input to the input terminal L of the selector 212. The input terminal H of the selector 212 is held at a high level, for example, at the power supply voltage V _CC level.

The NAND gate 207 receives the clock BCLK2X from the clock selector 201 and the signal S202 from the NAND gate 202, generates a signal S207, and inputs the signal S207 to the input terminal L of the selector 213. The input terminal H of the selector 213 is held at a high level, for example, at the power supply voltage V _CC level.

The selectors 211, 212, and 213 select and output the signal input to the input terminal H or the input terminal L according to the level of the latch signal DOSE_LAT of the clock stop signal DOSE input from the control unit 10.
For example, when the signal DOSE_LAT is held at a low level, the selector 211 selects the signal S206 input to the input terminal L and outputs the signal S206 to the latch 214.
On the other hand, when the signal DOSE_LAT is held at a high level, the selector 211 selects the signal input to the input terminal H. That is, at this time, the output terminal of the selector 211 is held at the low level.

Similarly, when the signal DOSE_LAT is held at the low level, the selector 212 selects the signal S204 input to the input terminal L, and
Output to On the other hand, when the signal DOSE_LAT is held at a high level, the selector 212
Select the signal input to. That is, at this time, the output terminal of the selector 212 is held at the high level.

Further, in the selector 213, when the signal DOSE_LAT is held at a low level,
The selector 213 outputs the signal S20 input to the input terminal L.
7 are selected and output as the clock signal phi _3. On the other hand, when the signal DOSE_LAT is held at a high level, the selector 213 selects the signal input to the input terminal H. That is, this time, the clock signal phi ₃ is held at the high level. The output signal S207 of the AND gate 207 as a clock signal phi _3S, is output together with the clock signal phi _3.

The latch 214 latches a signal input to the input side according to the clock BCLK2X from the clock selector 201 and outputs the signal to the output side. For example, the latch 214 at the rising edge of the clock BCLK2X, latches the output signal of the selector 211, and outputs to the output terminal Q _0. The output signal of the output terminal Q ₀ is input to one input terminal of the AND gate 225, and is further transmitted through the inverters 215 and 216 connected in series.
The signal is input to the other input terminal of the D gate 225. AND
An output terminal of gate 225 is connected to the output terminal of the clock signal phi _1.

Further, the latch 214 outputs the clock BCLK
On the rising edge of 2X, latches the output signal S206 of the AND gate 206, and outputs to the output terminal Q _1.
The output signal of the output terminal Q ₁ is input to one input terminal of the AND gate 226, further via the inverter 217 and 218 are connected in series, are input to the other input terminal of the AND gate 226. An output terminal of the AND gate 226 is connected to the output terminal of the clock signal phi _1S.

The latch 214 outputs the clock BCLK
On the rising edge of 2X, latches the output signal of the selector 212, and outputs to the output terminal Q _2. Output terminal Q ₂
Is input to one input terminal of the AND gate 227, and further connected to the inverter 21 connected in series.
9, 220, and is input to the other input terminal of the AND gate 227. The output terminal of the AND gate 227 is
Is connected to the output terminal of the clock signal phi _2.

Further, the latch 214 receives the clock BCL
At the rising edge of K2X, the output of AND gate 208 is output.
Output signal Q_ThreeOutput to Output end
Child Q _ThreeIs output from one input terminal of an AND gate 228.
Inverters that are input to
221 and 222, the other of the AND gate 228
Input to the input terminal. Output terminal of AND gate 228
Is the clock signal φ_2ROutput terminal.

Furthermore, the latch 214
At the rising edge of CLK2X, NAND gate 20
The fourth output signal is latched and outputted to the output terminal Q _4.
Output signals of the output terminal Q ₄ are input to one input terminal of the AND gate 229, further via the inverter 223 and 224 are connected in series, are input to the other input terminal of the AND gate 229. An output terminal of the AND gate 229 is connected to the output terminal of the clock signal phi _2S.

As described above, each clock signal φ
₁ , φ _1S , φ ₂ , φ _2R , and φ _2S are the logical product of the original clock and the clock passed through the two-stage inverter connected in series, and the rising edge of the output clock is 2 Delay by the delay time of the inverter in the stage. Thus, for example, falling overlapping edges of the clock signal phi ₂ clock signal phi ₁ of the rising edge and its inverted signal is avoided, the occurrence of malfunction due to external circuitry overlap clock running at these clock Can be prevented.

FIG. 5 is a waveform diagram showing waveforms during the operation of the clock supply circuit of the present embodiment. Hereinafter, the operation of the clock supply circuit of the present example will be described with reference to the waveform diagram of FIG. As shown in FIG. 5, the clock signals φ ₁ and φ ₂ are clock signals having phases inverted from each other, and the clock signal φ _2R
Is in phase with the clock signal φ ₂ and the control signal RUN
(Waveform not shown) is output only when held at a high level.

Clock B output from selector 209
The frequency of CLK2X is twice the frequency of clock signal CLK output from selector 210. Further, assuming that the external clock ECK input to the output unit 20 is held at, for example, a high level, the selector 210 selects the clock signal BCLK output from the clock selector 201 and outputs it as the clock signal CLK. Therefore, as shown in FIG. 5, the waveforms of the clock signal CLK and the clock signal BCLK are the same.

[0065] until the clock selection control signal WLK ₀ to level change occurs time t _0, the clock supply circuit to normal operation, continues to output a clock signal to the outside. At this time, the sequencer 121 in the control unit 10 is held in the state S0. Then, at time t ₀ , the clock selection control signal WLK ₀ switches from the low level to the high level.
The state change instruction signal HDI is generated, and the sequencer 121
Is input to

The sequencer 121 outputs a state change instruction signal H
In response to DI, a state transition occurs from state S0 to state S1. In the state S1, the sequencer 121 waits for a level change of the timing signal HDT.

At time t ₁ , the timing signal HDT
Rises, and in response, the sequencer 121 transitions to the state S2. At this time, the sequencer 121
A high-level clock holding signal HDC is output. Then, after switching the clock holding signal HDC, the sequencer 121 transitions from the state S2 to the state S3. State S
3, the sequencer 121 outputs the clock change signal CH
Start G. In response, the clock selection signal SE
Clock selection control signals WLK ₀ , WLK to which C is input
Set according to level ₁ .

Output unit 20 receives a high level clock holding signal HDC from control unit 10. If the CPU stop signal CPS is held at a high level, for example, the NAND gate 202 of the output unit 20 outputs a low-level signal S202. In response, NAND gates 203 and 204 output high-level signals S203 and S204, respectively.
D-gates 205 and 206 output low-level signals S205 and S206, respectively.

Therefore, as shown in FIG. 5, the clock signal φ ₁ is at the low level, the clock signal φ ₂ is at the high level,
Clock signal phi _2R is low level, the clock signal CLK is at a low level, the clock CLK2X are respectively held at the high level. That is, all the levels of the clock signal output from the output unit 20 are held. During this time, the clock signal specified by the clock selection signal SEC is selected by the clock selector 201, and the clock BCLK2
Output as X, BCLK. As described above, while the output signal is held, the clock signal is switched by the clock selector 201. Then, when the switching of the clock signal is completed, the sequencer 121 lowers the clock change signal CHG to change from the state S3 to the state S3.
Transition to 4.

In the state S4, the sequencer 121 monitors the level of the clock holding release signal HDR. While the clock holding release signal HDR is held at the low level, no state transition is performed and the clock holding release signal HDR is not changed.
After R rises from the low level to the high level, the clock change signal CHG is switched from the high level to the low level, and the state transits to the state S5.

In the state S5, the sequencer 121 switches the clock holding signal HDC from the high level to the low level, and makes a transition to the normal state S0. When the clock holding signal HDC is switched to the low level, the clock holding state in the output unit 20 is released, and the clock output operation is restarted. As a result, the output is restarted in the same state as when the clock is held, so that clock switching can be realized without causing a hazard in the output clock.

As described above, the switching of the clock is performed under the control of the sequencer 121, and the clock after the switching is in the same state as the clock held before the start of the switching. The switching of the clock is realized without the logical failure and the disturbance of the operation of the external circuit which is operated by the supplied clock. Thus, for example, in the normal operation state and the standby state, the clocks having different operation frequencies are switched and supplied to the external circuit, so that the power consumption of the entire device can be reduced.

As described above, according to the present embodiment, the control section 10 controls the clock selection control signals WLK ₀ , WL
Generating a status change indication signal HDI in accordance with the level change of the K ₁ and the clock stop signal DOSE, sequencer 121 outputs a clock hold signal HDC for holding the clock when the output clock has reached a predetermined state in response to this , And the output unit 20 holds the clock. Then, the clock is switched, and when the switched clock reaches a state similar to the held clock, the output of the clock is restarted. Therefore, in the logic circuit operated by the output clock, the breakdown of the logic and the disturbance of the operation are prevented. In addition, the clock can be switched, and the clock can be switched according to the operation state, whereby the power consumption of the device can be reduced.

[0074]

As described above, according to the clock supply circuit of the present invention, clock switching / stop / re-operation can be performed accurately including the phase relationship. As a result, in a logic circuit operating in synchronization with a clock signal, clock switching and switching between an operation / stop state can be performed without breaking the logic, and an operation frequency can be switched or stopped for each block to reduce power consumption. Thus, there is an advantage that power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a clock supply circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a control unit in the clock supply circuit.

FIG. 3 is a state transition diagram of a sequencer.

FIG. 4 is a circuit diagram illustrating a configuration example of an output unit in the clock supply circuit.

FIG. 5 is a timing chart of the clock supply circuit.

[Explanation of symbols]

10 control unit, 20 output unit, 30 clock generation unit,
100, 101, 102 ... latch, 103, 104, 1
05: Exclusive OR gate, 106: OR gate, 107: NOR gate, 108: NAND gate,
109, 110: Buffer with enable, 111, 1
12, 113, 114, 115, 116 ... inverter,
117, 118, 119: AND gate, 120: latch, 121: sequencer, 200: frequency divider, 201: clock selector, 202, 203, 204: NAND gate, 205, 206, 207, 208, 225, 22
6, 227, 228, 229... AND gate, 209,
210, 211, 212, 213 ... selector, 214 ...
Latch, V _CC ... the power supply voltage, GND ... ground potential.

Claims (5)

[Claims] 1. A clock supply circuit capable of switching between a plurality of clocks and supplying the output clock as an output clock, comprising: receiving a clock switching instruction signal, outputting a clock holding signal for holding a level of an output clock, and holding the output clock. A clock switching means for switching the clock after the switching, and receiving a clock holding signal from the clock switching means, holding an output clock, and the clock switched by the switching means and the held clock are in the same state. A clock supply circuit having output means for outputting a clock to the outside when the clock signal is output. Determining whether the output clock of the output means is in a preset phase state, and outputting a first timing signal when the output clock is in a preset phase state; The clock supply circuit according to claim 1, further comprising a first determination circuit. Determining whether or not the clock switched by the clock switching means is in the preset phase state; and determining whether or not the switched clock is in the preset phase state, 2. The clock supply circuit according to claim 1, further comprising a second determination circuit that outputs a second timing signal. 4. The clock switching means, after receiving the clock switching instruction signal, outputs a clock holding signal for holding the output clock to the output means in response to the first timing signal. 4. The clock supply circuit according to claim 3, wherein a release signal for releasing the holding state of the output clock is output to said output means in response to the timing signal of (2). 5. The clock supply circuit according to claim 4, wherein said output means receives a release signal from said clock switching means and outputs the clock switched by said clock switching means to the outside.