JPH1091429A - Information processing device - Google Patents

Abstract

(57) Abstract: A processor that supports a plurality of instruction architectures, and eliminates the control storage of microinstructions and instruction words and the redundant storage in instruction storage. A mode register for holding an architecture mode of an instruction to be processed, a plurality of setup data generation units (DS) for generating setup data required for instruction processing for each instruction architecture mode, and an execution order of each instruction are determined. A plurality of sequence memories (SS) for storing the sequence code sequences provided are provided. With the mode register, one DS is selected, setup data of the instruction to be processed is obtained, a part of the setup data is input to one SS as an SS address, and a sequence code sequence of the instruction is read from the SS, Using the code string as an address for control storage or instruction storage, a target microinstruction group or instruction word group is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for performing instruction processing by microcode control or hardware logic, and more particularly to reading and reading microinstructions and instructions suitable for a multi-instruction architecture processor having different instruction architectures. Regarding the execution mechanism.

[0002]

2. Description of the Related Art In a conventional information processing apparatus which implements instruction processing by microcode, an instruction control unit reads and decodes an instruction from a main memory or the like, and then stores the instruction stored in a control memory in advance. The microinstruction (microinstruction data) that realizes the processing function of (1) is sequentially read out according to a microcode processing procedure in a fixed procedure, the microinstruction is temporarily set in the control storage data register, and the microinstruction is executed from the control storage data register. Is generally sent to an execution unit that performs the operations described above, and the execution unit performs a plurality of operations specified by a plurality of fields of the microinstruction.

In an information processing apparatus in which instruction processing is implemented by hardware logic without implementing instruction processing by conventional microcode, an instruction control unit stores a plurality of instructions stored in a main memory or the like. According to the processing procedure of the program code composed of instructions, sequentially read the instruction words constituting the program code in a predetermined procedure,
After decoding and generating a parameter group necessary for execution of the decoded instruction word, the command group is sent to an execution unit that is responsible for executing the instruction, and the execution unit executes a plurality of operations specified by the parameter group. This is generally done.

First, a description will be given of a problem in a case where the present invention is applied to a micro-instruction read-out execution mechanism and a multi-instruction architecture processor of an information processing apparatus which realizes conventional instruction processing using microcode.

FIG. 2 shows a conventional information processing apparatus which implements instruction processing by using microcode, in particular, a main memory (hereinafter, referred to as MS) 200 and an instruction control unit (hereinafter, referred to as I).
U) 210, a control storage address register (hereinafter, referred to as a U)
CSAR) 250, control storage (hereinafter, referred to as CS) 260, control storage data register (hereinafter, CSDR)
FIG. 2 is a block diagram showing a relationship between the execution unit 270 and an execution unit 280 (hereinafter, referred to as EU).

[0006] The MS 200 stores a group of instructions. IU
210 reads an instruction from the MS 200;
After decoding the instruction, the first C corresponding to the instruction is read.
A micro instruction address of S (hereinafter referred to as an IU setup address) is created and sent to the CSAR 250.
Note that the instruction read source of the IU 210 may be a buffer storage or an instruction buffer. CSAR 250 receives and sets the IU setup address sent from IU 250, and issues a read request to CS 260 using the set CS start address. CS
260 reads out the intended microinstruction (microinstruction data) using the address and sends it to the CSDR 270. The CSDR 270 sets the microinstruction sent from the CS260, sends it to the EU 280, and stores data in a branch address field (hereinafter, referred to as a BA field) holding a microinstruction address to be executed next in the microinstruction. CSAR250
To send to. CSAR 250 uses B in the microinstruction
The data in the A field is set, and the process returns to the operation of issuing a read request to the CS 260. Hereinafter, by repeating this, microcodes composed of a plurality of microinstructions in the CS 260 realizing the functions of the respective instruction words read from the MS 200 are sequentially executed.

[0007] The end of the execution of a microcode composed of a series of a plurality of microinstructions is determined by an operation end field (hereinafter, referred to as an end field) of the last microinstruction constituting the microcode.
This is realized by setting the value of the EOP field to ON.

When a microinstruction whose EOP field value is on is read from CS 260, CSDR 270 reads the data in the BA field holding the next microinstruction address to be executed in the microinstruction. The value of the EOP field is sent to the IU 210 without sending it to the CSAR 250. IU 210
When the value of the EOP field which is ON is received, the next instruction is read, and after decoding, the micro instruction address (IU setup address) of the first CS corresponding to the instruction is created and transmitted to the CSAR 250. ,
Invokes the microcode execution of the next instruction.

FIG. 3 shows the configuration of an instruction register, an instruction decoder, and a setup data generator in the IU 210. The IU 210 issues a read request for the instruction word to the main memory or the like, sets the read instruction word in an instruction register (hereinafter, referred to as IR) 211, and then sends it to an instruction decoder (hereinafter, referred to as IDEC) 212. Send out. I
The DEC 212 decodes the instruction code of the instruction word, and sends the instruction code, the instruction format, and the result of decoding other instructions to a setup data generator (hereinafter, referred to as DS) 213. The DS 213 generates the setup data based on the command decoding result of the command, and the EU 213 and the CSA
Send to R250. DS213 to CSAR250
Is the head microinstruction address of the instruction to be executed, and the IU setup data transmitted from the DS 213 to the EU 280 is the operand address or operand data of the instruction to be executed. And control information necessary for executing the microcode.

The DS 213 generally includes a storage device using each instruction code as an address parameter, and stores an IU setup data group corresponding to each instruction word supported by the instruction architecture of the processor (information processing device). It is stored in a storage device in advance, and the I
Generation of the U setup data is performed by reading the storage device.

FIG. 4 is a diagram showing a connection between a procedure of executing microcode composed of a plurality of microinstructions and a plurality of microinstructions in a conventional information processing apparatus which implements instruction processing with this kind of microcode. It is.

As described with reference to FIGS. 2 and 3, IU2
10 reads and decodes the instruction, creates an IU setup address corresponding to the head microinstruction address of the instruction, and sends it to the CSAR 250 for setting. Using the IU setup address set in the CSAR 250, the first microinstruction is read from the CS 260 and set in the CSDR 270. The BA field of the first microinstruction holds the CS address of the second microinstruction to be executed next. The first
The BA field of the microinstruction is sent to the CSAR 250 for setting, and the second microinstruction is read from the CS 260 using the address of the BA field. Here, the IU setup address is not used for reading micro instructions from the CS 260 after the second micro instruction. The BA field of the second microinstruction, read from CS 260 using the BA field of the first microinstruction and set in CSDR 270, is
It holds the CS address of the third microinstruction to be executed next, and sets the BA field of the second microinstruction to CS
It is sent to AR250 and set, and the third microinstruction is set to C
Read from S260.

It is assumed that the above operation is repeated and the n-th micro instruction is read from CS 260 and set in CSDR 270. The n-th set in the CSDR 270
The BA field of the microinstruction contains the nth
Holds the CS address of the +1 microinstruction,
The BA field of the n-th microinstruction is stored in CSAR 250
, And sets the (n + 1) th micro instruction to CS26.
Read from 0 and set to CSDR 270. In the example of FIG. 3, the (n + 1) th microinstruction is the last microinstruction of the microcode processing procedure composed of a series of a plurality of microinstructions. EO of this last microinstruction
Since the value of the P field is set to ON, the CSD
R270 stores a BA field holding a microinstruction address to be executed next to the microinstruction in CSAR.
The value of the EOP field, which is ON, is transmitted to the IU 210 instead of being transmitted to the IU 210, and the operation of reading and decoding the next instruction of the IU 210 is started.

FIG. 5 shows a conventional information processing apparatus which implements instruction processing by using microcode. In the information processing apparatus, each instruction function is constituted by a microcode processing procedure comprising a plurality of microinstructions. FIG. 9 is a diagram illustrating an example of a description of an instruction in a CS.

FIG. 5A shows an example of a description in the case where the instruction A having a function of moving data between two storage areas of the main memory is realized by a combination of a plurality of microinstruction functions. The first address aa is specified in the setup of the IU.

Address aa: Micro instruction BOP
Causes the hardware in the EU to set the operand parameter of the instruction word required to start the instruction execution set up from the IU. In this example, the address of the storage area in the main memory at the source and destination of the data and the length of the data are I
It is set in hardware in the EU as a parameter of an operand of an instruction word that is U setup data. Thereafter, the process branches to the address ab.

Address ab: The micro instruction CC is
Clear the counter, which is hardware in the EU. Thereafter, the process branches to the address ac.

Address ac: The micro-instruction L transfers specified storage data in the EU using the source storage area address in the main storage of data set up in hardware in the EU by the micro-instruction BOP at the address aa. Load the hardware registers of Thereafter, the process branches to the address ad.

Address ad: The micro instruction ST is
Using the destination storage area address in the main memory of the data set up in the hardware in the EU by the microinstruction BOP at the address aa, the data loaded by the microinstruction L at the address ac into the hardware register in the EU is used. , In the designated main storage area. Thereafter, the process branches to the address ae.

Address ae: The micro instruction MC is
The counter holding the transferred data length, which is hardware in the EU, is updated using the value of the data length stored by the microinstruction ST at the address ad. afterwards,
Branch to address af.

Address af: The micro instruction TC is
A counter holding the transferred data length, which is the hardware in the EU updated by the microinstruction MC at the address ae, and the operand of the instruction word set in the hardware register in the EU by the microinstruction BOP at the address aa Compares with the specified data length. Thereafter, the process branches to the address ag.

Address ag: The micro instruction BC is
The result of the comparison at the micro-instruction TC at the address af is checked, and if the comparison result matches, the process branches to the address ak,
If they do not match, branch to address ah, which is the normal order of execution.

Address ah: The micro instruction MA is
EU used in microinstruction L at address ac
Update the source storage area address in the main storage of the data held in the hardware in the next to the source storage area address in the next main storage. Thereafter, the process branches to the address ai.

Address ai: The microinstruction MA is
E used in micro instruction ST of address ad
The destination storage area address in the main storage of the data held in the hardware in U is updated to the next destination storage area address in the main storage. Thereafter, the process branches to the address aj.

Address aj: The micro instruction BC is
This step is used for unconditionally branching to the address ac. Therefore, the process branches to the address ac, and then loops through the addresses ac to aj until a match is detected in the microinstruction BC at the address ag.

Address ak: Micro instruction EOP
Indicates the end of the execution of the processing procedure of a plurality of microinstructions constituting the currently executed instruction function, and sets the parameter of the operand necessary for starting the execution of the instruction following the currently executed instruction in the EU. In order to have the hardware set up, the IU initiates a setup operation for the EU. There is no branch operation by the microinstruction in this step.

FIG. 5B shows a description example in the case where the instruction B having the function of performing a data exclusive OR between two storage areas of the main storage is realized by a combination of a plurality of microinstruction functions. . Again, the first address ba is specified by the IU setup address.

Address ba: micro instruction BOP
Causes the hardware in the EU to set the operand parameter of the instruction word required to start the instruction execution set up from the IU. In this example, the address of the storage area in the main memory of the read source of the first data and the read source and the storage destination of the second data and the length of the data are the parameters of the operand of the instruction word which is the IU setup data in the EU. Set in hardware. Thereafter, the process branches to the address bb.

Address bb: The micro instruction CC is
Clear the counter, which is hardware in the EU. Thereafter, the process branches to the address bc.

Address bc: The micro-instruction L is the designated storage data (using the read-source storage area address in the main memory of the first data set up in the hardware in the EU by the micro-instruction BOP at the address ba). First data) is loaded into a hardware register in the EU. Thereafter, the process branches to the address bd.

Address bd: The micro-instruction L is the storage data (specified by the micro-instruction BOP of the address ba) using the storage area address of the read source and the storage destination of the second data set in the hardware in the EU in the micro instruction BOP of the address ba. Second
Data) into a hardware register in the EU. Thereafter, the process branches to the address be.

Address be: The micro instruction XR is
The exclusive OR of the first data loaded into the hardware register in the EU with the microinstruction L at the address bc and the second data loaded into the hardware register in the EU with the microinstruction L at the address bd is obtained. In a hardware register in the EU. Then, the address bf
Branch to

Address bf: The micro instruction ST is
Using the storage area addresses of the read source and the storage destination in the main memory of the second data set up in the hardware in the EU by the microinstruction BOP at the address ba, the hardware in the EU obtained by the microinstruction XR at the address be The result of the exclusive OR placed in the wear register is stored in the specified storage area in the main storage.

Thereafter, the flow branches to the address bg.

Address bg: The micro instruction MC is
The counter holding the processed data length, which is hardware in the EU, is updated using the value of the data length stored by the microinstruction ST at the address bf. Thereafter, the process branches to the address bh.

Address bh: The micro instruction TC is
The counter holding the processed data length, which is the hardware in the EU updated by the microinstruction MC at the address bg, and the length of the data set up in the hardware in the EU by the microinstruction BOP at the address ba Compare. Thereafter, the process branches to the address bi.

Address bi: The micro instruction BC is
The result of the comparison at the microinstruction TC of the address bh is checked, and if the comparison result matches, the process branches to the address bm,
If they do not match, branch to address bc, which is the normal execution order.

Address bj: The micro instruction MA is
The read source storage area address in the main storage of the first data held in the hardware in the EU used by the microinstruction L at the address bc is updated to the next read source storage area address. Thereafter, the process branches to the address bk.

Address bk: The micro instruction MA is
The storage area addresses of the read source and the storage destination of the second data in the main memory held in the hardware in the EU used in the microinstruction L of the address bd and the microinstruction ST of the address bf are changed to the next read source and Update to the storage destination storage area address. Thereafter, the process branches to the address bl.

Address bl: The micro instruction BC is
This step is used for unconditionally branching to the address bc. Therefore, branch to address bc,
Thereafter, the address bc to bl are looped until a match is detected by the microinstruction BC at the address bi.

Address bm: Micro instruction EOP
Indicates the end of the execution of the processing procedure of a plurality of microinstructions constituting the currently executed instruction function, and sets the parameter of the operand necessary for starting the execution of the instruction following the currently executed instruction in the EU. The setup operation from the IU is started to make the hardware set up. There is no branch operation by the microinstruction in this step.

As described above, in the information processing apparatus which realizes the instruction processing by the microcode of the prior art,
When an instruction function is realized by combining a plurality of functions of a plurality of micro-instructions, it is necessary to store a plurality of the same micro-instructions on different CS addresses. For example, as shown in FIG. 5, an instruction A having a function of performing data movement between storage areas and an instruction B having a function of performing an exclusive OR of data between storage areas are each combined with a plurality of microinstruction functions. If realized, BOP, CC, ST, M
The microinstructions C, TC, and EOP are used in two places, the microinstruction L is used in three places, and
The micro-instructions BC and MA are used in four places. In other words, 10 types of micro-instructions have 22 different CSs
The address is duplicated and stored.

Considering that the instruction word of the information processing apparatus usually consists of several hundred instructions, the same microinstruction can be replaced by a different C instruction.
Duplicate storage on the S address results in the requirement of a very large CS as compared to the number of microinstruction types.

The requirement for installing a large-capacity CS is that the word length of a microinstruction used by an information processing device is much longer than the instruction word length at the machine language level used by a normal information processing device. This causes an increase in the size of the physical CS, and this increase in the size of the physical CS results in the necessity of configuring the CS using a plurality of memory chips, and the The configuration using chips directly leads to an increase in the access time to the CS by the hardware of the information processing device, and the increase in the access time to the CS improves the performance of the information processing device that performs instruction processing under microcode control. This is an important issue that cannot be ignored when planning.

Further, in the case of realizing an information processing device which realizes instruction processing by microcode having a plurality of instruction architectures with a single processor, the problem that the above-mentioned extremely large capacity CS is required is several times. In reality, the physical limitations on the chip area of the processor have hindered the practical application of information processing equipment that implements instruction processing using microcode with multiple instruction architectures on a single processor, which can be ignored. There were no very serious technical barriers.

Next, a description will be given of a problem in the case where the present invention is applied to a multi-instruction architecture processor and an instruction reading and executing mechanism of an information processing apparatus which implements instruction processing by conventional hardware logic.

FIG. 9 is a block diagram showing an example of the configuration of an IU for reading and decoding instructions and generating a parameter group necessary for executing an instruction word in an information processing apparatus which implements instruction processing by conventional hardware logic. It is.

In FIG. 9, the IU 910 makes a request to read an instruction word in the main memory or the like, sets the read instruction word in the IR 911, and sends it to the IDEC 912. The IDEC 912 decodes the instruction code of the instruction word, and sends the instruction code, the instruction format, and other instruction decryption results to the DS 913. The DS 913 generates setup data based on the command decoding result of the command, and sends the setup data to the EU. The IU setup data sent from the DS 913 to the EU includes the operand address and operand data of the instruction to be executed, and the designation of the instruction execution type and instruction execution procedure required for the execution of the instruction.

The DS 913 is generally constituted by a storage device using an instruction code of each instruction word as an address parameter or by an encoder comprising an encoding logic circuit using the instruction code of each instruction word as input data. . In the case of a storage device having an instruction code of each instruction word as an address parameter, an IU setup data group corresponding to each instruction word supported by the instruction architecture of the instruction processor (information processing device) is stored in advance in the storage device. The IU setup data is generated by reading out the storage device. In the case where the encoder is constituted by an encoder composed of an encoding logic circuit using the instruction code of each instruction word as input data, an IU setup data group corresponding to each instruction word supported by the instruction architecture of the instruction processor is output. The encoding logic circuit is configured as described above, and the generation of the IU setup data is performed by directly using the output of the encoder as the IU setup data.

FIG. 10 is a diagram showing the relationship between the configuration of an information processing apparatus, an operating system operating thereon, and an application program when the information processing apparatus performs instruction processing of a single instruction architecture. In FIG. 10, on an instruction processor (hereinafter, referred to as IP) 1010, which is an information processing apparatus, an operating system (hereinafter, referred to as OS) 1020 having an instruction architecture basically supported by IP and control of the OS 1020 An arbitrary number of application programs (hereinafter, referred to as APGM) 1030 having the above-described instruction architecture are operating. This is the configuration of the basic operation mode of the information processing apparatus.

FIG. 11 shows an O operating on the information processing apparatus.
FIG. 6 is a diagram illustrating the relationship between an IP, an OS operating on the IP, and the configuration of an APGM when S and the APGM have a plurality of instruction architectures different from the instruction architecture basically supported by the IP; .

Generally, a method called a virtual machine (hereinafter referred to as a VM) is used as a method of operating an OS using instructions having a plurality of different instruction architectures on a single IP. In order to implement a VM on a single IP, a program called a virtual machine control program (hereinafter referred to as a hypervisor or a VMCP) is operated on the IP, and a VM having a plurality of different instruction architectures under the control of the hypervisor. And run an independent OS using instructions of different instruction architectures on each of the VMs. Therefore, the hypervisor is provided with a function of sharing a single IP hardware resource with each VM and using the same, and a function of executing instructions of different instruction architectures.

In FIG. 11, on the IP 1140,
The hypervisor 1130 whose instruction architecture type basically supported by the IP consists of a is operating. On this hypervisor 1130, the OSa 1120 whose instruction architecture type is a and the instruction architecture type are b. The OSb 1121 and an APGM group c1 which is a stand-alone type application program group whose instruction architecture type is c
125 is operating. On the OSa 1120, the APGM group a1110 whose instruction architecture type is a operates, and on the OSb1111, the APGM group ba111 whose instruction architecture type is b.
1 is working.

On the hypervisor 1130, the OSa 1120 whose instruction architecture type is a and the APGM
When the group a1110 operates, the OSa1120 and the AP
Most of the instructions issued by the GM group a1110 are IP111
10 are directly executable, but not directly executable are some instructions that affect interrupt handling and hardware resources. The above-described processing that cannot be directly executed is realized by passing control to the hypervisor 1130 using a means of interception, which is a form of interrupt, and simulating the control by the simulation function of the hypervisor 1130.

On the hypervisor 1130, the OSb 1121 whose instruction architecture type is b and the APGM
When the group b1111 operates, the OSb1121 and the AP
All instructions issued by GM group b1111 and I of interrupt
The above-described processing that cannot be directly executed by P1140 and cannot be directly executed is realized by passing control to the hypervisor 1130 by using a means of interception and simulating by the simulation function of the hypervisor 1130. . Similarly, the hypervisor 113
0, the AP whose instruction architecture type is c
When the GM group c1125 operates, the APGM group c11
It is impossible to directly execute all instructions and interrupts issued by the IP 25 by the IP 1140, and control is passed to the hypervisor 1130 using a means of interception, and the control is simulated by the simulation function of the hypervisor 1130.

Next, referring to FIG. 12 and FIG. 13, in a conventional information processing apparatus which implements instruction processing by hardware logic, a simulator or interpreter of a hypervisor executes instructions of different instruction architectures. An implementation method and configuration will be described.

FIG. 12 shows a program of the instruction architecture b supporting only the instruction architecture a.
FIG. 4 is a diagram illustrating a configuration of each functional module and a role of each functional module when the processing is executed by using an interpreter when executed by P.

In FIG. 12, a processing procedure 121 programmed with an instruction or instruction sequence of the instruction architecture b.
At the time of execution, 0 is divided into instructions or instruction steps of the instruction architecture b, which is the minimum unit suitable for execution, and input to the interpreter 1220. The input instructions or instruction steps of the instruction architecture b are interpreted by the interpreter 1220. It is translated into an instruction or instruction sequence of the instruction architecture a. The interpreter 1220 stores a translation procedure composed of an instruction sequence of the instruction architecture a.

The instruction or instruction sequence of the instruction architecture a translated by the interpreter 1220 is
The object code output from the instruction architecture 220 is stored in the data set 1240, and the data group of the instruction architecture b as an operand of the instruction or the instruction step of the instruction architecture b is translated into the data group of the instruction architecture a, and the data set 1250.
The interpreter 1220 further outputs, to the data set 1230, a linkage parameter group corresponding to an instruction or an instruction step of the instruction architecture b and a data group corresponding to the instruction architecture b during the translation. Furthermore,
The interpreter 1220 refers to the linkage parameter group corresponding to the instruction or the instruction step of the instruction architecture b stored in the data set 1230 and the data group corresponding to the instruction architecture b, and converts the data group corresponding to the instruction architecture b. The data set 125 is translated into a data group corresponding to the instruction architecture a.
Store to 0.

Next, the execution of the instruction is controlled by the interpreter 1.
The data is transferred from 220 to the object code stored in the data set 1240, and the IP 1260 executes predetermined instruction processing according to the processing procedure of the object code while referring to the data set 1240 and the data set 1250. When the execution of the instruction processing according to the processing procedure of the object code is completed, the execution control of the instruction is transferred from the object code stored in the data set 1240 to the interpreter 1220, and the execution of the data set 125 is started.
Instruction architecture a which is the result of the process stored in
Is translated into a data group corresponding to the instruction architecture b while referring to the linkage parameter group, and is used as a result operand of the instruction or instruction step of the instruction architecture b cut out in the processing procedure 1210.

FIG. 13 shows a program of the instruction architecture b supporting only the instruction architecture a.
FIG. 4 is a diagram illustrating a configuration of each functional module and a role of each functional module when the processing is performed by using a means serving as a simulator when the processing is performed in P;

In FIG. 13, a processing procedure 131 programmed by an instruction or an instruction sequence of the instruction architecture b.
At the time of execution, 0 is input to the simulator 1320 as an instruction of the instruction architecture b which is the minimum unit suitable for the execution, and the input instruction of the instruction architecture b is
Simulator 1320 provides instruction architecture a
And a sequence of instructions. Simulator 132
0 stores a translation procedure composed of an instruction sequence of the instruction architecture a. The translated instruction or instruction sequence of the instruction architecture a is an object code previously incorporated in the simulator 1320.

Simulator 1320 outputs a linkage parameter group corresponding to the instruction of instruction architecture b and a data group corresponding to the instruction architecture b to data set 1330 at the stage of executing the processing procedure. Further, the simulator 1320 includes the data set 13
And a linkage parameter group corresponding to the instruction of the instruction architecture b stored in the instruction architecture b.
The data group corresponding to the instruction architecture b is converted into a data group corresponding to the instruction architecture a and stored in the data set 1340 while referring to the data group corresponding to the instruction architecture b.

Next, the IP 1360
According to the processing procedure located in the data set 20,
A predetermined instruction process is executed with reference to 40.

In the latter half of the execution of the instruction processing of the simulator 1320 in accordance with the processing procedure of the object code, the simulator 1320 executes the instruction processing of a data group corresponding to the instruction architecture a, which is the result of the processing stored in the data set 1340. Inverse conversion is performed on the data group corresponding to the architecture b while referring to the linkage parameter group, and the result is used as a result operand of the instruction of the instruction architecture b extracted in the processing procedure 1310.

A case where the function of the simulator is implemented in a style in which IP1360 can be directly executed independently of the hypervisor is also called an emulator. The configuration and function of this emulator are almost the same as those of the simulator described above. With the configuration.

FIG. 14 shows a conventional information processing apparatus that implements instruction processing by hardware logic, in order to implement instruction processing of different instruction architectures, in the simulator or emulator processing procedure. Different instruction architecture 1 by combining multiple functions
3 shows an example of description of individual instructions in a storage device when executing one instruction function.

In FIG. 14, (1) shows a case where the instruction A of the instruction architecture b having a function of moving data between two storage areas of the main storage is realized by a combination of a plurality of instruction functions of the instruction architecture a. And (2)
Is an instruction B of the instruction architecture b having a function of performing an exclusive OR operation on data between two storage areas of the main storage,
This is an example in the case of being realized by a combination of a plurality of instruction functions of the instruction architecture a.

The individual instruction functions of the instruction architecture a in (1) and (2) of FIG. 14 and their roles are the same as those of the microinstructions in FIGS. 5 (1) and (2), and therefore description thereof is omitted. I do. For example, the instruction BOP of the instruction architecture a is basically the same as the micro-instruction BOP of FIG. 5, and the parameter of the operand of the instruction word necessary to start the instruction execution of the instruction A of the instruction architecture b set up from the IU. Let the hardware in the EU be set. The other instructions are the same.

As shown in FIG. 14, in an information processing apparatus in which instruction processing is realized by conventional hardware logic, instruction functions of different instruction architectures are combined with the functions of a plurality of instructions basically supporting the instruction functions. In such a case, it is necessary to store a plurality of identical instructions at different main memory addresses. For example, in FIG. 14, an instruction architecture b having an exclusive OR of an instruction A of the instruction architecture b having a function of moving data between storage areas and data between the storage areas.
Is realized by a combination of instruction functions of a plurality of instruction architectures a, BOP, CC, ST, MC, T
Instructions of the instruction architecture a of C and EOP are used at two places, instructions of the instruction architecture a of L are used at three places, and instructions of the instruction architecture a of BC and MA are used at four places. That is, instructions of 10 types of instruction architecture a are stored redundantly on 22 different main memory addresses, and the instruction words constituting the simulator or emulator of the information processing apparatus are usually
Considering that it consists of several hundred instructions, the result is that a very large main memory is required compared to the number of instruction types of the instruction architecture a.

When a simulator or emulator is incorporated in an information processing apparatus that implements instruction processing by hardware logic, instruction functions of different instruction architectures are combined by combining the functions of a plurality of basically supported instructions. However, the necessity of installing the large-capacity main memory is based on the fact that the number of instruction words of the simulator or emulator constituted by the basic instruction architecture a used by the information processing device is a machine language that the information processing device can directly execute. Since the number of instructions is extremely large compared to the number of instructions at the level, the size of the physical main memory is increased, and this increase in the size of the physical main memory is performed by using a large number of memory chips. The result is that the memory must be configured, and configuring the main memory using a large number of memory chips is not suitable for the main memory of the information processing apparatus. This increase in access time to the main memory is directly associated with an increase in access time, and this increase in access time to the main memory is an important problem that cannot be ignored in improving the performance of an information processing apparatus that realizes instruction processing of different instruction architectures under simulator or emulator control. Met.

Further, an information processing apparatus which realizes instruction processing by hardware logic executes an instruction processing of a different instruction architecture using a simulator or emulator in order to support a plurality of instruction architectures with a single processor. In realizing the device, the above-mentioned problem is manifested in a range of several times, and due to the physical limitation of the chip area of the processor, in order to support a plurality of instruction architectures with a single processor, instruction processing is actually performed by a simulator or emulator. This has prevented practical use of the information processing device to be realized, and this was also a very serious technical barrier that cannot be ignored.

[0073]

As described above, a conventional information processing apparatus which implements instruction processing by microcode uses a microinstruction stored in a control storage (CS) in a microcode processing procedure. , The microinstruction is temporarily set in the control storage data register, and is sequentially transmitted from the control storage data register to the execution unit that is responsible for executing the microinstruction. A method of performing a plurality of operations specified by a plurality of fields has been common.
Then, the generation of the CS address, the reading of the microinstruction and the repetition of the execution of the microinstruction have been realized by a structure in which a part of each microinstruction specifies the address of the microinstruction to be executed next. .

In the conventional information processing apparatus which realizes instruction processing by using microcode, a plurality of functions of a plurality of microinstructions are implemented in order to realize an instruction function at a machine language level used by the information processing apparatus. When the microcode processing procedure was programmed in combination, it was necessary to store a plurality of the same microinstructions on different CS addresses. That is, it is necessary to store a large number of micro-instructions in duplicate in the CS as compared with the number of types of micro-instructions. As a result, there is a problem that a large-capacity CS is required.

In addition, the word length of the microinstruction used by the information processing apparatus that realizes the instruction processing by the microcode is the machine language used by the information processing apparatus that realizes the instruction processing by the ordinary microcode. Since the instruction word length is generally extremely long compared to the instruction word length of the level, the requirement for installing a large-capacity CS leads to an increase in the size of a physical CS logic circuit, and this physical CS The increase in the size of
The CS has to be constructed using a plurality of memory chips, and the construction of the CS using a plurality of memory chips requires a hardware of an information processing apparatus that realizes instruction processing by the microcode. The increase in the access time to the CS by the hardware is directly associated with the increase in the access time to the CS, and the increase in the access time to the CS is a serious problem that cannot be ignored in securing the performance of the information processing apparatus that performs the instruction processing under the microcode control. And to achieve a processor that supports multiple instruction architectures,
There was a serious problem that could not be realized.

Further, the large increase in the physical CS logic circuit size is caused by the chip area of a large-scale integrated circuit, which is the most important component of an information processing apparatus that implements instruction processing by microcode. There is an industrial problem in the manufacture of industrial products that increases the manufacturing cost of information processing devices that implement instruction processing with microcode, and this industrial problem can be ignored. Absent,
It was a serious problem.

Next, the information processing apparatus which realizes the instruction processing by the conventional hardware logic reads out sequentially according to a predetermined procedure according to the processing procedure of the simulator or emulator stored in the main memory in advance. Has been generally sent to an execution unit that is responsible for executing the instruction, and the execution unit performs the operation of the processing procedure specified by the instruction group. The generation of the instruction address, the reading of the instruction, and the repetition of the execution of the instruction have been realized by an instruction address update control procedure used in a normal information processing apparatus.

In such an information processing apparatus that implements instruction processing by hardware logic, a plurality of functions of a plurality of instructions are implemented in order to implement an instruction function at a machine language level used by the information processing apparatus. When the simulator or emulator processing procedure is programmed in combination,
It was necessary to store a plurality of the same instructions at different main memory addresses. That is, an extremely large number of instructions must be stored in the main memory in duplicate as compared with the number of instruction types, and as a result, a large-capacity main memory for a simulator or emulator processing procedure is required. There was a problem.

In addition, when a simulator or emulator is incorporated in an information processing apparatus that realizes instruction processing by the hardware logic, a plurality of basic hardware supports instruction functions of different instruction architectures. And the number of instruction words of a simulator or emulator composed of a plurality of instruction architectures supported by the underlying hardware used by the information processing device can be directly executed by the information processing device. Since the number of instruction words at the machine language level is extremely large, the requirement for installing this large-capacity main memory is as follows:
This leads to an increase in the size of the physical main storage, and this increase in the size of the physical main storage results in the necessity of configuring the main storage using a large number of memory chips,
The configuration of the main memory using a large number of memory chips directly leads to an increase in the access time to the main memory of the information processing apparatus.
This is a serious problem that cannot be ignored in securing the performance of an information processing apparatus that performs instruction processing using such hardware logic, and is not feasible in realizing a processor that supports a plurality of instruction architectures. There was a serious problem that could be said.

Further, the large increase in the size of the physical main memory is caused by the number of memory chips, which are the most important components of an information processing apparatus that implements instruction processing with basically supported instructions. This is a serious problem that cannot be ignored because there is an industrial problem in manufacturing an industrial product that increases the manufacturing cost of the information processing device.

An object of the present invention is to provide an information processing apparatus which implements instruction processing by microcode, in which a structure in which a part of the microinstruction specifies an address of a microinstruction to be executed next is improved, and When the microcode processing procedure is incorporated into an information processing device by combining a plurality of functions of a plurality of microinstructions to realize a word level instruction function, a plurality of the same microinstructions are stored on different CS addresses. By eliminating the need, a processor that executes instruction processing with microcode that supports a plurality of instruction architectures, that is, a multi-instruction architecture processor can be realized, and further, the instruction processing performance of the hardware of the multi-instruction architecture processor And to reduce industrial costs.

A further object of the present invention is to provide an information processing apparatus which implements instruction processing by hardware logic.
A part of the instruction data of the instruction architecture basically supported by the hardware revises the structure for specifying the address of the next instruction to be executed, and realizes the machine language level instruction function of a different instruction architecture. Therefore, when the processing procedure is incorporated into an information processing device as a simulator or emulator by combining the functions of a plurality of instructions of the instruction architecture basically supported by the hardware, the same instruction is stored in different main memory addresses. A processor that can support a plurality of instruction architectures can be realized by eliminating the necessity of storing individual instructions, and a processor that executes instruction processing with hardware logic that supports a plurality of instruction architectures, that is, a multi-instruction architecture processor Can be realized, and That the multi-instruction significantly increases hardware instruction processing performance architecture processor, and is to suppress the industrial costs.

[0083]

SUMMARY OF THE INVENTION The present invention basically provides an information processing apparatus including an instruction control unit for reading and decoding instructions and an execution unit for executing instructions, and an architecture of an instruction to be processed. An instruction architecture mode register for holding a mode, a plurality of setup data generators for generating setup data required for instruction processing for each instruction architecture mode, and an instruction execution order for each instruction architecture mode There are provided a plurality of sequence memories for storing the sequence code sequence and an instruction memory for storing the instruction word group to be executed without duplication. When performing the instruction processing, one of the plurality of setup data generators is selected according to the output value of the instruction architecture mode register, and the decoding result of the instruction to be processed is determined by the selected setup data. As an input of a generation unit, setup data necessary for processing the instruction is obtained, and at least a part of the obtained setup data is set as a head read address of one of the plurality of sequence memories, and A sequence code sequence that defines the execution order of the processing target instruction is read from the storage, and the read sequence code sequence is set as a read address sequence of the instruction storage, and a command word group corresponding to the processing target instruction is read from the instruction storage. , To the execution unit.

As a result, by changing the value of the instruction architecture mode register, it is possible to execute instructions having different operation specifications for instructions having the same instruction code. A multi-instruction architecture processor that dynamically switches and executes instructions having different architectures can be easily realized.

Here, in an information processing apparatus which performs instruction processing under microcode control, each microinstruction is stored in a control storage so as not to be duplicated, and each sequence storage is stored in a sequence storage.
For each architecture mode of the instruction, a sequence code sequence that defines the execution order of the microinstructions stored in the control storage according to the type of the instruction may be stored.

Further, in an information processing apparatus that performs instruction processing under hardware logic control, only instruction words having a specific instruction architecture (an instruction architecture basically supported by the information processing apparatus) are stored in the instruction storage. In each sequence storage, a sequence code sequence that determines the execution order of the instruction words stored in the instruction storage according to the type of instruction may be stored for each instruction architecture.

[0087]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the information processing apparatus according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an information processing apparatus for performing an instruction process under microcode control according to the present invention. In particular, FIG. 1 shows an entire configuration of a portion related to reading and execution of a microinstruction. .

In FIG. 1, 100 is a main memory (MS),
110 is an instruction control unit (IU), 120 is an SSAR group composed of a plurality of sequence storage address registers (hereinafter, referred to as SSARs), 130 is an address adder,
Reference numeral 40 denotes an SS group including a plurality of sequence storages (hereinafter, referred to as SS), and 150 denotes a control storage address register (CS).
AR), 160 is a control storage (CS), 170 is a control storage data register (CSDR), and 180 is an execution unit (EU). The conventional configuration shown in FIG.
20; an address adder 130; and an SS group 140. The IU 110 further includes a plurality of setup data generators (DS).

The information processing apparatus according to the present invention further includes an instruction architecture mode register for holding an instruction architecture mode, but is omitted in FIG. Also, in FIG. 1, the instruction reading of the IU 110 is performed by MS
However, it may be a buffer storage or an instruction buffer.

As shown in FIG. 3, the IU 110 has an instruction register (IR), an instruction decoder (IDEC), a setup data generator (DS), and the like.
A plurality of Ss are provided for different instruction architectures.
In FIG. 1, this is indicated by a DS group 113. The IU110
Sends a command read request to the main memory 100, sets the read command in IR, and sends the set command to IDEC. The IDEC decodes the instruction code of the instruction word, and sends the instruction decryption result to the DS group 113 including a plurality of DSs. DS group 113
Is a group of SSs 14 storing a head sequence code corresponding to the instruction word based on the instruction decoding result of the instruction word.
0 (hereinafter referred to as a sequence code address), and the SSAR group 12
Send to 0. Specifically, DS (i) of the DS group 113
Creates a sequence code address corresponding to SS (i) of the SS group 140 and sends it to SSAR (i). Here, i = 0, 1,..., N. Furthermore, DS group 1
13 creates a CS address of the first microinstruction corresponding to the instruction word depending on the decoding result, and sends it directly to the CSAR 150 via the signal line 12.

The SSAR group 120 includes a plurality of SSARs corresponding to the DS group 113 of the IU 110.
(I) (i = 0, 1,..., N) is the SS transmitted from DS (i) of the DS group 113 via the signal line 11.
A sequence code address designating the address of the sequence code of (i) is set once, a read request is sent to SS (i) of the SS group 140 described later via the signal line 13, and the address adder 130 is sent to the address adder 130. Then, the sequence code address is sent. In addition, SSAR
Each SSAR (i) of the group 120 includes an address adder 130 described later, SS (i) of the SS group 140, and a CSDR 170.
For example, a sequence code address designating the same SS (i) address sent via the signal line 14, the signal line 15, or the signal line 20 is set, and the SS code is set via the signal line 13. Corresponding SS (i) of group 140
To the address adder 13
0 has the role of transmitting the sequence address.

The address adder 130 is provided for the SSAR group 12
0, and updates the value of the sequence code address sent from the SSAR (i) of the SSAR group 120 via the signal line 13, and updates the SSAR value via the signal line 14.
(I). With this, SSAR
Each SSAR (i) in group 120 then uses the updated sequence code address value to
(I), and sends the updated sequence code address to the address adder 13 at the same time.
Send to 0. Hereinafter, this is repeated.

The SS group 140 is composed of a plurality of SSs corresponding to the SSAR group 120. Each SS (i) of SS group 140
(I = 0, 1,..., N) respectively store a plurality of sequence codes specifying the micro-instruction address of the CS 160, and store the corresponding SSARs of the SSAR group 120.
Reading the designated sequence code by the read request accompanied by the sequence code address from (i),
The signal is sent to the SSAR 150 via the signal line 15. Furthermore,
Each SS (i) of the SS group 140 is EO described later.
When a sequence code in which the value of the P field or PEOP field is ON is read, the EOP or PEOP
The value of the OP field is transmitted to the corresponding SSAR (i) of the IU 110 and the SSAR group 120 via the signal line 19. In response, the IU 110 starts reading the next instruction, decoding it, and creating a sequence code address, etc., and the SSAR (i) is
The next sequence code address updated in
The transmission to the corresponding SS (i) of 40 is suppressed.

CSAR 150 receives the sequence code sent from SS (i) in operation of SS group 140,
Once set, a read request is issued to CS 160 via signal line 16 using the set sequence code as a read address of CS 160. Also, in some cases, the CSAR 150 may use the DS
After directly receiving the microinstruction address sent from the group 113 and once setting it, the CS160 is also transmitted via the signal line 16 using the set microinstruction address.
Issues a read request to.

The CS 160 stores a plurality of micro-instructions each having a unique function, reads a target micro-instruction using the sequence code or micro-instruction address sent from the CSAR 150, and reads the read micro-instruction (micro-instruction data). ) Is sent to CSDR 170 via signal 17.

The CSDR 170 receives the microinstruction read from the CS 160 according to the above-described procedure, sets the microinstruction once, and then transmits the set microinstruction to the signal line 1.
8 to the EU 180. Also, CSDR1
70 sends the contents of the BA field of the microinstruction to the SSAR group 120 via the signal line 20 as needed, so that the sequence code can be used for the sequence code to be read next to the SS group 140. Micro instruction E
The contents of the OP field are sent to the IU 110,
It has a role to start reading of the next instruction at 10. As indicated by the broken line, if necessary, the contents of the BA field of the microinstruction can be directly used for the read address of the CS 160 as in the conventional case.

FIG. 6 is a diagram showing the format and contents of one sequence code entry stored in each SS of the SS 140 group. Here, one sequence code entry is composed of four fields: a code type field 601, an address field 602, a PEOP field 603, and an EOP field 604.

[0098] The code type field 601 of the sequence code entry stores a flag designating the type of the address field 602 of the sequence code entry. Further, the field 601 also stores information for recognizing the type of the microinstruction in the corresponding CS.

The address field 602 stores the address of the microinstruction in the CS 160 corresponding to the sequence code entry or the address of the next sequence code entry to be read. Which address information is held in the address field 602 is determined by the flag of the code type field 601. If the address field 602 is the address of the next sequence code entry to be read,
The content of the address field 602 is the SSAR group 120
Is used as an address of a sequence code entry to be read next, and the reading order of the sequence code entries is changed.

In the EOP field 603, a flag indicating the end of the execution of the microcode processing procedure composed of a series of sequence code entries is set. The EO
When a sequence code entry in which the value of the P field 603 is on is read from the active SS (i) of the SS group 140, the value of the EOP field that is on is IU1
10 and the corresponding SSAR (i) of the SSAR group 120. In response, the SSAR group 120 SSAR
(I) suppresses transmission of the next sequence code address to the corresponding SS (i) of the SS group 140. IU110
Reads and decodes the next instruction, and newly creates a DS group 11
3, a DS corresponding to the architecture of the instruction is selected, and in the DS, a leading sequence code entry address corresponding to the instruction is created, and the SSAR group 120 is created.
To the corresponding SSAR, and starts reading the sequence code of the next instruction.

In the PEOP field 604, a flag is set which indicates the pseudo end of the execution of the microcode composed of a series of sequence code entries. The P
When the sequence code entry in which the value of the EOP field 604 is ON is read from the operating SS (i) of the SS group 140, the execution of the microcode composed of a series of sequence code entries is not completed. The value of the PEOP field 604 is similarly set to IU11
0 or the corresponding SSAR in the SSAR group 120.
The operation of the SSAR (i) and the IU 110 upon receiving this is the same as in the case of the EOP field 603.

FIG. 7 shows an instruction register (IR), an instruction decoder (IDEC) and a DS
FIG. 3 is a block diagram illustrating details of hardware related to microinstruction address generation, such as a group, an SSAR 120 group, an SS group 140, and an instruction architecture mode register (hereinafter, referred to as IAMR).

In FIG. 7, an IR 111 is a register for temporarily buffering an instruction word read from the main memory or the like. The IR 111 is connected to the main memory 100 or the like via a signal line 701 and via a signal line 702. It is connected to IDEC 112. The IDEC 112 is a decoder that receives the command sent from the IR 111, decodes the command code of the command, and sends the command code, the command format, and other command decoding results to the DS group 113. And IR11 via the signal line 703, respectively.
1 and the DS group 113.

IAMR 115 is a register for holding a value that defines the instruction architecture of an information processing device that performs instruction processing under microcode control. A value that defines the instruction architecture is input via signal line 700. Via the EU 180 and DS group 11 respectively
3 and is connected to. By changing the value of the IAMR 115, while having the same instruction code,
Instruction processing with different operation specifications can be executed.

The DS group 113 includes DS (0) 113-0,
DS (1) 113-1,..., DS (n) 113-n
Any one DS of the DS group 113 is selected according to an instruction decoding result of the instruction word decoded by the IDEC 112 and a value defining an instruction architecture sent from the IAMR 115. DS113-0 to 11
3-n indicates the corresponding S of the SS group 140 based on the instruction decoding result of the instruction word corresponding to each instruction architecture.
A sequence code address which is an address storing the leading sequence code corresponding to the instruction word of S or a micro instruction address of the CS 160 is created directly. Further, the DSs 113-0 to 113-n create the operand address and operand data of the instruction word to be executed and control information necessary for executing the microcode. These DSs 113-0 to 113-n are connected to the signal line 70.
3, IDEC 112, IAMR1 via signal line 704
15 and the CSAR 150 and the EU 18 via a signal line 705 (corresponding to 12 in FIG. 1) and a signal line 706.
0, and further, the signal lines 707-0 to 707-n
(Corresponding to 11 in FIG. 1) via SSAR group 1
20 corresponding SSARs.

The SSAR group 120 includes SSAR (0) 120-0 and SSAR (1) 12 corresponding to the DS group 113.
0-1,..., SSAR (n) 120-n,
DS (0) 113− corresponding to each DS group 113
0, DS (1) 113-1,..., DS (n) 113
Set the sequence code address sent from -n once, and send a read request to the corresponding SS in the SS group 140. Each of the SSARs 120-0 to 120-n is connected to a D line via a signal line 707-0 to 707-n (11 in FIG. 1).
Connected to the corresponding DS of the S group 113, and
08-0 to 708-n (corresponding to 13 in FIG. 1)
It is connected to the corresponding SS of the S group 140. Furthermore, SSA
In R120-0 to 120-n, as shown in FIG.
The input / output lines with the address adder 130, the output lines of the SS group 140, the output lines of the CSDR 170, and the like are connected, but are omitted in FIG.

The SS group 140 includes the DS group 113 and the SSA
Similarly for the R group 120, SS (0) 140-0,
SS (1) 140-1,..., SS (n) 140-n
Consists of Each of these SSs 140-0 to 140-n is a storage device for storing a plurality of sequence codes specifying the micro-instruction address of the CS 160.
SSAR (0) 120- corresponding to each of AR 120
0, SSAR (1) 120-1,..., SSAR
(N) In response to a read request accompanied by a sequence code address from 120-n, the designated sequence code is read and transmitted to a signal line 709 (corresponding to 15 in FIG. 1). Each SS 140-0 to 140-n is connected to a signal line 708-
SSAR group 12 through 0-708-n (13 in FIG. 1)
0 and connected to the corresponding SSAR
(15 in FIG. 1) is commonly connected to the CSAR 150.

Next, referring to FIG. 1 and FIG. 7, a case where the information processing apparatus which executes the instruction processing under the present microcode control is operated as a multi-instruction architecture processor will be described.
DS, SS related to reading and execution of microinstruction
An example of a procedure for selecting an AR group and an SS group will be described.

The multi-instruction architecture processor
Prior to starting the processing of the instruction word, the value of the architecture mode of the instruction is set to the IAMR 115 via the signal line 700. This instruction architecture mode is prepared, for example, in a program status word (PSW), and
What is necessary is just to set to AMR115. Then, IU110
Sends an instruction read request to the main memory 100 or the like, sets the read instruction in the IR 111,
The set command is sent to the IDEC 112. I
The DEC 112 decodes the instruction code of the instruction word, and decodes the instruction decoding result into DS (0) 113-0 and DS (1) 11.
3-1 to DS (n) 113-n.

On the other hand, the signal line 700 is connected to the IAMR 115.
Are sent to the EU 180 via a signal line 704, and the DS (0) 113-0 and DS (1) 113-
DS group 11 consisting of 1,..., DS (n) 113-n
3 and one DS is selected. For example, IA
If the value of the architecture mode of the instruction set in MR 115 is “0”, DS (0) 113-0 is selected, and if the value of the architecture mode is “1”, DS (1) 113- is selected. 1 is selected, and if the value of the architecture mode is "n", DS (n)
113-n is controlled to be selected.

DS (0) 1 forming DS group 113
13-0, DS (1) 113-1,..., DS (n)
113-n include SSAR group 120 and SS group 1 respectively.
SSAR (0) 120-0 and SS (0) 1 at 40
40-0, SSAR (1) 120-1 and SS (1) 14
0-1,..., SSAR (n) 120-n and SS
(N) 140-n are associated with each other, and store sequence code addresses and sequence codes of different instruction architectures.

The selected DS (i) 1 in the DS group 113
13-i, when it is determined that the instruction word uses a sequence code from the architecture value of the instruction word output from the IAMR 115 and the instruction decoding result sent from the IDEC 112, the corresponding SS (i) 140-i An address (sequence code address) storing the first sequence code corresponding to the instruction word is assigned to signal line 7.
07-i. The IU setup data generated by the DS includes, in addition to the sequence code address,
There are operand addresses, operand data, control information, and the like of the instruction, which are sent to the EU 180 via the signal line 706. SSAR of SSAR group 120
(I) 120-i sets the sequence code address output from the DS (i) 113-i to the signal line 707-i once, and then sets the sequence code address via the signal line 708-i to the SS group 140-i. SS (i) 140-
to i. The SSAR (i) 120-i sends the sequence code address to the address adder 130, and receives the updated sequence code address from the address adder 130. Hereinafter, this is repeated.

The SS (i) 140-i of the SS group 140 is
The target sequence code is read using the sequence code address from the SSAR (i) 120-i, and the CSAR 15 is read via the signal line 709 (15 in FIG. 1).
Send to 0. CSAR 150 is the SS of SS group 140
(I) Receives the sequence code read from 140-i, sets it once, and issues a read request to CS 160 using the set sequence code.

On the other hand, the selected D in the DS group 113 is selected.
S (i) 113-i is the value of the architecture mode of the instruction word output from the IAMR 115 and the IDEC 112.
When it is determined from the instruction decoding result sent from the terminal that the instruction word does not use the sequence code, the signal line 707-
i does not output the sequence code address, but instead replaces the first microinstruction address corresponding to the instruction word with
CSAR 15 via signal line 705 (1002 in FIG. 1)
Send directly to 0. The CSAR 150 receives the microinstruction address, sets it once, and issues a read request to the CS 160 using the set microinstruction address. In this case, the selected DS (i) 113
-I corresponding to SSAR (i) 120-i and SS (i)
The operation of 140-i is suppressed.

The CS 160 reads a target microinstruction using the sequence code or the microinstruction address sent from the CSAR 150, and reads the CSDR.
Send to 170. The CSDR 170 receives the micro-instruction (micro-instruction data) read from the CS 160, and once sets, sends the set micro-instruction to the EU 180.
SSAR (i) 120-i of 110 or SSAR group 120
Send to

Next, referring to FIG. 8, the multi-instruction architecture processor of the information processing apparatus for performing instruction processing under microcode control according to the present invention has a function of an instruction word composed of a plurality of sequence codes and a plurality of microinstructions. The description frequency of each microinstruction in the CS in the case of realizing by a microcode processing procedure will be described.

FIG. 8 shows a plurality of sequence codes and a plurality of instructions corresponding to individual instructions when the instructions A and B in FIG. 5 are realized by combining a plurality of functions of a plurality of sequence codes and a plurality of microinstructions. FIG. 3 is a diagram showing a combination of the microinstruction functions of FIG.

In FIG. 8, (1) shows an example showing a programming order when an instruction A having a function of moving data between storage areas is realized by a combination of a plurality of sequence codes and a plurality of microinstruction functions. It is. this is,
It has the same function as the instruction shown in (1) of FIG. (2)
Is an example showing a programming order when an instruction B having a function of performing an exclusive OR of data between storage areas is realized by a combination of a plurality of sequence codes and a plurality of microinstruction functions. This has the same function as the instruction shown in (2) of FIG. (3) is a diagram showing an arrangement state of a plurality of micro-instructions used in the instructions A and B on the CS.

The individual micro-instruction functions and their roles for (1) and (2) in FIG. 8 have already been described in the description of (1) and (2) in FIG. 5 and will not be repeated here.

As shown in FIG. 8A, the microcode processing procedure for executing the instruction A is as follows:
For example, in SS (i) 140-i of 40, a plurality of sequence codes stored in a continuous area starting from a sequence code address a are described. in this case,
In the microcode processing procedure, the first sequence code address a is generated by DS (i) 113-i,
(I) The sequence code is sequentially extracted from 140-i in the ascending direction of the sequence code address a, and the microinstruction indicated by the microinstruction address designated by the sequence code is read from the micro instruction in the CS 160 shown in (3) of FIG. This is realized by sequentially fetching from the instruction arrangement and sequentially executing the fetched microinstructions by the EU 180.

Similarly, as shown in FIG. 8B, the microcode processing procedure for executing the instruction B is as follows.
For example, in the SS group 140, for example, SS (i) 140-i is described as a plurality of sequence codes stored in a continuous area starting from the sequence code address b. In this case, the microcode processing procedure is DS (i) 11
In 3-i, a leading sequence code address b is generated,
A sequence code is sequentially extracted from the SS (i) 140-i in the ascending direction of the sequence code address b, and the microinstruction indicated by the microinstruction address designated by the sequence code is similarly CS1 shown in (3) of FIG.
This is realized by sequentially fetching the micro-instructions from the micro-instruction arrangement in 60 and sequentially executing the fetched micro-instructions by the EU 180.

As shown in FIG. 8, by using the SS group 140, ten micro-instructions used in the instructions A and B may be stored in the CS 160. That is, there is no need to store a large number of microinstructions in the CS redundantly in comparison with the number of types of microinstructions. Instead, it is necessary to store the sequence code in the SS group. However, the number of fields of the sequence code is much smaller than the number of fields of the microinstruction. The disadvantages of using groups are not as much of a problem. In general, in order to execute instruction processing having different operation specifications for instructions having the same instruction code, sequence groups of different combinations and execution orders may be stored in the SS groups. Only the sequence code string is stored in the SS group, and the SS group can be reduced in size and speed.

In the above description of the embodiment, the case where the address of the microinstruction is designated by the sequence code has been exemplified. However, as shown by the broken line in FIG. 1, the microaddress is designated by using the branch address field in the conventional microinstruction. It goes without saying that it may be used in combination with the method of designating the address of the instruction.

Next, a description will be given of an embodiment of an information processing apparatus for performing an instruction process under hardware logic control according to the present invention.

FIG. 15 is a block diagram showing an embodiment of an information processing apparatus according to the present invention which executes instruction processing of an instruction having a different instruction architecture under the control of a simulator or an emulator under the control of hardware logic. In particular, FIG. It shows the overall configuration of the part related to execution.

In FIG. 15, 1500 is the main memory (M
S) and 1510 are an instruction control unit (IU) related to reading and execution of an instruction of an architecture basically supported by the information processing device, 1520 is an SSAR group including a plurality of sequence address registers (SSAR),
Reference numeral 1530 denotes an address adder, 1540 denotes an SS group including a plurality of sequence stores (SS), 1560 denotes an instruction store (IS), and 1570 denotes an instruction modification conversion unit (IM).
U) and 1580 are execution units (EU), and 1590 is a group of register files.

The MS 1500 is a storage device for storing a group of programs having one or more instruction architectures.
10, SS group 1540 and IS 1560. Further, MS 1500 is connected to EU 1580 via signal line 15008. In addition, MS1500
Is connected to the EU 1580 via a signal line 15008.

The IU 1510 basically includes the IR, IDEC, and DS shown in FIG. 9, but a plurality of DSs are provided for different instruction architectures. FIG.
Then, this is indicated by DS group 1513. IU1510
A command read request is sent to the main memory 1500, the read command is set in the IR, and the IDEC is read.
To send to. IDEC 1612 decodes the instruction code of the instruction word, and outputs the instruction decryption result to a D
It is sent to the S group 1513. The DS group 1513 is a device that generates setup data corresponding to the instruction word based on the instruction decoding result of the instruction word, and the setup data stores a leading sequence code corresponding to the instruction word. A sequence code address of the SS group 1540 is included. IU 1510 is connected to signal lines 15002, 150
09 respectively via SSAR group 1520 and IMU1
570 and the EU via a signal line 15010.
1580.

[0129] The SSAR group 1520 is the DU of the IU 1510.
It comprises a plurality of SSARs corresponding to the S group 1513. The S
The SAR group 1520 is connected to the SS group 1540 and the address adder 1530 via a signal line 15003, respectively.

The address adder 1530 is connected to the signal line 150
03 and the SSAR group 1520 via the signal line 15012
It is connected to the. The address adder 130 has an SSA
SSA with SSAR group 120 shared by R group 120
It has the role of updating the value of the sequence code address sent from R via the signal line 15003 and returning it to the SSAR via the signal line 15012. As a result, each SSAR in the SSAR group 120 next sends a read request to the corresponding SS in the SS group 140 with the updated sequence code address value, and at the same time, adds the updated sequence code address to the address. Table 13
Send to 0.

The SS group 1540 includes a plurality of SSs corresponding to the SSAR group 1520. The SS group 1540
S1560 is a storage device for storing a plurality of sequence codes specifying respective instruction addresses of an instruction group of an instruction architecture which is basically supported by the information processing device, and includes a sequence code address from the SSAR group 1520. Read request with
Reads the specified sequence code. SS group 15
40 is connected to IS 1560 via signal line 15004 and IMU 1570 via signal line 15005
It is connected to the.

The IS 1560 is a storage device that stores an instruction group (instruction word group) of an instruction architecture basically supported by the information processing apparatus.
The target instruction word is read using the sequence code address sent from 0 as the instruction address. The IS15
60 is connected to IMU 1570 via signal line 15006, and further connected to IU 1510 via signal line 15007.
Connected to.

The IMU 1570 is an instruction modification conversion unit that generates instruction data so that the EU 1580 can actually execute the function specified by the instruction.
The command code data read from the I / O unit is received via the signal line 15006, and the contents of the sequence code transmitted from the SS group 1540 via the signal line 15005 and the setup data transmitted from the IU 1509 via the signal line 15010 And modifies and converts data in an arbitrary field of the command data. The IMU15
70 is connected to the IU 1510 via the signal line 15007, and sends the modification result to the IU 1510.

An EU 1580 is an operation execution unit that executes an instruction from IU setup data including an execution condition of the instruction sent from the IU 1510. Operand data used for the execution of the operation includes a main storage 1500 and a register file group. Access and get 1590. The register file group 1590 is a register group prepared in the IP, and includes an operand register that can be specified by an instruction word and a temporary register temporarily used by hardware.
It is connected to the.

FIG. 16 shows the IR 15 of the IU 1510 relating to the reading and execution of the instruction word of the architecture basically supported by the information processing apparatus, out of the configuration of FIG.
FIG. 11 is a block diagram showing details of hardware of a part including 11, IDEC 1512, DS group 1513, SSAR group 1520, SS group 1540, and IAMR 1600.

In FIG. 16, IR 1511 is connected to main memory 1500 via signal line 15001, and IR 1511
The instruction sequence read out from 500 is stored. The IR1
Reference numeral 511 denotes an IDEC 1512 via a signal line 16011.
And IDEC 1512 are connected via signal line 16012 to DS (0) 1513-0 and DS (1) 15 respectively.
13-1,..., DS group 1 of DS (n) 1513-n
513. On the other hand, a value defining the instruction architecture of the instruction sequence read from the MS 1500 is input to the IAMR 1600 via the signal line 16001. The IAMR 1600 is connected to the EU 1580 and DS (0) 1513- via a signal line 16002, respectively.
0, DS (1) 1513-1,..., DS (n) 15
13-n DS group 1513.

DS (0) 1513-0, DS (1) 15
13-1,..., DS (n) 1513-n
The S group 1513 stores one of the ones according to the instruction decoding result of the instruction word decoded by the IR 1511 and the value defining the instruction architecture sent from the IAMR 1600.
DSs are selected. Each DS generates the setup data of the instruction word based on the instruction decoding result of the instruction word corresponding to the instruction architecture. The setup data stores the leading sequence code corresponding to the instruction word. Each corresponding S
A sequence code address which is an address corresponding to one SS in the S group 1640 is included. DS group 151
3 are connected to IMU 1570 and EU 1580 via signal lines 15009 and 15010, respectively.
DS (0) 1513-0, DS forming S group 1513
(1) 1513-1,..., DS (n) 1513-n
Are the signal lines 15002-0, 15002-1,.
.., SSA via signal line 15002-n
SSAR (0) 1520-0 forming R group 1520;
SSAR (1) 1520-1,..., SSAR (n)
1520-n.

SSA forming SSAR group 1520
R (0) 1520-0, SSAR (1) 1520-1,
, SSAR (n) 1520-n is connected to the signal line 150.
.., Signal line 15
002-n via DS (0) 1513-
0, DS (1) 1513-1,..., DS (n) 15
13-n, the sequence code address sent from SS-n is set once, and the SS forming the SS group 1540 is set.
(0) 1540-0, SS (1) 1540-1, ...
., SS (n) 1540-n is an address register that has a role of issuing a read request. SSAR (0) 1
520-0, SSAR (1) 1520-1,..., S
The SAR (n) 1520-n is connected to the signal line 1500
3-0, signal line 15003-1, ..., signal line 150
SS (0) 1540-0, SS (1) via 03-n
, SS (n) 1540-n.

SS (0) forming SS group 1540
1540-0, SS (1) 1540-1,..., SS
(N) Each of 1540-n is a storage device for storing a plurality of sequence codes specifying instruction addresses of instruction words of an instruction architecture which is basically supported by the information processing device and stored in IS1560. Yes, SSAR (0) forming SSAR group 1520
1520-0, SSAR (1) 1520-1,...
In response to a read request with a sequence code address from SSAR (n) 1520-n, the specified sequence code is read and sent to IS 1560. The SS
(0) 1540-0, SS (1) 1540-1, ...
, SS (n) 1540-n are connected to the signal line 15
IS1560, IMU15 via 004, 15005
70.

FIG. 17 is a diagram for explaining the format and contents of one sequence code entry stored in the SS group 1540. One sequence code entry has a code type field 1701, an address field 17
02, the PEOP field 1703, the PEOP field 1704, and the modification parameter field 1705-5
It consists of two fields.

In the code type field 1701 of the sequence code entry, a flag defining the contents of the address field 1702 of the sequence code entry is stored. Further, this field 1701 contains
Information for recognizing the type of the corresponding command word in S1560 is also stored.

The address field 1702 stores the address of the instruction word in the IS 1560 corresponding to the sequence code entry or the address of the sequence code entry to be read next. Which of the above address information the address field holds is determined by the flag of the code type field,
If the address field is the address of the next sequence code entry to be read, the contents of the address field are used as the address of the next sequence code entry. This is used to change the reading order of the sequence code entry.

In the EOP field 1703, a flag indicating the end of the processing procedure of the simulator or emulator composed of a series of sequence code entries is set. That is, when a sequence code entry in which the value of the EOP field of the sequence code entry is ON is read, the value of the EOP field which is ON is immediately sent to the IU 1510 (in FIG. 15, this path is omitted). The IU group 1510 reads and decodes instruction words having different instruction architectures, creates a sequence code entry address of the first SS group 1540 corresponding to the instruction, sends it to the SSAR group 1520, and sends the next instruction sequence. Activate code reading.

In the PEOP field 1704, a flag is set which indicates a pseudo end of the processing procedure of the simulator or emulator which is composed of a series of sequence code entries. That is, the P of the sequence code entry
When a sequence code entry in which the value of the EOP field is ON is read, the value of the PEOP field is immediately stored in the IU group 1510 even if the processing procedure of the simulator or emulator composed of a series of sequence code entries has not been completed. Sent, IU group 1510
Reads and decodes the next instruction having a different instruction architecture, and reads the first SS group 154 corresponding to the instruction.
Create a sequence code entry address of SSA
It is sent to the R group 1520 to start reading the sequence code of the next instruction.

In the modification parameter field 1705,
A modification parameter used to modify or change an instruction read from the IS 1560 specified by the address field of the sequence code entry is stored. This modification parameter is the signal line 15005
And is used to modify and convert data in any field of the command data read from the IS 1560.

Next, with reference to FIGS. 15 and 16, how the instruction processing of an instruction having a different instruction architecture in the simulator or emulator processing procedure is performed in the information processing apparatus of the present invention will be described.

In FIG. 15 and FIG. 16, the information processing apparatus sets the value of the instruction architecture mode to be processed to the IAMR 1600 on the signal line 16 before starting the processing of the instruction word.
Set via 001. After that, the IU 1510 sends a command word read request to the main memory 1500,
The read instruction is set in the IR 1511, the set instruction is sent to the IDEC 1512, and the I
The DEC 1512 decodes the instruction code of the instruction word,
DS (0) 1513-0, DS
(1) 1513-1,..., DS (n) 1513-n
To the DS group 1513 consisting of

A signal line 160 is connected to the IAMR 1600.
01, the value of the instruction architecture mode of the instruction word set via EU1580 via signal line 16002
And DS (0) 1513-0, DS
(1) 1513-1,..., DS (n) 1513-n
Is transmitted to the DS group 1513 comprising the IAMR1
One DS corresponding to the value of the instruction architecture mode of 600 is selected. For example, if the value of the instruction architecture mode of the instruction word set in the IAMR 1600 is'
If 0, DS (0) 1513-0 is selected, and if the value of the instruction architecture mode is '1', D (0) 1513-0 is selected.
S (1) 1513-1 is selected, and if the value of the instruction architecture mode is 'n', DS (n)
1513-n is controlled to be selected.

DS (0) constituting DS group 1513
1513-0, DS (1) 1513-1,..., DS
(N) 1513-n has SSAR (0) 15
20-0 and SS (0) 1540-0, SSAR (1) 1
520-1, SS (1) 1540-1, ..., SSA
R (n) 1520-n and SS (n) 1540-n are associated with each other, and the respective DS and SS store sequence code addresses and sequence codes of different instruction architectures.

The sequence code address, which is the output of the target DS (i) 1513-i selected from the DS group 1513, corresponds to one corresponding SS in the SSAR group 1520.
AR (i) 1520-i and SS group 1540
Is input to one SS (i) 1540-i corresponding to the DS (i) 1513-i, and a target sequence code is read. The code type and address field of the read sequence code are sent to IS 1560 via signal line 15004, and the modification parameter field is sent to IM 1500 via signal line 15005.
It is sent to U1570.

The IS 1560 is based on the SS (i) 1540
The target instruction word is read using the sequence code sent from -i as the instruction address, and the read instruction data is sent to the IMU 1570.

IMU 1570 receives the instruction data read by IS 1560 and, based on the contents of the sequence code (modification parameter) sent from SS (i) 1540-i, stores the data in an arbitrary field of the instruction data. To generate instruction data in a format executable by EU 1580, that is, instruction data in a format of an instruction architecture basically supported by the information processing apparatus, and convert the instruction data into a signal. Send to IU 1510 via line 15007.

When the IU 1510 receives the command data from the IMU 1570, the IU 1510 sets the command in the IR 1511 as if it were read from the MS 1500, sends the set command to the IDEC 1512, and , Decodes the instruction code of the instruction word, and sends the instruction decryption result to the DS group 1513,
DS (i) 1513-i of the DS group 1513 is an execution parameter of an instruction corresponding to the instruction word, which is an execution parameter of the instruction corresponding to the instruction word, based on the instruction decoding result of the instruction word. It generates IU setup data such as operand address, operand data, and designation of an instruction execution type and an instruction execution procedure required for the execution of the instruction.
10 to the EU 1580.

On the other hand, for the instruction read from MS 1500, DS (0) 1 forming DS group 1513
513-0, DS (1) 1513-1,..., DS
(N) 1513-n is the value of the instruction architecture mode which is the output of the IAMR 1615 and the IDEC 1512
When it is determined from the instruction decoding result sent from the above that the instruction can be executed without using the sequence code, the selected DS does not output the sequence code address, and instead, the selected DS does not output the sequence code address. The instruction data of the instruction architecture itself, which is basically supported by the information processing apparatus, is transmitted to the IMU 1570 via the signal line 1509. The IMU 1570 receives instruction word data of an instruction architecture basically supported by the information processing apparatus, modifies and converts data in an arbitrary field of the instruction data, and is actually specified by the instruction in the EU 1580. Command data in a format capable of executing the specified function, and sends the command data to the IU 1510. In this case, the SSAR and S corresponding to the selected DS
The selection operation of S is suppressed. Also, depending on the command, the selected DS does not send the command data to the IMR 1570, but immediately generates the IU setup data and
80.

As described above, in FIG.
C1512 is one set, but two sets are prepared and M
The command from S1500 and the command from IMU 1570 may be used separately. Furthermore, a unique DS may be assigned in advance to the instruction word from the IMU 1570. Accordingly, the configuration of each DS forming the DS group 1513 can be simplified.

FIG. 18 is a diagram showing an instruction architecture basically supported by the information processing apparatus when the information processing apparatus of the present invention performs instruction processing of instructions having different instruction architectures in a simulator or emulator processing procedure. FIG. 9 is a diagram illustrating a sequence code corresponding to each instruction and a description example of the instruction in the IS when an instruction function of one different instruction architecture is realized by combining instructions.

In FIG. 18, (1) shows an instruction architecture a in which an instruction architecture b having a function of moving data between storage areas is basically supported by a plurality of sequence codes and an information processing apparatus. 5 is an example of a flowchart showing a programming order in the case of being realized by a combination of instructions. This instruction A has the same function as the instruction shown in (1) of FIG. (2) is an instruction B of an instruction architecture b having a function of performing an exclusive OR of data between storage areas, which is a combination of a plurality of sequence codes and an instruction of an instruction architecture a basically supported by the information processing apparatus. 6 is an example of a flowchart showing a programming order when the combination is realized. this is,
It has the same function as the instruction shown in (2) of FIG. (3)
FIG. 4 is a diagram showing an arrangement state of instructions of the instruction architecture a used in the instruction A and the instruction B of the instruction architecture b on the IS.

For example, a simulator or emulator processing procedure for executing the instruction A of the instruction architecture b includes a plurality of sequence codes stored in a continuous area starting from the sequence code address a in one SS in the SS group 1540. And each sequence code is sequentially taken out from the corresponding SS in the direction in which the sequence code address increases, and
The instruction words of the instruction architecture a are sequentially extracted from the position specified by the instruction address specified by the sequence code. As described with reference to FIG. 15, the extracted instruction word of the instruction architecture a is transmitted to the IMU 1570, and the IMU 1570 executes the instruction A of the instruction architecture b.
Modifying and converting data in a predetermined field of the instruction data of the instruction architecture a using the instruction information of
This command data is sent to the IU 1510, and the IU group 15
10 to the EU 1580 as IU setup data. The same applies to the instruction B of the instruction architecture b.

As shown in FIG. 18, in the present example, when processing instructions A and B having different instruction architectures in a simulator or emulator processing procedure, the information processing apparatus basically supports the architectures. What is necessary is just to store ten instructions in IS1560.

As described above, when the information processing apparatus of the present invention performs instruction processing of instructions having different instruction architectures in the simulator or emulator processing procedure, a specific example of the description frequency of the instruction of the simulator or emulator processing procedure in the IS will be described. One embodiment of the sequence of programming the sequence codes has been described.

Next, the parameters to be input to and output from the IMU 1570 and the modification conversion operation of the instruction in the IMU 1570 will be described.

As shown in FIG. 15, as parameters input to IMU 1570, an instruction sent from IU 1510 via signal line 15009 and having an instruction architecture different from the basic instruction architecture of the information processing apparatus is simulated or processed. Instruction group data relating to an instruction having a different instruction architecture for emulation, or instruction group data relating to an instruction which does not need to be simulated or emulated in the case of an instruction having the same instruction architecture as the basic instruction architecture of the information processing apparatus, SS group 1540 From signal line 1
The content data of the modification parameter field in the sequence code sent via the
There is a parameter group of instruction word data of an instruction architecture which is basically supported by the information processing device read from the 560 and transmitted via the signal line 15006. I
The parameters output from MU 1570 include IM
The instruction word having the same instruction architecture as the basic instruction architecture of the information processing device input to U1570 is actually decoded by the IU group 1510, and the data of the input instruction word is modified and converted so that it can be executed by the EU1580. There is a parameter for the resulting command data.

First, the type of instruction sent from the IU 1510 is instruction data itself having an instruction architecture different from the basic instruction architecture of the information processing apparatus, and the above-described simulation or emulation is required. Next, the type of instruction sent from the IU 1510 is an instruction having the same instruction architecture as the basic instruction architecture of the information processing apparatus, and does not need to be simulated or emulated. The instruction word data itself has the same instruction architecture as the basic instruction architecture of the device. The instruction data read from the IS 1560 for performing the simulation or the emulation is the instruction data itself having the same instruction architecture as the basic instruction architecture of the information processing apparatus described above.

Data of the modification parameter field in the sequence code sent from SS group 1540 is
This is input data for modifying or converting the command word data sent from the IS1560. The input data is used as a parameter for extracting, in bit units, instruction data having a different instruction architecture sent from the IU 1510, and is composed of the following modification parameter groups.

That is, the following parameters are generated using instruction word data having different instruction architectures as source operands. Modification parameter 1: A parameter that specifies a bit position to be extracted. Modification parameter 2: A parameter that specifies the bit width to be extracted. Modification parameter 3: A parameter that specifies the number of bits to be extracted. Modification parameter 4: A parameter that specifies an operation for the extracted bit data or bit data group. Modification parameter 5: A parameter for designating editing of bit data or a group of bit data after an arithmetic operation. Modification parameter 6: A parameter that specifies the bit position where the bit data after the editing operation is to be inserted. Modification parameter 7: A parameter for specifying the bit width into which the bit data after the editing operation is to be inserted. Modification parameter 8: A parameter that specifies the number of bits into which the bit data after the editing operation is to be inserted.

Further, the input data is based on the above-mentioned IS15
The instruction word data having the same instruction architecture sent from 60 is also used as a parameter for extracting in bit units, and is composed of the following modification parameter groups. That is, the following parameters are generated using instruction word data having the same instruction architecture as a source operand. Modification parameter 11: A parameter that specifies a bit position to be extracted. Modification parameter 12: A parameter that specifies the bit width to be extracted. Modification parameter 13: A parameter that specifies the number of bits to be extracted. Modification parameter 14: A parameter for specifying an operation for the extracted bit data or bit data group. Modification parameter 15: Bit data after operation
Parameter that specifies the insertion of a fixed value of '0' or '1'. Modification parameter 16: A parameter for designating editing of bit data or a group of bit data after an arithmetic operation. Modification parameter 17: A parameter that specifies the bit position where the bit data after the editing operation is to be inserted. Modification parameter 18: A parameter for specifying the bit width into which the bit data after the editing operation is to be inserted. Modification parameter 19: A parameter for specifying the number of bits into which the bit data after the editing operation is to be inserted. The IMU 1570 executes a command modification conversion operation in the following procedure using the modification parameter group. In addition,
Before starting the qualification conversion operation procedure, the instruction data for the instruction having a different instruction architecture from the IU 1510, the qualification parameter from the SS group 1540, and the IS1
The instruction word data of the instruction architecture from 560, which is basically supported by the information processing apparatus, is IMU157
It is assumed that the value has already been input within 0.

Step 1: Based on the designation of the modification parameter 1, the modification parameter 2 and the modification parameter 3, the IU1
Bit data of an instruction word related to an instruction having a different instruction architecture input from 510 is extracted, grouped into one or more groups defined for each predetermined function, and one or more grouped Let the data be the output of this step. Step 2: Based on the designation of the modification parameter 4, a predetermined operation is performed on the output of step 1, and one or a plurality of data on which the operation is performed is set as the output of this step. Step 3: A predetermined editing operation is performed on the output of step 2 based on the designation of the modification parameter 5, and one or a plurality of data that has been format-converted by performing the editing operation is output as the output of this step. I do. Step 4: On the basis of the specification of the decoration parameters 6, the decoration parameters 7, and the decoration parameters 8, the output of the step 3 is re-grouped into one or a plurality of groups defined for each predetermined function,
One or more grouped data is output from this step. Step 5: Based on the specification of the modification parameter 11, the modification parameter 12, and the modification parameter 13, extract the bit data of the instruction word having the same instruction architecture input from the IS 1560, and determine the bit data for each predetermined function. One or a plurality of data is grouped into one or a plurality of groups, and one or a plurality of the grouped data is output as the output of this step. Step 6: Modification parameter 1
Based on the designation of 4, the output of step 4 and the output of step 5 are used as input operands, a predetermined operation is performed, and one or a plurality of data subjected to this operation is output as this step. Step 7: Based on the specification of the qualifying parameter 15, the output of step 6 may be performed as necessary, if necessary.
An operation of inserting a fixed value of 0 'or' 1 'is performed, and one or a plurality of data subjected to this operation is output as the output of this step.

Step 8: A predetermined editing operation is performed on the output of step 7 based on the designation of the modification parameter 16, and one or a plurality of data that has been format-converted by the execution of this editing operation is output to this step. Output. Step 9: decoration parameter 17, decoration parameter 18
Based on the specification of the modification parameter 19, the output of step 8 is re-grouped into one or more groups defined for each predetermined function, and the grouped 1
One or more data are output from this step. The output of step 9 is the command data modified and converted by the IMU 1570 and sent to the IU 1510 as a command having the same command architecture as the basic command architecture of the information processing device.

Next, various embodiments in which the information processing apparatus of the present invention is mounted in a semiconductor chip will be described with reference to FIGS.
Shown in

FIG. 19 is a block diagram showing a first embodiment in which the information processing apparatus of the present invention shown in FIG. 1 for executing command processing under microcode control is mounted in a semiconductor chip. In FIG. 19, the IU 110 includes an instruction register (IR), an instruction decoder (IDEC), a setup data generator (DS), etc., as shown in FIG. To be implemented. This is shown by section 19-0 in FIG. Also, an SSAR group 120 composed of logic circuits and an SS group 140 composed of storage circuit elements are provided.
In addition, the CSAR 150 including the logic circuit and the address adder 130 are mounted on the same semiconductor chip. This is shown in FIG.
In FIG. Similarly, the CS 160 composed of a memory circuit element and the CSDR 170 composed of a logic circuit are mounted on the same semiconductor chip. This is shown in FIG.
Indicated by -2.

By mounting as described above, the section 1 in FIG.
It is possible to eliminate a drive circuit for driving an input / output terminal for a signal line closed inside 9-0 and the sections 19-1 and 19-2, and as a result, it is possible to reduce a signal transmission delay between chips. Further, a drive circuit for driving the input / output terminals is provided in the 19-
The power consumption of the information processing apparatus can be reduced because it is necessary to add only to the signal lines connecting the three sections 0, 19-1, and 19-2. Further, by not passing through the input / output terminals, the limitation on the number of signal lines, which was limited by the number of physical input / output terminals, can be removed, and the function blocks of the respective information blocks constituting the information processing apparatus can be removed. By determining the grouping so that the number of signal lines is reduced, the number of signal lines passing through input / output terminals requiring a driving circuit can be easily reduced.

FIG. 20 is a block diagram showing a second embodiment in which the information processing apparatus of the present invention shown in FIG. 1 for performing instruction processing under microcode control is mounted in a semiconductor chip. In FIG. 20, an IU 110 including a logic circuit and a storage circuit element, an SSAR group 120 including a logic circuit, an SS group 140 including a storage circuit element, and a C including a logic circuit
The SAR 150, the address adder 130, the CS 160 including storage circuit elements, and the CSDR 170 including logic circuits are all mounted on the same semiconductor chip. Figure 2
A value of 0 indicates the section 20-1.

By mounting in this manner, the signal lines interconnecting the seven functional blocks can be connected while maintaining a wide data width, and the signal lines to be closed inside the section 20-1 in FIG. The drive circuit for driving the input / output terminals can be eliminated, and as a result, the signal transmission delay between chips can be reduced. Further, a drive circuit for driving the input / output terminals is provided by EU13
The power consumption of the information processing apparatus can be reduced by adding only 0 to the signal line connecting the 0. Further, by not passing through the input / output terminals, the limitation on the number of signal lines, which was limited by the number of physical input / output terminals, can be removed, and the function blocks of the respective information blocks constituting the information processing apparatus can be removed. By determining the grouping so that the number of signal lines is reduced, the number of signal lines passing through input / output terminals requiring a driving circuit can be easily reduced.

FIG. 21 is a block diagram showing a third embodiment in which the information processing apparatus of the present invention shown in FIG. 1 for performing instruction processing under microcode control is mounted in a semiconductor chip. In FIG. 21, an IU 110 including a logic circuit and a storage circuit element, an SSAR group 120 including a logic circuit, an SS group 140 including a storage circuit element, and a CS including a logic circuit
The AR 150 and the address adder 130 are mounted on the same semiconductor chip. This is indicated by section 21-1 in FIG.
Similarly, the CS 160 composed of a memory circuit element and the CSDR 170 composed of a logic circuit are mounted on the same semiconductor chip. This is indicated by section 21-2 in FIG.

By mounting as described above, the drive circuit for driving the input / output terminals for the signal lines closed inside the sections 21-1 and 21-2 in the case of FIG. 19 can be eliminated. Signal transmission delay can be reduced. Furthermore, since a driving circuit for driving the input / output terminals only needs to be added to the signal line connecting the two sections, the power consumption of the information processing device can be reduced. Further, by not passing through the input / output terminals, the limitation on the number of signal lines, which was limited by the number of physical input / output terminals, can be removed, and the function blocks of the respective information blocks constituting the information processing apparatus can be removed. By determining the grouping so that the number of signal lines is reduced, the number of signal lines passing through input / output terminals requiring a driving circuit can be easily reduced.

FIG. 22 shows a first embodiment in which an information processing apparatus which executes instruction processing of instructions having different instruction architectures under the control of the simulator or emulator of the present invention shown in FIG. 15 by hardware logic control is mounted in a semiconductor chip. It is a block diagram showing an example. In FIG. 22, an IU 151 comprising a logic circuit of an instruction register (IR) and an instruction decoder and a storage circuit element of a data generation group (DS group)
0, SSAR group 1520 composed of logic circuits, SS group 1540 composed of storage circuit elements, IS15 composed of logic circuits
60, the address adder 1530 and the IMU 1570 are mounted on the same semiconductor chip. This is shown in FIG.
Indicated by -1. Similarly, a register file group 1590 composed of storage circuit elements and an EU 1580 composed of logic circuits are mounted on the same semiconductor chip. This is shown in FIG.
2-2 is shown.

By mounting as described above, the section 2 in FIG.
A drive circuit for driving an input / output terminal for a signal line closed inside the section 2-1 and the section 22-2 can be eliminated, and as a result, a signal transmission delay between chips can be reduced. Further, since a driving circuit for driving the input / output terminals only needs to be added to the signal line connecting the two sections 22-1 and 22-2, the power consumption of the information processing apparatus can be reduced. Further, by not passing through the input / output terminals, the limitation on the number of signal lines, which was limited by the number of physical input / output terminals, can be removed, and the function blocks of the respective information blocks constituting the information processing apparatus can be removed. By determining the grouping so that the number of signal lines is reduced, the number of signal lines passing through input / output terminals requiring a driving circuit can be easily reduced.

FIG. 23 is a block diagram showing a second embodiment in which an information processing apparatus for performing hardware logic control of instructions having different instruction architectures under the control of a simulator or emulator of the present invention is mounted in a semiconductor chip. This particularly shows an embodiment in which the configuration shown in FIG. 16 is formed into a semiconductor chip. In FIG. 23, IR1511 and IDEC1512 each composed of a logic circuit
Are mounted in the same semiconductor chip. This is indicated by section 23-1 in FIG. Further, a DS comprising a storage circuit element
(0) 1513-0, SS (0) 1540-0 and SSAR (0) 1520-0 composed of a logic circuit are mounted on the same semiconductor chip. This is indicated by section 23-2 in FIG. Similarly, DS (1) 151 composed of a storage circuit element
3-1 and SSAR (1) 1520-1 comprising SS (1) 1540-1 and a logic circuit are mounted on the same semiconductor chip (section 23-3 in FIG. 23), and thereafter, similarly, from the storage circuit element. DS (n) 1513-n and SS (n)
SSAR (n) 15 comprising 1540-n and logic circuit
20-n are mounted in the same semiconductor chip (section 23-4 in FIG. 23).

By mounting as described above, in FIG. 23, a drive circuit for driving an input / output terminal for a signal line closed inside the sections 23-1, 23-2, 23-3 and 23-4. , And as a result, the signal transmission delay between chips can be reduced. Furthermore, since a driving circuit for driving the input / output terminals only needs to be added to the signal line connecting the two sections, the power consumption of the information processing device can be reduced. Further, by not passing through the input / output terminals, the limitation on the number of signal lines, which was limited by the number of physical input / output terminals, can be removed, and the function blocks of the respective information blocks constituting the information processing apparatus can be removed. By determining the grouping so that the number of signal lines is reduced, the number of signal lines passing through input / output terminals requiring a driving circuit can be easily reduced.

FIG. 24 is a block diagram of a third embodiment of the present invention in which an information processing apparatus which executes instruction processing of instructions having different instruction architectures under the control of a simulator or emulator under the control of hardware logic is mounted in a semiconductor chip. 23 shows another embodiment in which the configuration shown in FIG. 16 is formed into a semiconductor chip. In FIG. 24, IR1511 and IDEC1512, which are composed of logic circuits,
Are mounted in the same semiconductor chip (section 24-- in FIG. 24).
1). Similarly, DS (0) 151 composed of a storage circuit element
3-0 and DS (1) 1513-1 and DS (n) 151
SSAR (0) 1650 comprising 3-n and logic circuit
0 and SSAR (1) 1650-1 and SSAR (n) 16
50-n are mounted in the same semiconductor chip (section 24-2 in FIG. 24). Similarly, the SS composed of the storage circuit element
(0) 1540-0 and SS (1) 1540-1 and SS
(N) 1540-n is mounted in the same semiconductor chip (section 24-3 in FIG. 24).

By mounting as described above, in FIG. 24, a drive circuit for driving an input / output terminal for a signal line closed inside the sections 24-1, 24-2 and 24-3 can be eliminated. As a result, a signal transmission delay between chips can be reduced. Furthermore, since a driving circuit for driving the input / output terminals only needs to be added to the signal line connecting the two sections, the power consumption of the information processing device can be reduced. Further, by not passing through the input / output terminals, the limitation on the number of signal lines, which was limited by the number of physical input / output terminals, can be removed, and the function blocks of the respective information blocks constituting the information processing apparatus can be removed. By determining the grouping so that the number of signal lines is reduced, the number of signal lines passing through input / output terminals requiring a driving circuit can be easily reduced.

FIG. 25 is a block diagram of the embodiment of FIG. 4 in which an information processing apparatus which executes instruction processing of instructions having different instruction architectures under the control of a simulator or emulator under the control of hardware logic is implemented in a semiconductor chip. Then, as in FIGS. 23 and 24, there is shown still another embodiment in which the configuration shown in FIG. 16 is further integrated into a semiconductor chip.
In FIG. 25, IR1511 composed of a logic circuit and ID
The EC 1512 is mounted on the same semiconductor chip (FIG. 25)
Section 25-1). Similarly, an IA comprising a storage circuit element
MR1600, DS (0) 1513-0 and DS (1) 1
513-1 and DS (n) 1513-n are mounted on the same semiconductor chip (section 25-2 in FIG. 25). Similarly,
SSAR (0) 1520-0 consisting of a logic circuit and SSA
R (1) 1520-1 and SSAR (n) 1520-n and SS (0) 1540-0 and SS composed of storage circuit elements
(1) Mount 1540-1 and SS (n) 1540-n in the same semiconductor chip (section 25-3 in FIG. 25).

By mounting as described above, in FIG. 25, the drive circuit for driving the input / output terminals for the signal lines closed inside the sections 25-1, 25-2, and 25-3 can be eliminated. As a result, a signal transmission delay between chips can be reduced. Furthermore, since a driving circuit for driving the input / output terminals only needs to be added to the signal line connecting the two sections, the power consumption of the information processing device can be reduced. Further, by not passing through the input / output terminals, the limitation on the number of signal lines, which was limited by the number of physical input / output terminals, can be removed, and the function blocks of the respective information blocks constituting the information processing apparatus can be removed. By determining the grouping so that the number of signal lines is reduced, the number of signal lines passing through input / output terminals requiring a driving circuit can be easily reduced.

In the embodiment shown in FIGS. 19 to 21, the instruction control unit (IU) and the execution unit (EU)
And the instruction architecture mode register (IAMR)
As an electronic circuit for performing arithmetic and control, the semiconductor device is mounted in a semiconductor chip by processing using electromagnetic waves or magnetism or electrons or processing using a combination of electromagnetic waves or magnetism or electrons, and processing using a combination of chemical processing, control storage (CS) and sequence storage ( SS) is processing and scientific processing by electromagnetic waves or magnetism or electrons or a combination of electromagnetic waves or magnetism or electrons as storage elements using dielectric properties or storage elements using connection of electronic circuits to control data storage. A setup data generation unit (DS) is provided with an electronic circuit for controlling the operation and control and a storage element or an electronic circuit using characteristics of a dielectric material for managing data storage. What is necessary is just to mount in a semiconductor chip by the process used for both of the memory elements using the connection.

Similarly, in the embodiments shown in FIGS. 22 to 25, the instruction reading unit, instruction buffer register, instruction decoding unit and execution unit (E) of the instruction control unit (IU) are used.
U) and Instruction Architecture Mode Register (IAMR)
And the command modification unit are mounted in a semiconductor chip by processing by electromagnetic wave or magnetic or electronic or a combination of each of electromagnetic wave or magnetic or electronic and processing by a combination of chemical processing as an electronic circuit for controlling and controlling, and storing the instruction ( IS) and sequence storage (SS) are electromagnetic waves or magnetism or electrons or a combination of electromagnetic waves or magnetism or electrons as storage elements using characteristics of a dielectric substance or storage elements using connection of electronic circuits to control data storage. Is mounted in a semiconductor chip by processing using a combination of processing and scientific processing, and the setup data generation unit (D
S) is implemented in a semiconductor chip by processing used for both an electronic circuit that controls arithmetic and control and a storage element that uses characteristics of a dielectric to control data storage or a storage element that uses connection of an electronic circuit. do it.

[0186]

According to the information processing apparatus of the present invention which performs instruction processing under microcode control, by changing the instruction architecture mode of the instruction architecture mode register, different operation specifications can be applied to instructions having the same instruction code. It becomes possible to execute the instruction processing which has.

When attention is paid to the control storage (CS),
By storing a combination of microinstruction addresses as a microcode processing procedure and an execution order as a sequence code sequence in each sequence storage (SS), a plurality of instructions are provided to realize a machine language level instruction function of the information processing apparatus. When the microcode is incorporated by combining a plurality of functions of the microinstruction, the necessity of storing a plurality of the same microinstruction on different CS addresses can be eliminated. As a result, it is possible to greatly improve the instruction processing performance of the hardware of the information processing apparatus that realizes the instruction processing by the microcode. Further, a microcode-controlled multi-instruction architecture processor that supports a plurality of instruction architectures can be easily realized.

Further, it is not necessary to store a very large number of micro-instructions in the CS as compared with the number of types of the micro-instructions, and the physical CS logic circuit size in the integrated circuit can be reduced. The reduction in the size of the physical CS in the integrated circuit leads to a reduction in the access time to the CS by the hardware of the information processing apparatus that realizes the instruction processing by the microcode, and the information for performing the instruction processing by the microcode control. The performance of the processing device can be greatly improved, and the reduction in the size of the physical CS logic circuit in the integrated circuit is the most important component of the information processing device that realizes the instruction processing by microcode. This leads to a reduction in the chip area of large-scale integrated circuits, which has the industrial effect in manufacturing industrial products that greatly reduces the manufacturing cost of information processing equipment, and multi-instructions that reduce industrial cost. An architecture processor can be provided.

Further, in the information processing apparatus for performing the instruction processing under the hardware logic control according to the present invention, similarly, by changing the instruction architecture mode of the instruction architecture mode register, the instruction having the same instruction code can be executed. It is possible to execute instruction processing having different operation specifications.

When focusing on instruction storage (IS),
A combination of an instruction address having a first instruction architecture (an instruction architecture basically supported by an information processing apparatus) as a processing procedure of an instruction having a second instruction architecture is stored in each sequence memory (SS). By storing the execution order as a sequence code sequence, the second instruction architecture is implemented by combining a plurality of functions of instructions having a plurality of first instruction architectures in order to realize a machine language level instruction function of the information processing apparatus. When incorporating an instruction having the same instruction architecture, it is possible to eliminate the need to store a plurality of instructions having the same first instruction architecture at different storage addresses of instruction storage. As a result, the instruction processing performance of the hardware of the information processing apparatus that realizes the instruction processing of the instruction having the second instruction architecture with the combination of the instructions having the first instruction architecture can be significantly improved. Also, a hardware logic controlled multi-instruction architecture processor that supports a plurality of instruction architectures can be easily realized.

Furthermore, there is no need to store in the instruction storage a very large number of instructions having the first instruction architecture as compared with the number of types of instructions having the first instruction architecture. Instruction memory circuit size can be reduced. The size of the physical instruction storage in the integrated circuit is reduced by the hardware of the information processing apparatus that realizes the instruction processing of the instruction having the second instruction architecture by the combination of the instructions having the first instruction architecture. This leads to a reduction in the access time to the instruction storage, greatly improving the performance of the information processing apparatus that performs the instruction processing under the hardware logic control, and reducing the physical instruction storage circuit size in the integrated circuit. This leads to a reduction in the chip area of a large-scale integrated circuit, which is the most important component of an information processing device that realizes instruction processing of an instruction having a second instruction architecture by a combination of instructions having the same instruction architecture. Has an industrial effect in manufacturing industrial products that significantly reduces the cost of manufacturing information processing equipment. It is possible to provide a multi-instruction architecture processor with reduced industrial costs Te.

Further, the instruction control unit, the execution unit, the instruction architecture mode register, and the instruction modification / conversion unit in the information processing apparatus which performs the instruction processing having the first instruction architecture by the hardware logic control are provided by an electronic control unit which performs operations and controls. The control memory, the instruction memory, and the sequence memory are implemented in a semiconductor chip as a general logic circuit, and the electronic memory described above is used as an electronic memory element for controlling data storage or a memory element using connection of an electronic circuit. The setup data generation unit is mounted in the same semiconductor chip as the circuit, and the electronic circuit that performs the arithmetic and control and the storage element that stores the data or the storage element that uses the connection of the electronic circuit are stored in the same semiconductor chip. Instruction control unit, execution unit and instruction architecture mode register By mounting the control unit, control storage, instruction storage, sequence storage, and setup data generation unit in the same semiconductor chip, the time delay of an electric signal generated between the storage element chip and the logic circuit chip can be reduced. It becomes possible. As a result, the instruction processing performance of the hardware of the information processing apparatus that realizes the processing of instructions having a different instruction architecture by a combination of instructions having a certain instruction architecture can be significantly improved.

Further, as described above, the components comprising the storage element and the logic circuit are mounted on the same semiconductor chip, so that the input / output terminals for transmitting and receiving the electric signals between the storage element chip and the logic circuit chip are provided. It can be removed. As a result, the limitation on the number of physical input / output terminals that can be mounted on a chip can be eliminated. As a result, the data width of the electric signal between the storage element and the logic circuit can be greatly expanded, and the information processing device that realizes the instruction processing by the microcode, and another by the combination of the instructions having a certain instruction architecture. The instruction processing performance of the hardware of the information processing apparatus that realizes the instruction processing of the instruction having the instruction architecture can be greatly improved.

Further, as described above, by mounting the components comprising the storage element and the logic circuit on the same semiconductor chip, a circuit for amplifying an electric signal passing between the storage element chip and the logic circuit chip and the circuit for amplifying the electric signal are provided. The power consumed by the circuit and the heat generation can be significantly reduced. As a result, an information processing device that realizes instruction processing with microcode,
The power consumption and the heat generation of the information processing apparatus that realizes the instruction processing can be significantly reduced because the instructions having a certain instruction architecture are combined with another instruction architecture.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a micro-instruction reading and executing mechanism in an information processing apparatus according to the present invention.

FIG. 2 is a block diagram illustrating an example of a micro-instruction reading and executing mechanism of an information processing apparatus according to the related art.

FIG. 3 is a diagram illustrating a configuration example of a command control unit of an information processing apparatus according to the related art.

FIG. 4 is a diagram showing a connection between a microcode execution procedure composed of a plurality of microinstructions and a plurality of microinstructions according to the related art.

FIG. 5 is a diagram showing an example of a combination of microinstruction functions and a programming order for realizing an instruction function in the related art.

FIG. 6 is a diagram showing an example of the format and content of one sequence code entry stored in a sequence storage according to the present invention.

FIG. 7 is a block diagram showing a detailed configuration of a main part in the information processing apparatus of the present invention.

FIG. 8 is a diagram showing an example of a combination of a sequence code and a microinstruction function and a programming order for realizing the instruction function in the present invention.

FIG. 9 is a diagram illustrating a configuration example of a command control unit of an information processing apparatus according to the related art.

FIG. 10 is a diagram illustrating a configuration and a relationship between an information processing apparatus according to the related art, an operating system operating on the information processing apparatus, and an application program.

FIG. 11 is a diagram illustrating the relationship between the configuration of an information processing apparatus, an operating system, and an application program when an information processing apparatus according to the related art performs instruction processing having a plurality of different instruction architectures.

FIG. 12 is a diagram showing a configuration of functional resources and a role of the functional resources when a different instruction architecture program according to the prior art is executed by means of an interpreter.

FIG. 13 is a diagram showing a configuration of functional resources and a role of the functional resources when a different instruction architecture program according to the prior art is executed by means of a simulator or emulator.

FIG. 14 is a diagram showing an example of a combination of instruction functions and a programming order for realizing the instruction functions in the related art.

FIG. 15 is a block diagram showing an embodiment of an instruction reading and executing mechanism in the information processing apparatus which performs instruction processing under hard logic control according to the present invention.

FIG. 16 is a diagram showing a detailed configuration of a main part in the information processing apparatus of FIG. 15;

FIG. 17 is a diagram showing an example of a combination of a sequence code and an instruction function and a programming order for implementing the instruction function in the present invention.

FIG. 18 is a diagram showing an example of the format and content of one sequence code entry stored in the sequence storage according to the present invention.

FIG. 19 is a block diagram showing an embodiment in which an information processing device for performing instruction processing under microcode control according to the present invention is mounted in a semiconductor chip.

FIG. 20 is a block diagram showing another embodiment in which an information processing apparatus for performing instruction processing under microcode control according to the present invention is mounted in a semiconductor chip.

FIG. 21 is a block diagram showing still another embodiment in which an information processing apparatus for performing instruction processing under microcode control according to the present invention is mounted in a semiconductor chip.

FIG. 22 is a block diagram showing an embodiment in which an information processing device for performing instruction processing under hard logic control according to the present invention is mounted in a semiconductor chip.

FIG. 23 is a block diagram showing an embodiment in which an instruction reading and executing mechanism of an information processing device that performs instruction processing under hard logic control according to the present invention is mounted in a semiconductor chip.

FIG. 24 is a block diagram showing another embodiment in which the instruction reading and executing mechanism of the information processing apparatus for performing the instruction processing by the hard logic control according to the present invention is mounted in a semiconductor chip.

FIG. 25 is a block diagram showing still another embodiment in which the instruction reading and executing mechanism of the information processing apparatus according to the present invention is mounted in a semiconductor chip.

[Explanation of symbols]

 100, 1500 Main storage 110, 1510 Instruction control unit 120, 1520 Sequence storage address register group 130, 1530 Address adder 140, 1540 Sequence storage group 150 Control storage address register 160 Control storage 170 Control storage data register 180, 1580 Execution unit 111 , 1511 Instruction register 112, 1512 Instruction decoder 113, 1513 Setup data generator group 115, 1615 Instruction architecture mode register 1560 Instruction storage 1570 Instruction modification conversion unit

Claims (9)

[Claims] 1. An information processing apparatus comprising: an instruction control unit that reads and decodes an instruction; and an execution unit that executes the instruction. An instruction architecture mode register that holds an architecture mode of an instruction to be processed; A plurality of setup data generating units for respectively generating setup data required for instruction processing for each architecture mode; and a plurality of sequence storages for storing a sequence code sequence defining an execution order of instructions for each instruction architecture mode. And an instruction storage for storing a group of instruction words to be executed without duplication, wherein one setup data generation unit is selected from the plurality of setup data generation units by an output value of the instruction architecture mode register. And decode the result of the instruction to be processed. As input setup data generation unit that is, to give the set-up data necessary for the processing of the instruction, at least a portion of the resulting set-up data,
As a head read address of one of the sequence memories out of the plurality of sequence memories, a sequence code string that determines the execution order of the processing target instruction is read from the sequence memory, and the read sequence code string is stored in the instruction memory. An information processing apparatus, wherein an instruction group corresponding to a processing target instruction is read from the instruction storage as a read address string and sent to the execution unit, so that instructions having different architectures can be executed. 2. The information processing apparatus according to claim 1, wherein
An information processing apparatus, wherein instruction processing having different operation specifications is executed for instructions having the same instruction code by changing the instruction architecture mode of the instruction architecture mode register. 3. An instruction control unit for reading and decoding an instruction, a control storage for storing a plurality of micro-instructions for controlling execution of the instruction, and an execution unit for executing the micro-instruction. In an information processing apparatus that performs instruction processing, an instruction architecture mode register that holds an architecture mode of an instruction to be processed, and instruction processing setup data including, for each instruction architecture mode, a sequence code address that differs according to the type of instruction. And a plurality of sequences for storing, for each architecture mode of the instruction, a sequence code sequence that defines the execution order of the microinstructions stored in the control storage according to the type of the instruction. Memory and the instruction architecture One of the setup data generators is selected from the plurality of setup data generators according to the output of the key mode register, and the decoding result of the instruction to be processed is input to the selected setup data generator, and A corresponding set-up data is obtained, a sequence code address in the obtained set-up data is set as an input of one of the plurality of sequence stores, and the sequence code is read from the sequence store with the sequence code address as a head. An information processing apparatus comprising: sequentially reading micro-instructions from the control storage using the read sequence code as a read address of the control storage, and transmitting the micro-instructions to an execution unit. 4. The information processing apparatus according to claim 2,
Each of the plurality of setup data generation units has a function of generating a microinstruction address in addition to a different sequence code address according to the type of the instruction as setup data for instruction processing, The unit reads the microinstruction directly from the control storage using the microinstruction address as an input to the control storage when a condition for transmitting the microinstruction address is satisfied according to the type of the decoded instruction. Processing equipment. 5. A main memory for storing an instruction having an arbitrary instruction architecture, an instruction control unit for reading and decoding instructions, and an instruction having a specific instruction architecture (hereinafter referred to as an instruction word of a first instruction architecture). ), An instruction modification unit for modifying the instruction word, and an execution unit for executing the instruction word of the first instruction architecture. An instruction architecture mode register that holds the instruction, a plurality of setup data generators that generate setup data corresponding to the instruction type for each instruction architecture mode, and an instruction execution order for each instruction architecture mode Multiple sequence memories for storing Selecting one setup data generation unit from the plurality of setup data generation units according to an output value of the instruction architecture mode register; and determining a decoding result of the processing target instruction read from the main storage by the selection. Obtained setup data required for processing the command as an input of the setup data generation unit, at least a part of the obtained setup data,
As a head read address of one of the plurality of sequence storages, a sequence code that determines an execution order of a processing target instruction is sequentially read from the sequence storage, and at least a part of the read sequence code is read. As a read address of the instruction storage, sequentially read the instruction words of the first architecture corresponding to the instruction to be processed from the instruction storage, perform the instruction modification unit modification and the conversion operation on the read instruction words, An information processing apparatus for transmitting the information to the execution unit. 6. The information processing apparatus according to claim 5, wherein
The selected setup data generating unit, when the instruction to be processed is not an instruction having the first architecture,
A part of the generated setup data is sent to the sequence storage as a head read address of the sequence storage. If the processing target instruction is an instruction having the first architecture, the generated setup data is sent to the instruction modification unit as it is. An information processing apparatus characterized by the above-mentioned. 7. The information processing apparatus according to claim 1, wherein
An information processing apparatus, wherein all of the instruction control unit, the instruction architecture mode register, the setup data generation unit group, the sequence storage group, and the instruction storage or a desired combination thereof are mounted on one semiconductor chip. 8. The information processing apparatus according to claim 3, wherein one of the instruction control unit, the instruction architecture mode register, the set-up data generation unit group, the sequence storage group, and the control storage is provided for each or a desired combination thereof. An information processing device mounted on a semiconductor chip. 9. The information processing apparatus according to claim 5, wherein all of the instruction control unit, the instruction architecture mode register, the setup data generation unit group, the sequence storage group, the instruction storage and the instruction modification conversion unit, or a desired combination thereof. An information processing apparatus, wherein each of the information processing apparatuses is mounted on one semiconductor chip.