JPH1091545A - Data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To continuously execute data transfer even during retry by receiving a retry request outputted from a second device to a first device and transferring data to which retry is requested to the second device. SOLUTION: A common bus 1, bus masters 2 and 3 connected to the common bus 1, bus slaves 4 and 5 and a retry control circuit 6 are provided. The bus masters 2 and 3 output data to the common bus 1 and the bus slaves 4 and 5 respectively receive the data. It often occurs that the bus slaves 4 and 5 output data to the common bus 1 and the bus masters 2 and 3 receive the data. When the bus slave 4 (5) cannot receive data outputted to the common bus 1, a bus retry request signal P is outputted from the bus slave 4 (5), the retry control circuit 6 is outputted from the bus slave 4 (5) and the retry control circuit 6 transfers data to the bus slave 4 (5) instead of the bus masters 2 and 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system, and more particularly to a retry (instruction re-execution) when outputting data.
The present invention relates to a data transfer system capable of performing the following.

[0002]

2. Description of the Related Art Conventionally, when an access made by a bus master cannot be accepted by a slave, the bus master has re-accessed the slave.
This is called a retry.

[0003] As this kind of technology, Japanese Patent Application Laid-Open No. H04-0768 is disclosed.
Japanese Patent Application Publication No. 54-54, envisaged that the actual retry time is measured and compared with the total retry time, and when the real retry time is short, the retry processing is continued, thereby increasing the number of retry operations and efficiently performing the retry processing. A retry processing method for the purpose is disclosed.

[0004]

However, according to this conventional technique, there is a disadvantage that the number of retries is limited. This is because the number of times of retry and the time are set in advance.

Further, when a retry occurs, there is a disadvantage that the bus master having made the access cannot perform the next access. This is because once the retry occurs, the retry is performed during the set retry count and the retry time, so that the next data transfer stops.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data transfer system which does not need to measure the number of retries and the retry time, and can continue data transfer during a retry.

[0007]

According to the present invention, a first device and a second device transfer data via a common bus, and the first device and the second device transfer the data from the first device to the second device. A data transfer system that outputs a retry request from the second device to the first device when the second device cannot receive the data transferred to the second device. Receiving means for receiving a retry request output from the device to the first device, and transferring the data requested to be retried to the second device.

According to the present invention, the transfer means separate from the first and second devices transfers the data requested to be retried to the second device which has output the retry request.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is an overall configuration diagram of a data transfer system according to the present invention.

The data transfer system includes a common bus 1, bus masters 2 and 3 connected to the common bus 1, bus slaves 4 and 5, and a retry control circuit 6.

The bus masters 2 and 3 output data to the common bus 1, and the bus slaves 4 and 5 receive the data, respectively. Conversely, the bus slaves 4 and 5 may output data to the common bus 1 and the bus masters 1 and 2 may receive the data respectively.

On the other hand, the bus slave 4 or 5 is connected to the common bus 1
When the data output to the bus master 4 cannot be received, a retry request signal P is output from the bus slave 4 or 5 to the common bus 1, the retry request signal P is received by the retry control circuit 6, and the retry control circuit 6 , 3 in place of data transfer to the bus slave 4 or 5.

Next, the configuration of the retry control circuit 6 will be described. FIG. 2 is a configuration diagram of the first embodiment of the retry control circuit.

The retry control circuit 6 includes a data control unit 12 to which a retry request signal P is input from a control signal line 11 constituting the common bus 1, and a data signal controlled by the data control unit 12 and constituting the common bus 1. A data buffer unit 14 for storing the data QN input from the line 13.

The data buffer section 14 is a buffer that always stores only one latest data QN on the data signal line 13. Therefore, when the retry request signal P is input to the data control unit 12, the data QN requesting the retry is stored in the data buffer unit.

Next, the operation of the retry control circuit 6 will be described. FIG. 3 is a flowchart showing the operation of the retry control circuit according to the first embodiment.

First, the latest data QN is written to the data buffer section 14 via the data signal line 13 (S
1).

Next, the data control unit 12 controls the control signal line 11
It is checked whether or not the retry request signal P has been generated via the data buffer (S2). If the retry request signal P has been generated, the latest data Q
N is read out and output to the data signal line 13 (S3).

The latest data QN is transmitted to the request source (for example, the bus slave 4 or 5) of the retry request signal P via the data signal line 13 of the common bus 1.

As a result, the request source can obtain the data QN requested to be retried.

On the other hand, if no retry request has been issued in S2, the process returns to S1.

The first embodiment shows a case where the retry control circuit 6 transfers data to a request source immediately after a retry request is generated. Such an operation is possible when the retry request P occurs intermittently.

However, when two or more retry requests P occur consecutively, data may not be transferred to the request source immediately after the retry request P is generated. This is because the common bus is in use (busy).

FIG. 4 is a schematic explanatory diagram showing an example of a bus access situation. In the figure, MA-A means bus master 1, MA-B means bus master 2, SU-A means bus slave 4, SU-B means bus slave 5, and R circuit means retry control circuit 6.

As shown in the figure, the bus access is, for example, first, the access 1 from the MA-A to the SU-A is normal ("normal" means that data has been transferred normally. The same applies hereinafter). ), The next access 2 from the MA-B to the SU-B is retried (retry means a state in which data is not normally transferred and a retry request is issued from the SU to the MA. The same applies hereinafter. ), Access 3 from the next MA-A to SU-B is retried, retransmission of access 2 from the next R circuit to SU-B is normal, and access 4 from the next MA-B to SU-B is retried. The re-transfer of the access 3 from the next R circuit to the SU-B is retried again.
-Retransfer of access 4 to B is normal, next R circuit
Retransmission of access 3 to UB proceeds normally.

That is, retransmission of data to access 2 is performed after retrying access 3. or,
Similarly, retransmission of data for access 4 is similar to access 3
This is done after retrying.

Further, the access 3 shows a state in which it becomes normal only after the second data retransfer.

The configuration of the retry control circuit 26 adapted to such an operation will be described. FIG. 5 is a configuration diagram of the second embodiment of the retry control circuit. The same components as those of the retry control circuit 6 are given the same numbers,
Description is omitted.

The retry control circuit 26 receives a retry request signal P from the control signal line 11 constituting the common bus 1 and a common bus input control section 27 which receives the retry request signal P from the control signal line 11 and a data signal line 13 constituting the common bus 1. Temporary storage unit 28 in which data QM from the latest data to a certain time before is always stored.
And the target data QR of the retry request from the temporary storage unit 28
Is read and stored, and data QR is read from data buffer unit 29 and data signal line 1 is read.
3 and a common bus output control unit 30 for outputting the data to the common bus output control unit 3.

The common bus input control unit 27 controls the transfer of the data QR from the temporary storage unit 28 to the data buffer unit 29.

Next, the operation of the retry control circuit 26 will be described with reference to a flowchart. FIG. 6 is a flowchart showing the operation of the retry control circuit according to the second embodiment.

First, data QM up to a predetermined time before the latest data input from the data signal line 13 is written into the temporary storage unit 28 (S11). Next, the common bus input control unit 27 checks whether a retry request P has occurred (S12). Next, when it is confirmed that the retry request P has occurred, the common bus input control unit 27 reads the read signal F1.
, The target data QR of the retry request P is read out from the temporary storage unit 28 in time series, and the read data QR is transferred to the data buffer unit 29 by the write signal F2 (S
13). Next, upon receiving the data output enable signal F3 from the data buffer unit 29, the common bus output control unit 30 outputs a read signal F4 to the data buffer unit 29, and outputs the data QR from the data buffer unit 29 in time series. Output to the line 13 (S14).

The data QR is transmitted to the request source (for example, the bus slave 4 or 5) of the retry request signal P via the data signal line 13.

On the other hand, if the retry request P has not occurred in S12, the process returns to S11.

The data buffer unit 29 is stored in a first-in first-out memory (FIFO; FirstIn First).
Out). In this case, when a retry request P is generated on the control signal line 11 of the common bus 1, the data QR from the temporary storage unit 28 is written to the first-in first-out memory 29, and then the data QR is read out from the first-in first-out memory 29 in time series. Output to signal line 13.

When the data buffer unit 29 is constituted by a first-in first-out memory, the step of reading and writing data in the order of addresses can be omitted, so that the circuit can be simplified.

[0037]

According to the present invention, the first device and the second device transfer data via the common bus, and transfer the data transferred from the first device to the second device to the second device. A data transfer system in which a retry request is output from the second device to the first device if the second device cannot receive the request; and the second device sends a retry request to the first device. Since there is a transfer means for receiving the output retry request and transferring the data for which the retry was requested to the second device, it is not necessary to measure the number of retries and the retry time, and the data transfer is performed during the retry. It is possible to continue.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a data transfer system according to the present invention.

FIG. 2 is a configuration diagram of a first embodiment of a retry control circuit of the system.

FIG. 3 is a flowchart showing an operation of the retry control circuit of the first embodiment of the system.

FIG. 4 is a schematic explanatory diagram showing an example of a bus access situation of the system.

FIG. 5 is a configuration diagram of a second embodiment of a retry control circuit of the system.

FIG. 6 is a flowchart illustrating an operation of a retry control circuit according to a second embodiment of the system.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 common bus 2, 3 bus master 4, 5 bus slave 6, 26 retry control circuit 12 data control unit 14 data buffer unit 27 common bus input control unit 28 temporary storage unit 29 data buffer unit 30 common bus output control unit

Claims (4)

[Claims] 1. A first device and a second device perform data transfer via a common bus, and the first device transmits data to the second device from the first device.
A data transfer system that outputs a retry request from the second device to the first device when the second device cannot receive the data transferred to the second device; A data transfer system for receiving a retry request output from the device to the first device and transferring the data requested to be retried to the second device. 2. The transfer means stores the latest data on the common bus at all times, and receives the retry request output from the second device, reads the latest data from the storage means, and reads the latest data from the storage means. 2. A data transfer system according to claim 1, further comprising data control means for transferring data to said second device. 3. The storage device according to claim 2, wherein the transfer unit stores data up to a predetermined time before the latest data on the common bus, and a retry request output from the second device. 2. The data transfer system according to claim 1, further comprising data control means for transferring the data requested to be retried to the second device in time series. 4. The data transfer system according to claim 3, wherein said data control means comprises a first-in first-out memory.