JPH1092811A5

JPH1092811A5 -

Info

Publication number: JPH1092811A5
Application number: JP1997184946A
Authority: JP
Filing date: 1997-07-10
Publication date: 2005-05-12
Anticipated expiration: 2017-07-10

Description

【００１８】
【課題を解決するための手段】
本願の第１発明は、半導体基板上に複数の絶縁膜と配線層が積層形成されたチップを有する半導体装置において、下層配線層と、該下層配線層上に積層され、上面が平坦に形成された最上層間絶縁膜と、該最上層間絶縁膜の平坦面上に積層され、Ａｌ系材料に比べて硬度の大きい金属で形成され、厚さが０．５μｍ以下の所定パターンの最上配線層と、該最上配線層上に積層された、鏡面状平坦面を有するパッシベーション膜と、該パッシベーション膜及び最上層間絶縁膜を開口して、前記下層配線層を露出させたボンディングパットとが形成された構成とすることにより、前記第１及び第２の課題を解決したものである。 [0018]
[Means for solving the problem]
The first invention of the present application solves the first and second problems by providing a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate, the semiconductor device comprising: a lower wiring layer; a top interlayer insulating film stacked on the lower wiring layer and having a flat upper surface ; a top wiring layer of a predetermined pattern stacked on the flat surface of the top interlayer insulating film and made of a metal harder than Al -based materials and having a thickness of 0.5 μm or less; a passivation film stacked on the top wiring layer and having a mirror-like flat surface; and a bonding pad formed by opening the passivation film and the top interlayer insulating film to expose the lower wiring layer .

第１発明は、又、半導体基板上に複数の絶縁膜と配線層が積層形成されたチップを有する半導体装置の製造方法において、基板上に下層配線層を形成する工程と、該下層配線層上に堆積させた絶縁材料を平坦化して最上層間絶縁膜を形成する工程と、該最上層間絶縁膜の平坦面上に、Ａｌ系材料に比べて硬度の大きい金属で形成され、厚さが０．５μｍ以下の所定パターンの最上配線層を形成する工程と、該最上配線層上の基板全体に絶縁膜を堆積し、ＣＭＰ法によって研磨することにより、鏡面状平坦面を有する最上絶縁膜を形成する工程と、該最上絶縁膜及び最上層間絶縁膜を開口して、前記下層配線層が露出したボンディングパットを形成する工程とを有することにより、上記半導体チップを確実に製造可能としたものである。 The first invention also provides a method for manufacturing a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate, comprising the steps of: forming a lower wiring layer on the substrate; planarizing the insulating material deposited on the lower wiring layer to form a top interlayer insulating film; forming a top wiring layer of a predetermined pattern made of a metal harder than Al-based materials and having a thickness of 0.5 μm or less on the flat surface of the top interlayer insulating film; depositing an insulating film over the entire substrate on the top wiring layer and polishing it by CMP to form a top insulating film having a mirror-like flat surface; and forming an opening in the top insulating film and the top interlayer insulating film to form a bonding pad in which the lower wiring layer is exposed , thereby enabling the semiconductor chip to be manufactured reliably.

本願の第２発明は、又、半導体基板上に複数の絶縁膜と配線層が積層形成されたチップを有する半導体装置において、下層配線層と、該下層配線上に設けられた、シリコン窒化膜もしくは酸化シリコン窒化膜からなるチップ保護膜を含む最上層間絶縁膜と、該最上層間絶縁膜上に設けられた、Ａｌ−Ｓｉ合金に比較して腐食に強い材料からなる最上配線層と、該最上層間絶縁膜を開口して、前記下層配線層を露出させたボンディングパットと、を有することにより、前記第１及び第３の課題を解決したものである。 The second invention of the present application also solves the first and third problems by providing a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate, a lower wiring layer, a top interlayer insulating film provided on the lower wiring layer and including a chip protective film made of silicon nitride film or silicon oxide nitride film, a top wiring layer provided on the top interlayer insulating film and made of a material that is more corrosion resistant than Al-Si alloy, and a bonding pad having an opening in the top interlayer insulating film to expose the lower wiring layer .

前記最上配線層には、通常配線材料として用いられるＡｌ−Ｓｉ合金等に比べて腐食に強い材料を用い、且つ、チップ内部を保護するために、その直下の最上層間絶縁膜にチップ保護性を持たせることにより、チップの信頼性を確保した上で、上記最上配線層を実質的に剥き出しの状態で使用可能とし、チップに他の部品や装置を直接取付けて電気的に接続することが可能となる。ここでチップ保護性というのは、半導体素子に悪影響を与える各種の外部要因の影響を受けないようにチップを保護することをいう。そのために要求される特性として、１）保護膜自体にピンホール、クラック、微小欠陥が存在しないこと、２）配線、特にＡｌ系の配線の腐食を誘発する水分の浸透を防止できること、３）半導体基板界面に形成されたトランジスタ等の特性を劣化させるアルカリイオン、特にＮａ＋イオンの浸透を防止できることである。このような特性を有する保護膜としてはプラズマＣＶＤ法で形成するシリコン窒化膜、酸化シリコン窒化膜等が用いられる。 The top wiring layer is made of a material that is more corrosion-resistant than commonly used wiring materials such as Al-Si alloys. Furthermore, the top interlayer insulating film directly below it is provided with chip protection to protect the chip's interior. This ensures chip reliability while allowing the top wiring layer to be used in a substantially exposed state, allowing other components and devices to be directly attached and electrically connected to the chip. Here, chip protection refers to protecting the chip from various external factors that adversely affect semiconductor devices. The required characteristics for this are: 1) the protective film itself is free of pinholes, cracks, and micro-defects; 2) it is able to prevent the penetration of moisture, which can induce corrosion of wiring, particularly Al-based wiring; and 3) it is able to prevent the penetration of alkali ions, particularly Na+ ions, which can degrade the characteristics of transistors formed at the semiconductor substrate interface. Examples of protective films with these characteristics include silicon nitride films and silicon oxide nitride films formed by plasma CVD.

本願の第３発明は、更に、反射型液晶表示装置において、下層配線層と、該下層配線層上に積層され、上面が平坦に形成された最上層間絶縁膜と、該最上層間絶縁膜の平坦面上に積層され、Ａｌ系材料に比べて硬度の大きい金属で形成され、厚さが０．５μｍ以下の所定パターンの最上配線層と、該最上配線層上に積層された、鏡面状平坦面を有するパッシベーション膜と、該パッシベーション膜及び最上層間絶縁膜を開口して、前記下層配線層を露出させたボンディングパットとを有するチップ、又は、下層配線層と、該下層配線層上に設けられ、上面が平坦に形成され、且つシリコン窒化膜もしくは酸化シリコン窒化膜からなるチップ保護性を有する最上層間絶縁膜と、該最上層間絶縁膜の平坦面上に積層され、Ａｌ−Ｓｉ合金に比較して腐食に強い特性を有する材料からなる最上配線層と、該最上層間絶縁膜を開口して前記下層配線層を露出したボンディングパットとを有するチップと、該チップ上に配設された、該チップにより駆動される反射型の液晶部とを備えることにより、前記第４の課題を解決したものである。 The third invention of the present application further relates to a reflective liquid crystal display device, which is a chip having a lower wiring layer, a top interlayer insulating film laminated on the lower wiring layer and having a flat upper surface, a top wiring layer of a predetermined pattern that is laminated on the flat surface of the top interlayer insulating film and is made of a metal that is harder than an Al -based material and has a thickness of 0.5 μm or less, a passivation film laminated on the top wiring layer and having a mirror-like flat surface , and a bonding pad that exposes the lower wiring layer by opening the passivation film and the top interlayer insulating film , or a chip having a lower wiring layer, a top interlayer insulating film that is provided on the lower wiring layer and has a flat upper surface and is made of a silicon nitride film or a silicon oxide nitride film and has chip protection properties, and a bonding pad that is laminated on the flat surface of the top interlayer insulating film, The fourth problem is solved by providing a chip having an uppermost wiring layer made of a material that is more resistant to corrosion than an Al-Si alloy , and a bonding pad that exposes the lower wiring layer by opening the uppermost interlayer insulating film , and a reflective liquid crystal unit that is disposed on the chip and is driven by the chip.

Claims

In a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate,
a lower wiring layer;
an uppermost interlayer insulating film laminated on the lower wiring layer and having a flat upper surface;
a top wiring layer of a predetermined pattern, laminated on the flat surface of the top interlayer insulating film, made of a metal having a hardness greater than that of an Al -based material, and having a thickness of 0.5 μm or less;
a passivation film having a mirror-like flat surface laminated on the uppermost wiring layer;
a bonding pad that exposes the lower wiring layer by opening the passivation film and the uppermost interlayer insulating film;
A semiconductor device characterized in that:

2. The semiconductor device according to claim 1, wherein the uppermost wiring layer is formed of any of Ti, Cr, Cu, Ni, Mo, W, Pt, or a silicide thereof, or a composite film of any of these with TiN formed thereon.

2. The semiconductor device according to claim 1, wherein said uppermost wiring layer is formed of a TiN/Ti film in which TiN is deposited on Ti.

a lower wiring layer;
an uppermost interlayer insulating film laminated on the lower wiring layer and having a flat upper surface;
a top wiring layer of a predetermined pattern, laminated on the flat surface of the top interlayer insulating film, made of a metal having a hardness greater than that of an Al -based material, and having a thickness of 0.5 μm or less;
a passivation film having a mirror-like flat surface laminated on the uppermost wiring layer ;
a chip having a bonding pad in which the passivation film and the uppermost interlayer insulating film are opened to expose the lower wiring layer ;
a reflective liquid crystal unit disposed on the chip and driven by the chip;
A reflective liquid crystal display device comprising:

5. A reflective liquid crystal display device according to claim 4, wherein the uppermost wiring layer is formed of any of Ti, Cr, Cu, Ni, Mo, W, Pt, or a silicide thereof, or a composite film of any of these with TiN formed thereon.

In a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate,
a lower wiring layer;
an uppermost interlayer insulating film including a chip protection film made of a silicon nitride film or a silicon oxide nitride film , which is provided on the lower layer wiring;
a top wiring layer formed on the top interlayer insulating film and made of a material that is more resistant to corrosion than an Al-Si alloy ;
a bonding pad that exposes the lower wiring layer by opening the uppermost interlayer insulating film;
A semiconductor device comprising :

7. The semiconductor device according to claim 6, wherein the uppermost wiring layer is made of any one of Ti, Cr, Co, Ni, Mo, Ag, W, Pt, Au, and TiN.

7. The semiconductor device according to claim 6, wherein the upper surface of said uppermost wiring layer is covered with TiN or W.

9. The semiconductor device according to claim 6, wherein the uppermost wiring layer serves as an electrode for electrical connection with other components or devices directly mounted on the chip.

a lower wiring layer;
an uppermost interlayer insulating film provided on the lower wiring layer, having a flat upper surface, and made of a silicon nitride film or a silicon oxide nitride film and having chip protection properties;
a top wiring layer formed on the flat surface of the top interlayer insulating film and made of a material that is more corrosion resistant than an Al-Si alloy ;
a chip having a bonding pad in which the uppermost interlayer insulating film is opened to expose the lower wiring layer ;
a reflective liquid crystal unit disposed on the chip and driven by the chip;
A reflective liquid crystal display device comprising:

11. The reflective liquid crystal display device according to claim 10, wherein the uppermost wiring layer is made of any one of Ti, Cr, Co, Ni, Mo, Ag, W, Pt, Au, and TiN.

11. The reflective liquid crystal display device according to claim 10, wherein the upper surface of the uppermost wiring layer is covered with TiN or W.

A method of manufacturing a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate, comprising:
forming a lower wiring layer on the substrate;
a step of planarizing the insulating material deposited on the lower wiring layer to form an uppermost interlayer insulating film;
forming a top wiring layer of a predetermined pattern on the flat surface of the top interlayer insulating film , the top wiring layer being made of a metal having a hardness greater than that of an Al-based material and having a thickness of 0.5 μm or less ;
a step of depositing an insulating film over the entire substrate on the uppermost wiring layer and polishing it by a CMP method to form an uppermost insulating film having a mirror-like flat surface;
forming an opening in the uppermost insulating film and the uppermost interlayer insulating film to form a bonding pad exposing the lower wiring layer;
1. A method for manufacturing a semiconductor device, comprising:

14. A method for manufacturing a semiconductor device according to claim 13, wherein the uppermost wiring layer is formed of any of Ti, Cr, Cu, Ni, Mo, W, Pt, or silicides thereof, or a composite film of any of these with TiN formed thereon.