JPH1093035A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a reduced capacitor part area and fine chip by providing a second delay capacitor part which is formed on the top of a gate electrode to be a first delay capacitor part and comprises a capacitor having the same structure as those for memory cells and provided in the same layer, where the capacitors for the memory cells are provided. SOLUTION: On a semiconductor substrate 1 a gate electrode 3 is formed through a gate insulation film 2 to form a first capacitor part. Source/drain diffusion layers 5, 6 are formed on a region, surrounded by an LOCOS oxide 4 to be an element isolation film from both ends of the gate electrode 3. A capacitor 10 is composed of a pair of upper and lower opposite facing electrodes 7, 9 through a capacitor insulation film 8, forming a second capacitor part which locates in an upper plane of the gate electrode 3 forming the first capacitance part. Many capacitor 10 having the same layer and same structure as those of capacitors for memory cells are formed and used for the delay, thereby realizing a fine chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device requiring a large capacitance for the purpose of delay in a circuit, by reducing the area of the capacitance portion and miniaturizing a chip. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, such a semiconductor device will be described with reference to the drawings. For example, DRAM (Dynamic Random A)
In some cases, a large capacitance portion is formed in a ccess memory circuit for the purpose of delay. Usually, such a capacitance portion is formed using a capacitance between a gate electrode (the same layer as an electrode forming a transistor) and a semiconductor substrate.

FIG. 3 is a cross-sectional view of a conventional delay capacitor section. A conventional delay capacitor section 50 includes a gate electrode 53 formed on a semiconductor substrate 51 with a gate insulating film 52 interposed therebetween.
LOCOS for element isolation is applied to the gate electrode 53 from both ends.
Source / drain diffusion layer 5 formed between oxide films 54
5 and 56 are formed, an arbitrary signal is input to the gate electrode 53, and the source electrode 55 and the drain electrode 56 are connected to GND.

[0004]

However, depending on the circuit, a large capacitance section may need to be formed in multiple stages (see an example of the delay circuit shown in FIG. 4). However, there is a problem that a large area pattern is required and the chip size becomes large. Therefore,
An object of the present invention is to provide a semiconductor device in which a chip is miniaturized by reducing the area of a capacitor portion.

[0005]

Therefore, a semiconductor device according to the present invention comprises a first delay capacitor section comprising a gate electrode 3 formed on a semiconductor substrate 1 with a gate insulating film 2 interposed therebetween, and the first delay capacitor section. On the gate electrode 3 serving as a capacitance part, a second delay capacitance part having a capacitor 10 of the same layer and having the same structure as that for the memory cell is provided.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. The semiconductor device of the present invention is a MOS transistor that forms a capacitance unit,
The configuration is as shown in FIG. Reference numeral 1 denotes a semiconductor substrate, on which a gate electrode 3 is formed via a gate insulating film 2 and a first capacitance portion is formed.

Further, source / drain diffusion layers 5 and 6 are formed in a region surrounded by a LOCOS oxide film 4 as an element isolation film from both ends of the gate electrode 3. Further, a capacitor 10 having the same layer and the same structure as a capacitor formed for a memory cell (not shown) is formed above the gate electrode 3. The capacitor 10 has a pair of upper and lower electrodes, a first
And a second electrode 9 as a counter electrode facing the first electrode 7 to form a second capacitor.

As described above, the gate electrode 3 and the first electrode 7 are in contact with each other and have the same potential, and these form a capacitance portion between the semiconductor substrate 1 and the second electrode 9, respectively. Become. Then, the second electrode 9 is Ｖ V
It is connected to CC, and the source and drain electrodes are connected to GND.

As described above, the delay capacitor section 11 of the present invention is composed of the first and second capacitor sections. The feature of the present invention is that the gate electrode 3 forming the first capacitor section described above. By forming a large number of capacitors 10 having the same layer and the same structure as the capacitor for the memory cell forming the second capacitance portion in the upper plane of the capacitor 10 and diverting them for delay, the conventional capacitance portion is formed. The pattern area is １ ／ compared to the structure of
The size can be reduced to about 1/3, and the chip can be miniaturized.

Hereinafter, another embodiment of the present invention will be described. The same components as those in the embodiment are denoted by the same reference numerals, and description thereof will be omitted. In the above-described embodiment, the configuration is such that a large number of capacitors 10 serving as the second capacitance portions are formed in the upper plane of the gate electrode 3. May be formed from a single electrode having a large area. Similarly, the area of the capacitor can be reduced as compared with the related art.

Further, as shown in FIG. 2, a structure may be employed in which the second electrode 9, the source electrode 5 and the drain electrode 6 are all connected to GND. The present invention solves the conventional problem that a large area pattern is required by a circuit requiring a large capacitance portion and the chip cannot be miniaturized by using a technology for manufacturing a capacitor for a DRAM memory cell. Thus, the problem can be solved by forming the second capacitor on the gate electrode 3 serving as the first capacitor for delay.

Although the present embodiment has been described in connection with the case where a large capacity portion is required in a DRAM circuit, the present invention is not limited to this, and can be applied to various circuits. In this case, the manufacturing process does not become complicated, which is more effective.

[0013]

As described above, according to the present invention, a capacitor having the same structure and the same structure as that for the memory cell forming the second capacitance section is formed above the gate electrode forming the first capacitance section. By diverting this for delay, the pattern area can be reduced to about 1/2 to 1/3 as compared with the conventional structure of the capacitor section, and the chip can be miniaturized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a conventional semiconductor device serving as a delay capacitance unit.

FIG. 4 is a circuit configuration diagram of a conventional delay circuit.

Claims (3)

[Claims] A gate electrode formed on a semiconductor substrate via a gate insulating film; a source / drain region formed between element isolation films from both ends of the gate electrode; and a gate electrode formed on the gate electrode. And a capacitor having the same layer as the memory cell and having the same structure. 2. A first delay capacitance portion comprising a gate electrode formed via a gate insulating film on a semiconductor substrate, and a first delay capacitance portion for a memory cell above the gate electrode serving as the first delay capacitance portion. A semiconductor device, comprising: a second delay capacitor portion having a same layer and a capacitor having the same structure. 3. The capacitor according to claim 1, wherein the opposite electrode has a voltage of 1 / 2V.
A semiconductor device connected to CC or connected to GND.