JPH1093043A - Semiconductor device having a capacitor - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor device having a capacitor provided with a barrier layer that does not cause interdiffusion of platinum and silicon or platinum and titanium even when heated to a high temperature. SOLUTION: The capacitor 30 of the present invention includes a plug 1
1, barrier layers 14 a and 14 b, and a lower electrode layer 15. The plug 11 is formed on the impurity region 8,
Contains silicon. Barrier layer 14a is formed on plug 11 and includes titanium nitride. The barrier layer 14b is formed on the barrier layer 14a and is made of titanium dioxide (TiO ₂ ).
including. The lower electrode layer 15 is formed on the barrier layer 13b and contains platinum.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a capacitor using a high dielectric constant material as a dielectric film.

[0002]

2. Description of the Related Art In recent years, with the remarkable spread of information devices such as computers, demand for semiconductor memory devices has been rapidly expanding. Functionally, a device having a large-scale storage capacity and capable of high-speed operation is required. Along with this, technology development related to high integration and high responsiveness or high reliability of semiconductor memory devices is being promoted.

In a semiconductor memory device, a DRAM (Dynamic Radar) is known as a device capable of randomly inputting and outputting storage information.
ndom Access Memory) is generally known. This D
When the integration of the RAM is promoted, the memory cells must be reduced. As the memory cells are reduced, the planar occupation area of the capacitors is also reduced at the same time. Therefore, the amount of charge stored in the capacitor (the amount of charge stored in the 1-bit memory cell) decreases. If the amount of charge stored in the one-bit memory cell falls below a certain value, the operation of the DRAM as a storage area becomes unstable, and reliability decreases.

In order to prevent the operation of the DRAM from becoming unstable, it is necessary to increase the capacitance of the capacitor within a limited plane occupation area. As means for increasing the capacity of the capacitor, thinning of the capacitor dielectric film, increase of the dielectric constant of the capacitor dielectric film, and the like have been studied.

[0005] The thinning of the capacitor dielectric film shown in the above has reached the limit as long as a silicon oxide film usually used as a capacitor dielectric film is used. For this reason,
In order to increase the capacitance of a capacitor using a capacitor dielectric film made of a silicon oxide film, it is necessary to form the capacitor into a complicated shape such as a cylindrical shape or a fin shape. However, when manufacturing a capacitor having such a complicated shape, there is a problem that the manufacturing method becomes extremely complicated.

Accordingly, recently, techniques related to the increase in the dielectric constant of the capacitor described above have been actively pursued. In order to increase the dielectric constant of the capacitor dielectric film, there is a method in which a material having a high dielectric constant, that is, a material called a high dielectric constant material is used for the capacitor dielectric film. This high dielectric constant material generally has a dielectric constant several times to several hundred times that of a silicon oxide film. Therefore, by using this high dielectric constant material for the capacitor dielectric film, it is possible to increase the capacitance while maintaining the simple shape of the capacitor.

[0007] As one kind of a material called this high dielectric constant material, tantalum oxide (Ta ₂ O ₅ ), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium titanate (ST
O) and barium titanate (BTO).
Since such a high dielectric constant material is crystalline, a platinum group element having a lattice constant close to that of the high dielectric constant material is used for a portion in contact with the high dielectric constant material. Therefore, a conventional DRAM capacitor is one in which a platinum group element and a silicon substrate are electrically connected.

However, these platinum group elements have high reactivity with elements such as silicon, and in a structure in which they are in contact with each other, a solid phase reaction easily occurs by heat treatment at a temperature of 400 ° C. A silicide is formed. As a result, the crystal structure of platinum changes, and the high-permittivity material does not grow epitaxially on the surface of platinum. Also,
When forming a high dielectric constant material, an oxidizing atmosphere must be used. In this atmosphere, platinum silicide is oxidized and a silicon oxide film is formed on the surface of the platinum silicide. Since this silicon oxide film has a lower dielectric constant than a high dielectric constant material, it causes a decrease in the dielectric constant of the dielectric film.

Therefore, when a high dielectric constant material is used as a dielectric film of a capacitor, some kind of diffusion prevention layer is required between a lower electrode layer made of platinum and a conductive layer made of polysilicon. Generally, titanium nitride, which is widely used as a barrier metal for an aluminum wiring layer, is often used as a diffusion prevention layer. In this case, the temperature 50
It is known that it functions as a diffusion preventing layer up to about 0 ° C.

Here, a conventional DRAM using a titanium nitride layer as a diffusion preventing layer will be described with reference to the drawings.

FIG. 9 is a sectional view showing the structure of a conventional DRAM. Referring to FIG. 9, an isolation oxide film 102 is formed on a surface of a silicon substrate 101. Isolation oxide film 10
A plurality of transfer gate transistors 103 are formed on the surface of a silicon substrate 101 which is electrically separated by 2. In the memory cell region 104, a transfer gate transistor 103 for a memory cell is formed. In the peripheral circuit region 105, a transfer gate transistor 103 for the peripheral circuit is formed.

Transfer gate transistor 103
Has a gate oxide film 106, a gate electrode 107, and an impurity region 108. A gate electrode 107 made of doped polysilicon is formed on a region sandwiched between impurity regions 108 with a gate oxide film 106 interposed therebetween.

A bit line 109 made of doped polysilicon is formed so as to be in contact with impurity region 108. A silicon oxide film 112 is formed to cover bit line 109 and transfer gate transistor 103.

The impurity region 10 is formed on the silicon oxide film 112.
A contact hole 110 reaching 8 is formed.
A plug 111 made of doped polysilicon is formed so as to fill contact hole 110 and contact impurity region 108. Capacitor 130 is formed to be electrically connected to impurity region 108 through plug 111.

The capacitor 130 includes a lower electrode layer 115 made of platinum and a capacitor dielectric film 11 made of PZT.
7 and an upper electrode layer 118 made of platinum.

The lower electrode layer 115 includes a barrier layer 114 made of titanium nitride and an adhesion layer 11 made of titanium silicide.
3 is formed so as to be in contact with the plug 111 via the first and third plugs. A framed oxide film 116 made of silicon dioxide is formed between capacitors 130. The capacitor 130 is
It is formed only in the memory cell region 104. Upper electrode layer 118, capacitor dielectric film 117, and framed oxide film 11
A silicon oxide film 120 is formed so as to cover 6 and silicon oxide film 112.

[0017]

Here, the problem that occurs in the above-mentioned conventional DRAM will be described.

Referring to FIG. 9, generally, a memory cell region 104 in which a memory cell is formed is a peripheral circuit region 105.
It is higher than. Therefore, the memory cell area 1
When the silicon oxide film 120 covers the area 04 and the peripheral circuit region 105, a step occurs in the silicon oxide film 120 near the boundary between the memory cell region 104 and the peripheral circuit region 105.

Such a step is not preferable because it causes a problem in the photomechanical process. Therefore, in order to reduce such a level difference, interlayer reflow for heating and planarizing the silicon oxide film 120 is generally performed. The silicon oxide film 120 is planarized by interlayer reflow,
The step is reduced.

Here, in order to perform interlayer reflow,
It is necessary to heat the silicon oxide film 120 to a temperature of 700 to 800C. When heated to such a high temperature, the titanium nitride contained in the barrier layer 114 generally does not function as a diffusion barrier. Therefore, when heated to a high temperature, the silicon in the plug 111 and the lower electrode layer 11
The platinum in 5 causes interdiffusion, and the platinum reacts with silicon to deposit platinum silicide on the surface of the lower electrode layer 115. Further, silicon in the platinum silicide is oxidized to form a silicon oxide film. Since this silicon oxide film has a significantly lower dielectric constant than a high dielectric constant material such as PZT, there is a problem that the capacity of the capacitor is reduced at once if the silicon oxide film is formed.

When heated to a high temperature, platinum in the lower electrode layer 115 reacts with titanium in the barrier layer 114,
Titanium is deposited between the lower electrode layer 115 and the capacitor dielectric film 117. The deposited titanium is oxidized to form titanium oxide, whereby the capacitor dielectric film 1 is formed.
There is also a problem that the dielectric constant of No. 17 is lowered.

The titanium nitride in the barrier layer 114 is oxidized by the catalytic action of platinum in the lower electrode layer 115,
Form titanium oxide. When forming titanium oxide,
Since the crystal structure of titanium nitride changes, the barrier layer 114
And the lower electrode layer 115 has poor adhesion, which causes a problem that a leak current occurs.

Further, when ruthenium oxide is used for the barrier layer 114 and ruthenium is used for the adhesion layer 113,
Oxygen in the barrier layer 114 oxidizes ruthenium in the adhesion layer 113, and the shape of the adhesion layer 113 changes due to volume expansion at that time. Due to this change in shape, the adhesion between the adhesion layer 113 and the barrier layer 114 is reduced, and there is a problem that a leak current is generated.

Also, there is a problem that oxygen in the barrier layer 114 made of ruthenium oxide is oxidized to the plug 111 below the adhesion layer 113, thereby deteriorating the capacitor characteristics.

Accordingly, the present invention has been made to solve the above-described problem, and a barrier layer which does not cause interdiffusion of platinum and silicon and does not react with platinum even when heated to a high temperature. It is an object to provide a semiconductor device having a used capacitor.

[0026]

A semiconductor device having a capacitor according to one aspect of the present invention includes an impurity region, a first conductive layer, a second conductive layer, a third conductive layer, It has a lower electrode layer, a dielectric layer, and an upper electrode layer.

The impurity region is formed on the main surface of the semiconductor substrate. The first conductive layer contains silicon and is formed over the impurity region. The second conductive layer includes a nitride and is formed on the first conductive layer. The third conductive layer includes a metal oxide and is formed over the second conductive layer. The lower electrode layer contains a platinum group element and is formed on the third conductive layer. The dielectric layer is formed on the lower electrode layer. The upper electrode layer contains a platinum group element and is formed on the dielectric layer. Here, the platinum group element refers to platinum (Pt), ruthenium (Ru), iridium (Ir), rhenium (Re), rhodium (Rh), osmium (Os), and palladium (Pd).

In the semiconductor device having the capacitor of the present invention thus configured, the first device including silicon
A third conductive layer containing a metal oxide is formed between the conductive layer and the lower electrode layer containing a platinum group element. Therefore, even if the third conductive layer is heated to a high temperature, interdiffusion between the platinum group element and silicon can be prevented. Therefore, silicon and silicon dioxide do not precipitate on the surface of the lower electrode layer,
The dielectric constant of the dielectric film does not decrease. as a result,
The capacity of the capacitor is not reduced. Further, since the metal oxide in the third conductive layer is chemically stable, it does not react with platinum in the lower electrode layer even when heated to a high temperature. Therefore, the third conductive layer does not expand, and the adhesion between the third conductive layer and the lower electrode layer does not decrease. Therefore,
No leak current occurs. In addition, the third containing a metal oxide
A second conductive layer containing nitride is formed between the first conductive layer containing silicon and the first conductive layer containing silicon. Therefore, this second
Even if the conductive layer is heated to a high temperature, diffusion of oxygen in the metal oxide can be prevented, and silicon does not react with oxygen. Therefore, the first conductive layer does not expand, and the first conductive layer does not expand.
And the second conductive layer do not have reduced adhesion. As a result, no leak current occurs.

Preferably, a titanium silicide layer is formed between the first conductive layer and the second conductive layer. In this case, titanium silicide has good adhesion to both silicon in the first conductive layer and nitride in the second conductive layer. Therefore, the first conductive layer and the second conductive layer can be reliably connected.

Further, it is preferable that an impurity for improving the conductivity of the metal oxide is added to the metal oxide. In this case, the electric resistance is reduced, and the electric characteristics of the capacitor can be improved.

A semiconductor device having a capacitor according to another aspect of the present invention includes an impurity region, a first conductive layer,
It has a second conductive layer, a third conductive layer, a lower electrode layer, a dielectric layer, and an upper electrode layer. The impurity region is formed on the main surface of the semiconductor substrate. The first conductive layer is
It contains silicon and is formed over the impurity region. Second
The conductive layer includes an oxygen diffusion preventing material and is formed on the first conductive layer. The third conductive layer includes a metal oxide and is formed over the second conductive layer. The lower electrode layer contains a platinum group element and is formed on the third conductive layer. The dielectric layer is formed on the lower electrode layer.
The upper electrode layer contains a platinum group element and is formed on the dielectric layer.

In the semiconductor device having the capacitor of the present invention thus configured, the first device including silicon
A third conductive layer containing a metal oxide is formed between the conductive layer and the lower electrode layer containing a platinum group element. Therefore, even if the third conductive layer is heated to a high temperature, interdiffusion between the platinum group element and silicon can be prevented. Therefore, silicon and silicon dioxide do not deposit on the surface of the lower electrode layer. Therefore, the dielectric constant of the dielectric layer does not decrease. As a result, the capacity of the capacitor does not decrease. Further, since the metal oxide in the third conductive layer is chemically stable, it does not react with platinum in the lower electrode layer even when heated to a high temperature. Therefore, the third conductive layer does not expand, and the adhesion between the third conductive layer and the lower electrode layer does not decrease. Therefore, no leak current occurs. Further, a second conductive layer containing an oxygen diffusion preventing material is formed between the third conductive layer containing a metal oxide and the first conductive layer containing silicon. This second conductive layer prevents diffusion of oxygen in the metal oxide. Therefore, silicon does not react with oxygen. Therefore, the first conductive layer does not expand, and the first conductive layer does not expand.
And the second conductive layer do not have reduced adhesion. As a result, no leak current occurs.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a sectional view showing a semiconductor device having a capacitor according to a first embodiment of the present invention. FIG.
As shown in FIG.
A 00 nm isolation oxide film 2 is formed. A plurality of transfer gate transistors 3 are formed on the surface of the silicon substrate 1 electrically separated by the isolation oxide film 2. In the memory cell region 4, a transfer gate transistor 3 for a memory cell is formed.
In the peripheral circuit region 5, the transfer gate transistor 3 for the peripheral circuit is formed.

The transfer gate transistor 3 has a gate oxide film 6, a gate electrode 7, and an impurity region 8. A gate electrode 7 made of doped polysilicon is formed on a region surrounded by impurity region 8 with gate oxide film 6 interposed.

A bit line 9 made of doped polysilicon is formed in contact with impurity region 8. A silicon oxide film 12 of BPSG (Poro Phospho Silicate Glass) with a thickness of 500 to 800 nm is formed so as to cover the bit line 9 and the transfer gate transistor 3.

A contact hole 10 reaching impurity region 8 is formed in silicon oxide film 12. A plug 11 made of doped polysilicon is formed so as to fill contact hole 10 and contact impurity region 8. Capacitor 30 is formed to be electrically connected to impurity region 8 through plug 11.

The capacitor 30 includes a lower electrode layer 15 made of platinum, a capacitor dielectric film 17 made of PZT,
And an upper electrode layer 18 made of platinum. The thickness of the lower electrode layer 15 is 30 to 100 nm. The thickness of the capacitor dielectric film 17 is 30 to 80 nm. The thickness of the upper electrode layer 18 is 30 to 100 nm.

The lower electrode layer 15 is connected to the plug 11 via a barrier layer 14b as a metal oxide layer, a barrier layer 14a as a nitride layer as an oxygen diffusion suppressing layer, and an adhesion layer 13 as titanium silicide. It is formed so that it may contact. The thickness of the barrier layer 14a is 30 to 70 nm. The thickness of the barrier layer 14b is 30 to 70 nm. The thickness of the adhesion layer 13 is about 10 nm. The barrier layer 14a is made of TiN. The barrier layer 14b is made of TiO ₂ to which Ta ₂ O ₅ is added. A framed oxide film 16 made of silicon dioxide is formed between the capacitors 30. Capacitor 30 is formed only in memory cell region 4. Upper electrode layer 18, capacitor dielectric film 17, framed oxide film 16
A silicon oxide film 20 made of BPSG is formed to cover silicon oxide film 12 and silicon oxide film 12.

Next, a method of manufacturing a semiconductor device having the capacitor shown in FIG. 1 will be described.

FIGS. 2 to 9 are sectional views showing a method of manufacturing a semiconductor device having the capacitor shown in FIG.

Referring to FIG. 2, transfer gate transistor 3 having gate oxide film 6, gate electrode 7 and impurity region 8 is formed in a region of silicon substrate 1 separated by isolation oxide film 2. Bit line 9 is formed so as to be in contact with impurity region 8. A silicon oxide film 12 is formed on the entire surface of silicon substrate 1 using low pressure CVD so as to cover bit line 9 and transfer gate transistor 3.

Referring to FIG. 3, a photoresist (not shown) having a hole pattern is formed on the entire surface of silicon oxide film 12. The contact hole 10 is formed by anisotropically etching the silicon oxide film 12 using this photoresist as a mask. Doped polysilicon is deposited by a CVD method so as to fill the contact hole 10 and cover the entire surface of the silicon oxide film 12. The thickness of the doped polysilicon needs to be 1.5 times or more the inner diameter of the contact hole 10. The entire surface of the doped polysilicon is etched back to form a plug 11
To form

Referring to FIG. 4, a titanium silicide layer 31 is formed on silicon oxide film 12 and plug 11 by a sputtering method in an argon atmosphere. The thickness of the titanium silicide layer 31 is about 10 nm. Next, using a target made of titanium, a temperature of 200 to 500
Barrier layer 32 made of TiN by a reactive sputtering method in an atmosphere of a mixed gas of argon and nitrogen at a temperature of 1 ° C. and a total pressure of 1 Pa.
a is formed. The thickness of the barrier layer 32a is 30 to 70 nm
It is. The volume ratio between argon and nitrogen (Ar / N ₂ ) in the mixed gas is 1. Next, TiO _2, Ta ₂
Using a target sintered by adding 1 mol% of O ₅ ,
The barrier layer 32b is formed by RF magnetron sputtering in an atmosphere of a temperature of 200 to 500 ° C., a total pressure of 1 Pa, and a mixed gas of argon and oxygen. The thickness of the barrier layer 32b is 50 nm. The volume ratio of argon to oxygen (Ar / O ₂ ) in the mixed gas is 4. The barrier layer 32b is made of TiO ₂ to which Ta ₂ O ₅ as an impurity is added.
Next, the platinum layer 33 is formed by sputtering using platinum as a target in an argon atmosphere at a total pressure of 0.2 to 1.2 Pa.
To form The thickness of the platinum layer 33 is 30 to 100 nm.

Referring to FIG. 5, a titanium silicide layer 31 and a barrier layer 32 are formed in an argon atmosphere at a total pressure of 1 to 3 Pa.
The adhesion layer 13, the barrier layers 14a and 14b, and the lower electrode layer 15 are formed by sputter-etching the a, 32b and the platinum layer 33. A silicon oxide film covering the silicon oxide film 12 is deposited to a thickness of 200 to 800 nm, and is etched back to form the framed oxide film 16. At this time, in the peripheral circuit region 5, the silicon oxide film is entirely etched.

Referring to FIG. 6, a temperature of 300 to 700 ° C.
In a mixed gas atmosphere of argon and oxygen, total pressure 0.5-2P
In step a, a high dielectric constant layer 36 made of PZT is formed by a sputtering method. The thickness of the high dielectric constant layer 36 is 30 to 80 nm. Next, using platinum as a target, a temperature of 400 to 60
A platinum layer 37 is formed by a sputtering method at 0 ° C. in an argon atmosphere at a pressure of 0.5 to 2 Pa. The thickness of the platinum layer 37 is 30 to 100 nm.

Referring to FIG. 7, a photoresist (not shown) having a predetermined pattern is formed on platinum layer 37, and platinum layer 37 and high dielectric constant layer 36 are etched according to the photoresist. Thereby, the upper electrode layer 18
And a capacitor dielectric film 17 are formed. Thus, the capacitor 30 is formed.

Referring to FIG. 8, BPSG is formed so as to cover capacitor 30 and silicon oxide film 12 by CVD.
A silicon oxide film 26 is formed. Next, the temperature of the silicon oxide film 26 is maintained at 700 to 800 ° C., and the silicon oxide film 26 is planarized. Such flattening of the silicon oxide film by heating is called interlayer reflow. Thus, a silicon oxide film 20 is formed.

As described above, the semiconductor device having the capacitor of the present invention is completed. In the semiconductor device having the capacitor of the present invention thus configured,
As shown in FIG. 1, TiO is formed between a plug 11 made of doped polysilicon and a lower electrode layer 15 made of platinum.
_A barrier layer 14b of ₂ is formed. Therefore, even if the barrier layer 14b is heated to a high temperature, the TiO
_{According to 2} , interdiffusion between silicon and platinum can be prevented. Therefore, silicon or silicon dioxide does not precipitate at a portion where the lower electrode layer 15 and the capacitor dielectric film 17 are in contact. Therefore, the dielectric constant of the capacitor dielectric film 17 made of PZT does not decrease. As a result, the capacity of the capacitor does not decrease.

The barrier layer 1 in contact with the lower electrode layer 15
4b is composed of TiO _2. This TiO ₂ does not react with platinum constituting the lower electrode layer 15 even when heated to a high temperature. Therefore, the crystal structure of the barrier layer 14b does not change even when heated to a high temperature. As a result, the adhesion between the barrier layer 14b and the lower electrode layer 15 does not decrease, and no leak current occurs.

Further, a barrier layer 14b made of TiO ₂
Between the plug 11 and the plug 11 made of doped polysilicon.
A barrier layer 14a made of iN is formed. The barrier layer 14a can prevent diffusion of oxygen in the barrier layer 14b. Therefore, the plug 11 is not oxidized.
Therefore, volume expansion of the plug 11 can be prevented,
Generation of a leak current can be prevented.

An adhesion layer 13 made of titanium silicide is formed between the plug 11 and the barrier layer 14a. The adhesion layer 13 has good adhesion to both the barrier layer 14a and the plug 11, so that the plug 11 and the barrier layer 14a
Can be reliably connected.

The TiO ₂ constituting the barrier layer 14b is
Since Ta ₂ O ₅ is added as an impurity therein, the conductivity of the barrier layer 14b is improved. Therefore, the electrical characteristics of the entire capacitor can be improved.

Further, as a material constituting the barrier layer 14b, a material obtained by adding Ta ₂ O ₅ as an impurity to TiO ₂ as a metal oxide was used. 1 may be used.

[0054]

[Table 1]

As the metal oxide constituting the barrier layer 14b, “metal conductive oxide” such as Tsuda, Nasu, Fujimori,
Those described in Shiratori, Shokabo 1983, pp. 26-33, Table 2-2 may be used.

(Embodiment 2) In a semiconductor device having a capacitor according to Embodiment 2, barium strontium titanate (Ba-Sr) TiO ₃ is used for the capacitor dielectric film 17 of Embodiment 1 shown in FIG. Further, the barrier layer 14b is made of barium strontium titanate as a metal oxide containing lanthanum (La) as an impurity in an amount of 0.1%.
mol% is added. Alternatively, the capacitor dielectric film 17 may be made of lanthanum titanate (LaTiO ₃ ), and the barrier layer 14b may be made of lanthanum titanate as a metal oxide to which lanthanum (La) is added as an impurity.

Next, a method of manufacturing a semiconductor device having a capacitor according to the second embodiment will be described. Figure 2
Referring to FIG. 4, isolation oxide film 2, transfer gate transistor 3, memory cell region 4, peripheral circuit region 5, gate oxide film 6, gate electrode 7, impurity region 8, bit line 9, silicon oxide film 12, contact The hole 10, the plug 11, the titanium silicide layer 31, and the barrier layer 32a are formed. Next, using a (Ba—Sr) TiO ₃ target, by RF magnetron sputtering, in a mixed gas atmosphere of argon and oxygen at a total pressure of 1 Pa and a thickness of 30 to 70 n
The m barrier layers 32b are formed. The volume ratio of argon to oxygen (Ar / O ₂ ) in the mixed gas is 4. When lanthanum titanate is used for the barrier layer 32b, LaTiO ₃ may be used as a target. Lanthanum (La) as an impurity is added to the barrier layer 32b by 0.1 mol% by a plasma doping method.

Referring to FIGS. 5 and 6, similarly to the first embodiment, barrier layers 14a and 14b, lower electrode layer 15, and framed oxide film 16 are formed. Next, as a target (B
a-Sr) Using TiO ₃ , a high dielectric layer 36 having a thickness of 50 nm is formed by RF magnetron sputtering at a total pressure of 1 Pa in a mixed gas atmosphere of argon and oxygen. The volume ratio of argon to oxygen (Ar / O ₂ ) in the mixed gas is 4. The high dielectric layer 36 is made of barium strontium titanate (Ba—Sr) TiO ₃ . High dielectric constant layer 36
A platinum layer 37 is formed thereon in the same manner as in the first embodiment.

Referring to FIGS. 7 and 8, Embodiment 1
Similarly, the capacitor dielectric film 17 and the upper electrode layer 18 are formed, and the capacitor 30 is formed. Silicon oxide film 2
0 is formed.

The semiconductor device having the capacitor according to the second embodiment of the present invention configured as described above has the same effects as the first embodiment. In the steps shown in FIGS. 4 and 6, the barrier layer 32b and the high dielectric constant layer 36 can be formed in the same device. Therefore, the manufacturing process can be simplified.

When the barrier layer 14b is made of lanthanum titanate, the lanthanum titanate has a lattice constant close to that of platinum and has a lattice structure similar to that of platinum, so that the lower electrode layer 15 and the barrier layer 14b are in close contact with each other. And the generation of leakage current can be further reduced.

(Embodiment 3) In a semiconductor device having a capacitor according to Embodiment 3, a barrier layer 14a shown in FIG.
₃ N ₄ ).

Next, a method of manufacturing a semiconductor device having a capacitor according to the third embodiment of the present invention will be described. Referring to FIGS. 1-4, similarly to the first embodiment, isolation oxide film 2, transfer gate transistor 3, memory cell region 4, peripheral circuit region 5, gate oxide film 6, gate electrode 7, impurity region 8 , Bit line 9, silicon oxide film 12, contact hole 10, plug 11, adhesion layer 31
To form Next, a mixed gas of dichlorosilane and ammonia (volume ratio: dichlorosilane / ammonia = 3/4) was used as a source gas, the total pressure was 100 Pa, and the temperature was 700.
Barrier layer 3 made of silicon nitride by thermal CVD
2a is formed. The thickness of the barrier layer 32a is 2 nm. As in the first embodiment, the barrier layer 32b and the platinum layer 33
To form

Referring to FIGS. 5 to 8, barrier layer 14a,
14b, the lower electrode layer 15, the framed oxide film 16, the high dielectric constant layer 36, the platinum layer 37, the capacitor dielectric film 17, the upper electrode layer 18, and the silicon oxide film 20 are formed in the same manner as in the first embodiment.

In the semiconductor device having the capacitor according to the third embodiment of the present invention, silicon nitride having low conductivity is thinned and barrier layer 14 is formed.
By using as a, the conductivity of the barrier layer 14a does not decrease. Further, silicon nitride can further prevent diffusion of oxygen in the barrier layer 14b, and the plug 11 does not react with oxygen even when heated to a higher temperature.

Although the embodiment of the present invention has been described above, the embodiment shown here is only an example,
Various deformations are possible. For example, although the adhesion layer 13 in FIG. 1 is made of titanium silicide in the first to third embodiments, another metal silicide may be used. Examples of the metal silicide include tungsten silicide, tantalum silicide, cobalt silicide, platinum silicide, and the like.

Further, as a material constituting the barrier layer 14a, not only titanium nitride but also other nitrides such as tantalum nitride, tungsten nitride, and molybdenum nitride can be used.

Further, metal silicide nitride can be used as the barrier layer 14a. Here, titanium silicide nitride (TiSiN), tantalum silicide nitride (TaSiN), tungsten silicide nitride (WSiN), and molybdenum silicide nitride (MoSiN) can be used as the metal silicide nitride. Further, as the upper electrode layer 18 and the lower electrode layer 15, not only platinum but also ruthenium, iridium, rhenium, rhodium, osmium, palladium, and alloys thereof can be used.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0070]

According to a semiconductor device having a capacitor according to one aspect of the present invention, a first device including silicon is provided.
A third conductive layer containing a metal oxide is formed between the conductive layer and the lower electrode layer containing a platinum group element. Therefore, even if the third conductive layer is heated to a high temperature, interdiffusion between the platinum group element and silicon can be prevented. Therefore, silicon and silicon dioxide do not precipitate on the surface of the platinum group element.
Therefore, the dielectric constant of the dielectric layer does not decrease, and the capacitance of the capacitor does not decrease.

If an adhesion layer containing titanium silicide is formed between the first conductive layer and the second conductive layer,
The first conductive layer and the second conductive layer can be reliably connected.

Further, if impurities are added to the metal oxide, the conductivity of the metal oxide can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device having a capacitor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a first step of a method for manufacturing a semiconductor device having the capacitor shown in FIG.

FIG. 3 is a sectional view showing a second step of the method for manufacturing a semiconductor device having the capacitor shown in FIG. 1;

FIG. 4 is a cross-sectional view showing a third step of the method for manufacturing a semiconductor device having the capacitor shown in FIG. 1;

FIG. 5 is a sectional view showing a fourth step of the method for manufacturing a semiconductor device having the capacitor shown in FIG. 1;

FIG. 6 is a sectional view showing a fifth step of the method for manufacturing a semiconductor device having the capacitor shown in FIG. 1;

FIG. 7 is a cross-sectional view showing a sixth step of the method for manufacturing a semiconductor device having the capacitor shown in FIG.

FIG. 8 is a cross-sectional view showing a seventh step of the method for manufacturing a semiconductor device having the capacitor shown in FIG. 1;

FIG. 9 is a cross-sectional view showing the structure of a conventional DRAM.

[Explanation of symbols]

1 silicon substrate, 8 impurity regions, 11 plugs, 1
3 adhesion layer, 14a, 14b barrier layer, 15 lower electrode layer, 17 capacitor dielectric film, 18 upper electrode layer.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Keiichiro Kashiwara 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Yasushi Sho 4-1-1 Mizuhara, Itami-shi, Hyogo Ryoden Semi Conductor System Engineering Co., Ltd. (72) Inventor Makoto Matsushita 4-1-1 Mizuhara, Itami-shi, Hyogo Ryoden Semiconductor Conductor System Engineering Co., Ltd. (72) Takashi Utatsu 4-1-1, Mizuhara, Itami-shi, Hyogo Ryoden (72) Inventor Kiyoshi Hanafusa 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation

Claims (4)

[Claims] An impurity region formed on a main surface of a semiconductor substrate and a first region including silicon formed on the impurity region.
And a second layer containing nitride formed on the first conductive layer.
A third conductive layer including a metal oxide formed on the second conductive layer, and a lower electrode including a platinum group element formed on the third conductive layer A semiconductor device having a capacitor, comprising: a layer; a dielectric layer formed on the lower electrode layer; and an upper electrode layer containing a platinum group element formed on the dielectric layer. 2. A titanium silicide layer is formed between the first conductive layer and the second conductive layer.
A semiconductor device having the capacitor according to item 1. 3. The semiconductor device having a capacitor according to claim 1, wherein said metal oxide is doped with an impurity for improving conductivity of said metal oxide. 4. An impurity region formed on a main surface of a semiconductor substrate, and a first region including silicon formed on the impurity region.
A second conductive layer formed on the first conductive layer and including an oxygen diffusion preventing material; and a second conductive layer formed on the second conductive layer and including a metal oxide. A third conductive layer, a lower electrode layer containing a platinum group element formed on the third conductive layer, a dielectric layer formed on the lower electrode layer, and a And a top electrode layer containing a platinum group element.