JPH1093080A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

[PROBLEMS] To provide a semiconductor device including a MOS transistor having a polycide gate electrode structure which does not cause deterioration in gate electrode breakdown voltage or change in threshold voltage V _TH even if the thickness of the polycide gate electrode is reduced, and a semiconductor device including the same. A manufacturing method is provided. SOLUTION: A first film having a thickness of about 50 nm is formed on a gate oxide film 13.
A-Si film 31, a TiN film 32 of about 30 nm and a second a-Si film 33 of about 50 nm are formed, and these are patterned to form a gate electrode portion 2; After forming the drain layer 19,
A Ti film is deposited, and a gate electrode portion 2 is formed by a two-step heat treatment.
The second a-Si film 33 is entirely silicided to form a low-resistance TiSi ₂ film 34 and, at the same time, a low-resistance TiSi ₂ film 35 is also formed on the surface of the source / drain layer 19. [Effect] A highly integrated semiconductor device can be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device characterized by a gate electrode structure of a MOS transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a conventional MOS type semiconductor device, a polycrystalline silicon film (polysilicon film) in which an impurity such as phosphorus is diffused has been used as a gate electrode material. However, in recent years, with the increase in speed and integration of MOS-type semiconductor devices, the resistance of the polysilicon film is large, so that the signal propagation speed becomes a problem, and it is difficult to achieve high-speed MOS-type semiconductor devices. It has become to. In addition, due to the demand for higher integration of MOS type semiconductor devices, the source / drain diffusion layers of miniaturized, short channel MOS type transistors are becoming increasingly thinner, and a shallow PN junction structure is required. This has become an impeding requirement for semiconductor devices aiming for high integration and high speed.

As one of means for solving the above problems, a polysilicon film of a polysilicon gate electrode, for which a technique for obtaining a good Si—SiO ₂ interface state has been established, and a method of reducing the resistance of the gate electrode, have been proposed. The gate electrode is a metal silicide film intended for the purpose, usually a polycide gate film using a composite film with a high melting point metal silicide film.
A MOS type semiconductor device having a source / drain portion structure in which a refractory metal silicide layer is also formed on a drain diffusion layer has been developed. As the refractory metal silicide, titanium silicide (TiSi ₂ ) having the smallest specific resistance is regarded as the most promising. The sheet resistance of the polysilicon gate electrode with a normal film thickness is about 30 Ω / □,
The sheet resistance of the source / drain diffusion layer of the N junction is 100
The sheet resistance is about Ω / □, but by forming a TiSi ₂ film on the gate electrode and the source / drain diffusion layers, the sheet resistance can be made 2 to 5 Ω / □.

The use of the TiSi ₂ film as described above makes it possible to reduce the sheet resistance of the gate electrode and the source / drain diffusion layers, but has the following problems.
The formation of a polycide gate electrode using a TiSi ₂ film as a refractory metal silicide film is performed by depositing a Ti film on a polysilicon film and performing a heat treatment to cause an alloy reaction between the polysilicon film and the Ti film. TiSi only on top of film
_In this alloy reaction, the diffusion of Ti along the crystal grain boundary proceeds faster than the diffusion of Ti in the polycrystal of the polycrystalline polysilicon film. In some portions, Ti reaches the gate oxide film and diffuses into the gate oxide film, causing a problem of deterioration of the gate electrode withstand voltage. Also, a TiSi ₂ film is formed in a considerable portion under the polycide gate electrode by the gate oxide film. When the state of contact with
Differences and work function phi _M and doped polysilicon film and TiSi ₂ film, the problem of changing the threshold voltage V _TH of the MOS transistor in the change of other Si-SiO ₂ interface states or generated.

[0005] Due to the diffusion of Ti along the above-mentioned crystal grain boundary, T reaches a gate oxide film in a part of the polysilicon film.
The gate electrode portion of a MOS transistor having a polycide gate electrode with an iSi ₂ film formed thereon is shown in FIG.
FIG. The polycide gate electrode by conventional TiSi ₂ film, the boundary surface between the polysilicon film and TiSi ₂ film, although there are some irregularities to the influence of the early diffusion along the grain boundaries of Ti, schematic planar boundary surfaces However, MOS transistors having a polycide gate electrode having an abnormally grown portion of a TiSi ₂ film up to the inside of the polysilicon film or reaching the gate oxide film as shown in FIG. It is common to do such an MO
The S transistor causes deterioration in breakdown voltage. On the other hand, at the time of alloying reaction, impurity ions doped in the polysilicon film, such as As, may diffuse into the TiSi ₂ film and cause a problem that the sheet resistance increases.

As a countermeasure against the above problem, a MOS having a gate electrode structure using a polycide film composed of a polycrystalline silicon film, a diffusion prevention film and a refractory metal silicide film is used.
A conventional example of a semiconductor device including a transistor and a method of manufacturing the same will be described with reference to FIGS. First, as shown in FIG. 4A, a LOCOS (Local Oxi) as a field oxide film is formed on a P-type semiconductor substrate 11.
(Dation of Silicon) film 12 is selectively formed. Thereafter, a gate oxide film 13 is formed in the MOS transistor unit 1 by using a thermal oxide film. And then
A first polysilicon film 14 doped with impurities is deposited to a thickness of about 150 nm.

Next, a SiO ₂ film or a CV
A diffusion prevention film 15 made of a CVD SiO ₂ film, a SiN film, or the like is formed by the D method. Since these diffusion prevention films 15 are insulating films, in order to secure conductivity between the first polysilicon film 14 and a second polysilicon film 16 described later,
A tunnel current is used as a thin film having a thickness of about 0.6 nm to 3 nm of the diffusion prevention film 15. Next, a second polysilicon film 16 doped with impurities is deposited to a thickness of about 150 nm.

Next, as shown in FIG. 4B, the second polysilicon film 16 / diffusion prevention film 15 / first polysilicon film 14 / gate oxide film 13 are patterned by using a photolithography technique. Then, the gate electrode part 2 is formed in the MOS transistor part 1. Then, the LDD (L
In order to form an (lightly doped drain) layer 18, low-dose ion implantation using As ions is performed on the source / drain portion 3 by an ion implantation method. Next, a CVD oxide film is deposited by a CVD method, and subsequently, RIE (Reactive Ion Etchin).
g) Etch back the CVD oxide film using an anisotropic etching method as described above to form a sidewall oxide film 17 on the side wall of the gate electrode portion 2. Then, in order to form a source / drain layer described later,
A high dose ion implantation using As ions is performed in the source / drain portion 3. Further, thereafter, a heat treatment is performed for activating and diffusing As ions implanted into the source / drain portions 3 to form the source / drain layers 19 having the LDD layers 18.

Next, as shown in FIG. 4C, a Ti film is deposited by a sputtering method, and thereafter, an RTA (Ra
A first heat treatment at a temperature of about 650 ° C. is performed in a nitrogen atmosphere by a pid thermal annealing method, and the surface of the second polysilicon film 16 of the gate electrode portion 2 where the Ti film is in contact with silicon and the source TiSi ₂ is deposited on the surface of the source / drain layer 19 of the drain portion 3.
The films 20 and 21 are formed. Next, the TiN film on the surface of the Ti film on the insulating film and the like, and the unreacted Ti film and the like formed by the RTA are removed with a mixed solution of sulfuric acid and hydrogen peroxide. Thereafter, a _second heat treatment at a temperature of about 800 ° C. is performed for the purpose of lowering the resistance of the TiSi ₂ films 20 and 21. The heat treatment of this twice, the gate electrode 2 and the source and drain portions 3, a self was aligned manner is silicided, so-called salicide (S elf- Ali gned S
ili cide) was of a low resistance TiSi ₂ film 2
0 and 21 are formed. Here, the TiSi ₂ films 20 and 21 formed by the first heat treatment at a temperature of about 650 ° C.
Is TiSi, which is said to be a low-temperature stable phase and a high-resistance C49 phase.
_{The two-} crystal TiSi ₂ films 20 and 21 formed by the second heat treatment at a temperature of about 800 ° C. are TiSi ₂ crystals called a C54 phase having a high-temperature stable phase and a low resistance.

Next, as shown in FIG. 5, BPSG (Bo
ro-Phospho Silicate Glass
s) and the like, and the surface of the interlayer insulating film 22 is deposited by a reflow method or a CMP (Chemical) method.
The surface is flattened by Mechanical Polishing or the like, and then the interlayer insulating film 22 is patterned to form an opening 23 of a contact hole in the source / drain portion 3 of the MOS transistor portion 1 or the like.

Next, a Ti film and a TiN film as a barrier film 24 are deposited by a sputtering method or the like.
A blanket W film 25 is deposited by the method, and thereafter, etch back is performed to form a tungsten plug 26 as a buried plug in the opening 23 of the contact hole.
Next, a TiN film 27 and an Al alloy film 28 containing Si are deposited and then patterned to form a wiring 29 connected to the tungsten plug 26 and the like. Thereafter, although not shown, a semiconductor device is manufactured by forming a passivation film, opening a pad window, and the like.

However, the above-described semiconductor device and the method of manufacturing the same have the following disadvantages.
Anti-diffusion film 1 inserted between the fourth polysilicon film 16 and the second polysilicon film 16
5 is a thickness of 0.6 to 3 such that a tunnel current flows.
It is extremely difficult to form a thin film having such a thin film that it is so homogeneous that a diffusion preventing effect can be reliably expected. Therefore, the thickness of the first polysilicon film 14 and the second polysilicon film 16 are each increased to about 150 nm as in this conventional example, and only the surface of the second polysilicon film 16 is made of TiSi _2. and film 20, to lower the probability of abnormal formation of the TiSi ₂ when TiSi ₂ film 20 is formed and the heterogeneity of (see FIG. 3) and the diffusion preventing film 15 overlap, the abnormal formation of the TiSi ₂ film 20 is the gate oxide By preventing the film 13 from reaching the film 13, the effect of preventing the gate electrode breakdown voltage from deteriorating is improved. For the above-mentioned reasons, the thickness of the gate electrode film becomes thick, and it becomes difficult to satisfy the demand for the size reduction in the vertical direction of the semiconductor substrate surface accompanying the miniaturization of elements due to the high integration of the semiconductor device. There is a problem that makes it difficult.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the semiconductor device and the method for manufacturing the same. That object of the present invention, a polycrystalline silicon film, by a polycide film composed of a diffusion preventing film and the metal silicide film, even by reducing the polycide gate electrode thickness, the gate electrode breakdown voltage and the threshold voltage V _TH It is an object of the present invention to provide a semiconductor device including a MOS transistor having a polycide gate electrode structure having no change in the resistance and a method of manufacturing the same.

[0014]

SUMMARY OF THE INVENTION A semiconductor device and a method of manufacturing the same according to the present invention are proposed to solve the above-mentioned problems. The semiconductor device according to the present invention comprises a polycrystalline silicon film, a diffusion prevention film and In a semiconductor device including a MOS transistor having a gate electrode structure formed of a metal silicide film, the diffusion prevention film is a refractory metal nitride film.

Further, a method of manufacturing a semiconductor device according to the present invention
In a method of manufacturing a semiconductor device including a MOS transistor having a gate electrode structure composed of a polycrystalline silicon film, a diffusion prevention film, and a metal silicide film,
Forming a first silicon film, forming a refractory metal nitride film as a diffusion preventing film on the first silicon film, and forming a second silicon film on the refractory metal nitride film And a second silicon film / a high melting point metal nitride film /
Patterning the first silicon film / gate oxide film,
A step of forming a gate electrode portion, a step of depositing a high melting point metal film, and a step of forming a silicide film by causing an alloying reaction between the second silicon film and the high melting point metal film of the gate electrode portion by heat treatment. It is characterized by having.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device including a MOS transistor having a gate electrode structure constituted by a polycrystalline silicon film, a diffusion preventing film and a metal silicide film. Forming a first silicon film on the first silicon film, depositing a high melting point metal nitride film as a diffusion preventing film on the first silicon film, and forming a second silicon film on the high melting point metal nitride film. Forming a film, patterning the second silicon film / high melting point metal nitride film / first silicon film / gate oxide film to form a gate electrode portion, and depositing a high melting point metal film Forming a silicide film by heat-treating the second silicon film of the gate electrode portion and the high-melting-point metal film in an alloying reaction, and silicidizing the entire second silicon film. The one in which the features.

According to the present invention, in a MOS transistor having a gate electrode structure composed of a polycrystalline silicon film, a diffusion prevention film, and a metal silicide film, the diffusion prevention film is made of a refractory metal film nitride film to prevent diffusion. Since the tunnel current is not used to secure the conductivity of the film, the thickness of the diffusion prevention film can be increased, and therefore, the diffusion of the refractory metal can be almost certainly prevented during the silicidation alloying reaction. For this reason, polycide gate electrode breakdown voltage degradation and threshold voltage V _TH
A MOS transistor having a polycide gate electrode structure with no change in the thickness can be manufactured. In addition, since the diffusion preventing film made of the refractory metal film nitride film can almost certainly prevent the refractory metal from diffusing, the thickness of the first and second silicon films can be reduced. The entire thickness of the electrode can be reduced, and a highly integrated semiconductor device can be manufactured in order to satisfy the demand for size reduction in the direction perpendicular to the surface of the semiconductor substrate accompanying the miniaturization of elements due to the high integration of the semiconductor device.

[0018]

Embodiments of the present invention will be described below with reference to the accompanying drawings. The same components as those in FIGS. 4 and 5 referred to in the description of the related art are denoted by the same reference numerals.

The present embodiment is an example in which the present invention is applied to a semiconductor device and a method of manufacturing the same, which will be described with reference to FIGS. First, as shown in FIG.
LOC as a field oxide film on the semiconductor substrate 11
The OS film 12 is selectively formed. Thereafter, a gate oxide film 13 having a thickness of about 20 nm is formed in the MOS transistor portion 1 by using a thermal oxide film. Next, a first silicon film,
For example, a first amorphous silicon film 3 doped with P
1 (hereinafter referred to as a first a-Si film 31) is a vertical LP
A film thickness of about 50 nm by a CVD method using a CVD apparatus or the like.
Deposits. The CVD conditions for the first a-Si film 31 are, for example, as follows. [CVD conditions of first a-Si film 31] SiH ₄ gas flow rate: 500 sccm PH ₃ gas flow rate: 0.35 sccm Gas pressure: 133 Pa Temperature: 530 ° C.

Next, a refractory metal nitride film as a diffusion preventing film, for example, a TiN film 32 is deposited to a thickness of about 30 nm by a sputtering method. This TiN film 32 is deposited
For example, using a magnetron sputtering apparatus, it is performed under the following reactive sputtering conditions. [Reactive sputtering conditions for TiN film 32] N ₂ gas flow rate: 100 sccm Gas pressure: 1 Pa Substrate temperature: 200 ° C. Supply power: 6 kW

Next, a second silicon film, for example, a second amorphous silicon film 33 doped with P (hereinafter referred to as a second amorphous silicon film 33).
A-Si film 33) is deposited to a thickness of about 50 nm by a CVD method using a vertical LPCVD apparatus or the like. The CVD apparatus and the CVD conditions for the second a-Si film 33 are, for example, the same as those for depositing the first a-Si film 31.

Next, as shown in FIG.
-Si film 33 / TiN film 32 / first a-Si film 31 /
The gate oxide film 13 is patterned by using the photolithography technique to form the gate electrode 2 of the MOS transistor 1. The etching at the time of forming the gate electrode portion 2 uses an ECR plasma etching apparatus, and the etching conditions are, for example, as follows. [Etching conditions at the time of forming the gate electrode portion 2] Cl ₂ gas flow rate: 100 sccm O ₂ gas flow rate: 100 sccm Gas pressure: 0.4 Pa Substrate temperature: 20 ° C. RF power in the first step: 80 W RF power: 30 W

Next, an LDD (Lightly) described later will be described.
In order to form a doped drain (Drain) layer, for example, As ions are used by ion implantation at an implantation energy of about 25 keV and a dose of about 5E13 / cm ² .
Ion implantation is performed on the source / drain portion 3.

Next, a film thickness of about 300 nm is formed by CVD.
Then, the CVD oxide film is etched back using an anisotropic plasma etching method such as RIE to form a sidewall oxide film 17 on the side wall of the gate electrode portion 2. Thereafter, a thermal oxide film (not shown) is formed on the surface of the source / drain portion 3 or the second a-
After a film thickness of about 10 nm is formed on the surface of the Si film 33, ion implantation for forming a source / drain layer described later is performed on the source / drain section 3 of the MOS transistor section 1 by an ion implantation method. This ion implantation is performed by, for example, A
Using s ions, the implantation energy is about 20 keV, and the dose is about 2E15 / cm ² . Incidentally, the implantation energy value, the projection range R _P is a second a-Si film 33
It is desirable to be on the surface side from the center.

Next, a heat treatment combining activation and diffusion of the implanted ions, for example, RTA (Rapid The
rmal Annealing) about 1000 °
A heat treatment is performed for about 30 seconds at C to form a source / drain layer 19 having an LDD layer 18. After that, the thermal oxide film on the surface of the second a-Si film 33 of the gate electrode portion 2 and the surface of the source / drain layer 19 of the source / drain portion 3 is removed with a diluted hydrofluoric acid solution. It should be noted that the first and second a-Si films 31, 33 are subjected to a heat treatment step such as the above-described thermal oxide film or activation.
Has been polycrystallized, and at this stage, has been changed to a polysilicon film.

Next, as shown in FIG. 1C, a refractory metal, for example, a Ti film is formed by sputtering to a thickness of about 40 nm.
Deposit about nm. Thereafter, a first heat treatment in a nitrogen gas atmosphere by an RTA method is performed at about 650 ° C. for about 30 seconds. By this heat treatment, the second a-S
The i film 33 and the silicon of the source / drain portion 3 cause an alloy reaction with the Ti film, and the Ti film reacts with the silicon of the silicon layer having a thickness of about 2.3 times the Ti film thickness, and has a thickness of about 2.5 times the Ti film thickness. A double TiSi ₂ film is formed. Therefore, when the Ti film of this embodiment has a thickness of about 40 nm, the source / drain portion 3 has a thickness of about 1 nm.
Since a TiSi ₂ film 35 having a thickness of 00 nm is formed and a TiN film 32 serving as a diffusion preventing film is provided in the gate electrode portion 2, the second a-Si film 3 which has become a polysilicon film is formed.
Only 3 silicon reacts with the Ti film and about 54 nm of Ti
An Si ₂ film 34 is formed. At this time, as the Ti film of the gate electrode portion 2, only the Ti film having a thickness of about 22 nm on the side of the second a-Si film 33 is used for forming the TiSi ₂ film 34, and the remaining Ti film is unreacted Ti film. Remains as a film. The TiSi ₂ films 34 and 35 formed here are TiSi ₂ crystals called a C49 phase having a low-temperature stable phase and a high resistance.

Next, the unreacted T of the gate electrode 2
i film and a TiN film formed on the surface of the unreacted Ti film, an unreacted Ti film on an insulating film such as the sidewall oxide film 17 and the LOCOS film 12, and a TiN film formed on the surface of the unreacted Ti film And sulfuric acid and aqueous hydrogen peroxide in a ratio of 3: 1
And removed with a selective etchant mixed at a ratio of afterwards,
A second heat treatment in a nitrogen gas atmosphere by the RTA method is performed at about 800 ° C. for about 30 seconds. By this heat treatment, TiSi ₂ TiSi ₂ films 34 and 35 is a TiSi ₂ crystals called C49 phase of high resistance at low temperature stable phase is a TiSi ₂ crystals called C54 phase of low resistance at a high temperature stable phase
The phase changes to the films 34 and 35. In this manner, a low-resistance Ti is formed in the gate electrode portion 2 and the source / drain portion 3 in a self-aligned manner as a silicide film, a so-called salicide film.
Si ₂ films 34 and 35 are formed.

Next, as shown in FIG. 2, an interlayer insulating film 22 is deposited by BPSG or the like, the surface of the interlayer insulating film 22 is flattened by a reflow method, CMP or the like, and then the interlayer insulating film 22 is patterned. Then, an opening 23 of a contact hole is formed in the source / drain portion 3 of the MOS transistor portion 1 and the like.

Next, a Ti film and a TiN film as the barrier film 24 are deposited by a sputtering method or the like.
A blanket W film 25 is deposited by the method, and thereafter, etch back is performed to form a tungsten plug 26 as a buried plug in the opening 23 of the contact hole.
Next, a TiN film 27 and an Al alloy film 28 containing Si are deposited and then patterned to form a wiring 29 connected to the tungsten plug 26 and the like. Thereafter, although not shown, a semiconductor device is manufactured by forming a passivation film, opening a pad window, and the like.

In the above-described embodiment of the present invention, the description has been made of the N-type MOS transistor having the polycide gate electrode. However, a P-type MOS transistor having the polycide gate electrode can be similarly manufactured. In addition, by combining the process of forming an N-type MOS transistor of a polycide gate electrode and the process of forming a P-type MOS transistor of a polycide gate electrode, a CMOS semiconductor device having a polycide gate electrode can be manufactured. Further, in the above-described embodiment, the second a
Although the Si film 33 is used, the second
When using a thick Ti film such that the entire a-Si film 33 is changed to the TiSi ₂ film 34, the second
A-Si film 33 may be used. Further, in the above-described embodiment, the polycide gate electrode has a structure in which the entirety of the _second a-Si film 33 doped with impurities is changed to a TiSi ₂ film 34. However, the polycide gate electrode is 2.3 times or more the thickness of the Ti film. Second in film thickness
A-Si film 33 is formed, and TiSi
The second a-Si film 33 may be left below the _second film 34.

In the above-described semiconductor device, the diffusion preventing film is made of TiN
The TiN film 32 is formed of a MOS transistor having a polycide gate electrode as the film 32. The thickness of the TiN film 32 is about 30 nm, which is at least one digit thicker than that of the conventional diffusion prevention film 15. The effect of preventing the diffusion of Ti into the first a-Si film 31 is large over the entire surface, and the first and second a-Si
Even if the films 31 and 33 are thin, it is possible to manufacture a semiconductor device without deterioration in gate electrode breakdown voltage or change in threshold voltage _VTH . Accordingly, the thickness of the polycide gate electrode of the MOS transistor can be made significantly smaller than that of the conventional polycide gate electrode, and a highly integrated semiconductor device can be manufactured.

The present invention has been described with reference to the embodiments.
The present invention is not limited to this embodiment. For example, in this embodiment, a TiN film is used as the diffusion prevention film, but a refractory metal nitride film such as a WN film or a MoN film may be used. Also, although the first and second silicon films have been described using amorphous silicon films doped with impurities,
A polysilicon film doped with impurities may be used. Others
Within the scope of the technical concept of the present invention, the process equipment and process conditions can be changed as appropriate.

[0033]

As is apparent from the above description, the semiconductor device of the present invention and the method of manufacturing the same are characterized in that the diffusion preventing film is made of Ti.
By using the N film, even with a thin polycide gate electrode, a MOS transistor having a polycide gate electrode without deterioration of the gate electrode withstand voltage and a change in the threshold voltage _VTH can be manufactured, and therefore, higher integration can be achieved. A semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device for explaining the first half of the steps of an embodiment to which the present invention is applied in the order of steps. FIG. 1 (a) shows a gate oxide film, a first a-Si film, and TiN on a semiconductor substrate. (B) shows a state in which a film and a second a-Si film are formed, (b) forms a gate electrode portion, forms a side wall oxide film,
A state in which a source / drain layer having a DD layer is formed,
(C) shows Ti in the gate electrode part and the source / drain part.
This is a state in which a Si ₂ film has been formed.

FIG. 2 is a schematic cross-sectional view of a semiconductor device for explaining the latter half of the steps of an embodiment to which the present invention is applied in the order of steps, in which an interlayer insulating film is formed, a tungsten plug is formed, and wiring is formed. .

FIG. 3 is a schematic cross-sectional view of a part of a MOS transistor portion for explaining a gate electrode breakdown voltage deterioration phenomenon in a conventional MOS transistor having a polycide gate electrode without a diffusion preventing film.

4A and 4B are schematic cross-sectional views of a semiconductor device, illustrating the first half of the steps of a conventional method of manufacturing a semiconductor device in the order of steps; FIG. 4A shows a gate oxide film, a first polysilicon film on a semiconductor substrate,
A state in which a diffusion prevention film and a second polysilicon film are formed, (b) a state in which a gate electrode portion is formed, a sidewall oxide film is formed, and a source / drain layer having an LDD layer is formed, (c). Is a state in which a TiSi ₂ film is formed on the gate electrode portion and the source / drain portions.

FIG. 5 is a schematic cross-sectional view of a semiconductor device, illustrating the latter half of the process of the conventional method of manufacturing a semiconductor device in the order of steps, in which an interlayer insulating film is formed, a tungsten plug is formed, and a wiring is formed. .

[Description of References] 1 ... MOS transistor section, 2 ... gate electrode section, 3 ... source / drain section, 11 ... semiconductor substrate, 12 ... LOCO
S film, 13 gate oxide film, 14 first polysilicon film, 15 diffusion prevention film, 16 second polysilicon film,
17 ... sidewall oxide film, 18 ... LDD layer, 19 ...
Source / drain layers, 20, 21,... TiSi ₂ film, 22
... interlayer insulating film, 23 ... opening, 24 ... barrier film, 25 ... blanket W film, 26 ... tungsten plug, 27 ... T
iN film, 28 ... Al alloy film, 29 ... wiring, 31 ... first a-Si film, 32 ... TiN film, 33 ... second a-Si
Film, 34, 35 ... TiSi ₂ film

Claims (10)

[Claims] 1. A semiconductor device including a MOS transistor having a gate electrode structure composed of a polycrystalline silicon film, a diffusion prevention film and a metal silicide film, wherein the diffusion prevention film is a refractory metal nitride film. Semiconductor device. 2. The semiconductor device according to claim 1, wherein said refractory metal nitride film is a TiN film. 3. A method of manufacturing a semiconductor device including a MOS transistor having a gate electrode structure constituted by a polycrystalline silicon film, a diffusion preventing film and a metal silicide film, wherein a first silicon film is formed on a gate oxide film. Forming a high melting point metal nitride film as the diffusion preventing film on the first silicon film; forming a second silicon film on the high melting point metal nitride film; Patterning a second silicon film / the refractory metal nitride film / the first silicon film / the gate oxide film to form a gate electrode portion; depositing a refractory metal film; Forming a silicide film by performing an alloying reaction between the second silicon film of the gate electrode portion and the high melting point metal film. 4. A method for manufacturing a semiconductor device including a MOS transistor having a gate electrode structure constituted by a polycrystalline silicon film, a diffusion preventing film and a metal silicide film, wherein a first silicon film is formed on a gate oxide film. A step of depositing a high melting point metal nitride film as the diffusion preventing film on the first silicon film; a step of forming a second silicon film on the high melting point metal nitride film; Patterning a second silicon film / the refractory metal nitride film / the first silicon film / the gate oxide film to form a gate electrode portion; depositing a refractory metal film; Forming a silicide film by causing an alloying reaction between the second silicon film of the gate electrode portion and the refractory metal film and silicidizing the second silicon film entirely. A method of manufacturing a semiconductor device. 5. The semiconductor device according to claim 3, wherein the first silicon film is one of a polysilicon film doped with an impurity and an amorphous silicon film doped with an impurity. The manufacturing method of the semiconductor device described in the above. 6. The method according to claim 3, wherein the refractory metal nitride film is a TiN film. 7. The semiconductor device according to claim 3, wherein said second silicon film is one of a polysilicon film doped with an impurity and an amorphous silicon film doped with an impurity. Manufacturing method. 8. The semiconductor device according to claim 4, wherein the second silicon film is one of a polysilicon film not doped with impurities and an amorphous silicon film not doped with impurities. The manufacturing method of the semiconductor device described in the above. 9. The method according to claim 3, wherein the refractory metal film is a Ti film. 10. When a Ti film is used as the refractory metal film, the thickness of the second silicon film is set to 2.3 times or less of the thickness of the Ti film, and the thickness of the second silicon film is reduced during an alloy reaction by heat treatment. wherein the second silicon film by any reaction to TiSi ₂ film, a manufacturing method of a semiconductor device according to claim 4.