JPH1093358A - Light receiving element circuit and light receiving element circuit array - Google Patents

Abstract

(57) [Problem] To provide a variable sensitivity photodetector circuit and its array capable of controlling the output polarity from a pixel, simplifying the structure, suppressing output variations, removing offsets from data, suppressing power consumption, and improving functions. The purpose is addition. SOLUTION: Light receiving element circuits 57 arranged on a horizontal line
Share the control line 78, and the light receiving element circuits 57 arranged on the vertical line share two current output lines 58 and 59, respectively. In each pixel, the potential of the photoelectric conversion element is converted into a current or the potential is stored in a memory capacitor, and lines 58 and 59 are selected and output for each row. The difference between the two outputs is calculated by a canceling circuit, thereby performing a vertical inter-pixel operation. Also this cancellation circuit 7
9 and 80 are arranged in each column, and there are also two output terminals 76 and 77 connected thereto. The two horizontal scanning circuits 74 and 75 select from which output terminal the output of each column is read out, and add the weighted outputs together to perform a horizontal pixel-to-pixel operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light-receiving element circuit comprising: a light-receiving element having a photoelectric conversion element; And a light receiving element circuit array in which a plurality of light receiving element circuits are arranged.

[0002]

2. Description of the Related Art FIG. 46 shows an example of a structure diagram of a conventional variable sensitivity light receiving element circuit described in Japanese Patent Application No. 7-75082, showing the structure of a unit pixel 1221. . In the figure, the output from the photoelectric conversion element 1203 is input to the gate terminal of the bias current MOS transistor 1204 of the differential amplifier. Differential amplifiers are current mirror MOS transistors 1218 and 1219, and positive output MOS transistor 121.
7, MOS transistor 1216 for negative output, MOS for bias current
A transistor 1204 is used. Also, 1202 is a reset switch MOS transistor, 1213 is ground, 121
4 is a power supply voltage, and 1220 is an output terminal.

Next, the operation will be described. When charge is accumulated in the photoelectric conversion element 1203 due to light incidence, it is used for bias current
The conductance of the MOS transistor 1204 changes. Here, if the MOS transistor 1216 is turned on, the output current of the MOS transistor 1204 is inverted by the mirror circuit, and then output (negative output) in a direction to draw the current from the output terminal 1220, and the MOS transistor 1217 is turned on. If this occurs, the output current of the MOS transistor 1204 will be
Output (positive output) in the direction of sweeping current from 0. Thus, the variable-sensitivity light-receiving element circuit can accumulate and amplify photocharges, and can also perform reading in both positive and negative polarities. In this case, the potential of the photoelectric conversion element decreases as the light intensity increases, and the potential is guided to the bias p-MOS transistor of the differential amplifier. Therefore, the absolute value of the output current increases as the light intensity increases. It can be.

FIG. 47 is a structural diagram of a conventional variable sensitivity light receiving element circuit in which a plurality of the conventional variable sensitivity light receiving element circuits of FIG. 46 are arranged in an array.
Reference numeral 1221 denotes a unit pixel formed by a variable-sensitivity light-receiving element circuit, and has a structure as shown in FIG. Reference numeral 1222 denotes a control circuit for controlling the operation of the variable sensitivity light receiving element circuit array by sending a signal to the control terminal of the unit pixel 1221, and a pixel reset terminal 1224 controls, for example, the reset switch 1202 in FIG. The negative output terminal 1225 controls, for example, the negative output MOS transistor 1216 in FIG. 46, and the positive output terminal 1226 controls, for example, the positive output MOS transistor 1217 in FIG. The switch terminals of the variable sensitivity light receiving element circuits 1221 arranged on one horizontal line share these control terminals 1224, 1225, and 1226, and one set is provided for each row, and the control terminals 1224, 1225, and 1226 are provided. Is assigned. An output circuit 1223 for extracting an output current from the unit pixel 1221 is connected to an output terminal 1220 in FIG. 46 through an output line 1227, for example. The output terminals of the variable sensitivity light receiving element circuits 1221 arranged on one line in the vertical direction share this output line 1227, and one output line 1227 is assigned to each column.

Since the conventional variable sensitivity light receiving element circuit array is constructed as described above, the variable sensitivity light receiving element circuits 1221 in each row have the same sensitivity and the same polarity, and the output currents are added in the vertical direction. Therefore, one-dimensional or two-dimensional light patterns can be simultaneously extracted in parallel and while performing a vertical inter-pixel operation.

FIG. 48 is a structural view of an array using a conventional variable sensitivity light receiving element circuit described in the specification of Japanese Patent Application No. 7-95223. The control circuit 1222 and the output circuit 12 shown in FIG.
23 specific structures are shown. 1228 is a sensor cell array whose unit pixel is the variable sensitivity light receiving element circuit of FIG.
1221. The control circuit 1229 has a structure in which one scanner is assigned to each of the three control terminals 1224, 1225, and 1226 in FIG. 47, and the output circuit multiplexes the current flowing from the output line 1227 of each column. The multiplexer 1230 has become.

Next, the operation will be described. First, when a pulse from the scanner r is applied to a certain row, the photoelectric conversion elements in the pixel cells in that row are reset to the initial potential. In order to read a normal image, the output current from each pixel is scanned in the horizontal direction by the multiplexer while applying a pulse from the scanner p to the row after a certain accumulation time. At this time, the sensor cell array 12 is
Given a pattern at 28, the pattern determines the polarity of the output current of each row, and the current output from each sensor cell is taken out while adding in the vertical direction and multiplexed, so the output from the multiplexer 1230 Is a result extracted while automatically performing the vertical inter-pixel operation. Thus, the function of extracting the irradiated light pattern while performing an inter-pixel operation can be realized with a simple circuit configuration.

The applicant has already proposed a light receiving element circuit 1212 using a tri-state switch, which is different from FIG. 46 as disclosed in Japanese Patent Application Laid-Open No. 8-56011. This circuit is shown in FIG. . This circuit can also be used as a single pixel in the sensor of FIG. 47 or FIG. In the figure, reference numeral 1201 denotes a bias terminal.

[0009]

Since the conventional variable sensitivity light receiving element circuit is constructed as described above, a line for driving the output switching transistor 1211 in the pixel is required in FIG. There was a problem that the structure became complicated. Further, since an n-MOS or a p-MOS is used for the output switching transistor 1211, there is a problem that a potential change due to the resistance of the output transistor 1211 cannot be ignored depending on the potential of the output terminal 1209.

In addition, since a single-stage differential amplifier is used as an output circuit of a pixel, when the characteristics of the transistor change due to manufacturing variations or temperature changes, the magnitude of the positive or negative output current is likely to shift. There was a problem.

In the above-described structure and operation, the stronger the light is, the lower the potential of the photoelectric conversion element is, and the more the potential is guided to the bias n-MOS transistor of the differential amplifier. For this reason,
The light has an offset output in the state of 0, and the output current decreases as the light becomes stronger, and an operation of removing the offset is required outside the chip in the calculation between pixels. Was. Further, as shown in FIG. 48, the p-MO
Even when S is used, the initial potential of the photoelectric conversion element 1203 is 121
4, the potential of the photoelectric conversion element 1203 becomes p
-There is a problem that no current flows until the voltage drops by the threshold voltage of the MOS transistor 1215, and there is no response in a place where light is weak.

Further, as shown in FIG.
If the reset bias power supply of the 1203 and the power supply for the readout circuit are shared, if the reset operation is performed in one pixel and the readout is performed in another pixel sharing the power supply line, the output current value The potential drop occurs in the power supply line, and there is a problem that the photoelectric conversion element 1203 does not completely rise to the power supply potential.

In the above-described pixel configuration, the transistor 12
While 06 and 1216 are on, there is a problem that power consumption increases because current continues to flow in the input stage of the mirror circuit even if the current flowing to the output terminal is set to 0. .

Further, in the above configuration, since there is no memory mechanism in a pixel, there is a problem that a time change of an image cannot be detected.

Further, in the above configuration, since the number of transistors in the pixel is large, it is difficult to reduce the area of the pixel.

Further, in the above-described configuration, a measure for stabilizing the potential of the photoelectric conversion element and a measure for when excessive light is applied to the photoelectric conversion element and photocharges are excessively generated are not taken into consideration. There was a point.

Further, since the conventional sensitivity-variable light receiving element circuit array is configured as described above, there is a problem that the calculation between pixels in the vertical direction can be performed but the calculation between pixels in the horizontal direction cannot be performed.

In the above-described sensitivity-variable light receiving element circuit array, resetting of pixels is simultaneously performed in one row by a pulse from the scanner r, while reading is performed in the horizontal direction while applying a pulse from the p or n scanner. Since scanning is performed by the multiplexer, there is a problem in that the accumulation time differs even for pixels in the same row by the time required for multiplexing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The light-receiving element circuit and the light-receiving element circuit array have a simplified pixel structure, improve the uniformity of characteristics between pixels, and improve reliability. It is an object of the present invention to reduce the deviation of positive and negative outputs, eliminate offsets from output data, suppress power consumption, and add functions.

[0020]

According to a first aspect of the present invention, there is provided a light receiving element circuit for absorbing light and extracting a photocurrent corresponding to a control voltage to the outside as a positive or negative output signal. A differential amplifier comprising a mirror circuit for controlling an output signal, the light receiving element circuit being provided in series with an element connected to a positive output terminal in the mirror circuit, and an output from the mirror circuit. And read control means controlled in synchronism with.

According to a second aspect of the present invention, there is provided a light receiving element circuit according to the first aspect, further comprising a second read control means in series with an element connected to a negative output terminal in the mirror circuit. is there.

According to a third aspect of the present invention, in the light receiving element circuit according to the first or second aspect, the differential amplifier includes a first mirror circuit having an n-MOS transistor having at least a source fixed to a substrate potential. , A multi-stage mirror circuit including second and third mirror circuits each having a p-MOS transistor whose source is fixed to the power supply potential.

According to a fourth aspect of the present invention, there is provided a light receiving element circuit for absorbing light and extracting a photocurrent corresponding to a control voltage to the outside as a positive or negative output signal, and a differential element for controlling the output signal. A light-receiving element circuit comprising a dynamic amplifier and reset means for setting the potential of the light-receiving element to the potential adjusted by the reset potential adjusting means.

According to a fifth aspect of the present invention, there is provided a light receiving element circuit according to any one of the first to fourth aspects, which absorbs light,
A light receiving element circuit comprising: a light receiving element for extracting a photocurrent according to a control voltage to the outside as a positive or negative output signal; and a differential amplifier for controlling the output signal, wherein the potential of the light receiving element is reset. It has means for adjusting the timing of the reset means.

According to a sixth aspect of the present invention, there is provided a light-receiving element circuit for absorbing light and extracting a photocurrent corresponding to a control voltage to the outside as a positive or negative output signal, and a control for controlling the output signal. A circuit for storing a potential generated in the light receiving element according to the amount of light absorption.

According to a seventh aspect of the present invention, there is provided a light receiving element circuit for absorbing light and extracting a photocurrent corresponding to a control voltage to the outside as a positive or negative output signal, and a control for controlling the output signal. And a circuit for transmitting a plurality of output signals to a plurality of output terminals controlled by an external control signal.

The light receiving element circuit according to claim 8 of the present invention is the light receiving element according to any one of claims 1 to 7, wherein:
It is surrounded by a diffusion region connected to the ground potential or the power supply potential.

According to a ninth aspect of the present invention, there is provided a light receiving element circuit according to any one of the first to seventh aspects, wherein:
It has a plurality of contact holes, and the contact holes are connected to each other.

According to a tenth aspect of the present invention, there is provided a light receiving element circuit according to any one of the first to seventh aspects, wherein the excess electron removing means accumulated in the light receiving element is provided in parallel with the resetting means for resetting the potential of the light receiving element. It is provided with.

A light-receiving element circuit according to claim 11 of the present invention is the power-supply potential connected to the reset means for resetting the potential of the light-receiving element and the power supply connected to the control circuit according to any one of claims 1 to 7. It is independent of the potential.

According to a twelfth aspect of the present invention, in the light receiving element circuit according to any one of the first to eleventh aspects, the control circuit is shielded by a metal film via an insulating film.

According to a thirteenth aspect of the present invention, there is provided a light receiving element circuit array, wherein the light receiving element circuits according to any one of the first to third aspects are arranged in a two-dimensional array and arranged in a horizontal direction. The connection terminal connected to the reset means, the positive output terminal, and the negative output terminal are shared for each row, connected to the vertical scanning difference circuit, and read out of the light receiving element circuits arranged in the vertical direction. The read control terminal connected to the control means is shared by one column and connected to a horizontal scanning circuit, and the output terminals of the light receiving element circuits arranged in the vertical direction are shared by one column, and the horizontal scanning circuit Connected to an array output terminal via a transmission gate controlled by the

According to a fourteenth aspect of the present invention, there is provided a light receiving element circuit array, wherein the light receiving element circuits according to the sixth aspect are arranged in a two-dimensional array and connected to reset means of each of the light receiving element circuits arranged in a horizontal direction. The connection terminal, the positive output terminal, the negative output terminal, and the memory control terminal connected to the means for storing the potential generated in the light receiving element are shared for each row by the vertical scanning difference circuit. The output terminals of the light receiving element circuits connected and arranged in the vertical direction are shared for each column, and connected to an array output terminal via a transmission gate controlled by a horizontal scanning circuit.

According to a fifteenth aspect of the present invention, there is provided a light receiving element circuit array, wherein the light receiving element circuits according to the seventh aspect are arranged in a two-dimensional array and connected to reset means of each of the light receiving element circuits arranged in a horizontal direction. The connection terminal, the positive output terminal, and the negative output terminal are shared for each row and connected to a vertical scanning difference circuit, and a plurality of output terminals of each of the light receiving element circuits arranged in the vertical direction are respectively connected. Each row is shared, and a plurality of output terminal lines composed of the shared output terminals are connected to the array output terminals via a canceling circuit controlled by a horizontal scanning circuit for each row.

According to a sixteenth aspect of the present invention, in the light-receiving element circuit array according to the fifteenth aspect, the light-receiving element circuit includes means for storing a potential generated in the light-receiving element in accordance with the amount of light absorption. A memory control terminal connected to a means for storing the generated potential is shared for each row and connected to a vertical scanning difference circuit.

According to a seventeenth aspect of the present invention, in the light receiving element circuit array according to the fifteenth or sixteenth aspect, the canceling circuit has a p-MOS transistor whose source is fixed to a power supply potential, and the light receiving element is arranged in a vertical direction. A mirror circuit which receives a plurality of output terminal lines of an element circuit and whose reading is controlled by a horizontal scanning circuit; and a transmission gate which is connected to an output side of the mirror circuit and is controlled by the horizontal scanning circuit. It is.

In the light-receiving element circuit array according to claim 18 of the present invention, in accordance with claim 15 or 16, the canceling circuit comprises: a first mirror circuit having an n-MOS transistor whose source is fixed to the substrate potential; A plurality of output terminal lines of a light receiving element circuit arranged in a vertical direction are constituted by a second mirror circuit and a third mirror circuit having p-MOS transistors whose sources are fixed to the power supply potential. A multi-stage mirror circuit controlled by the circuit,
A transmission gate connected to the output side of the mirror circuit and controlled by a horizontal scanning circuit.

According to a nineteenth aspect of the present invention, in the light receiving element circuit array according to the fifteenth or sixteenth aspect, the canceling circuit has an n-MOS transistor whose source is fixed to the substrate potential, and the light receiving element is arranged in the vertical direction. A mirror circuit which receives a plurality of output terminal lines of an element circuit and whose reading is controlled by a horizontal scanning circuit; and a transmission gate which is connected to an output side of the mirror circuit and is controlled by the horizontal scanning circuit. It is.

According to a twentieth aspect of the present invention, in accordance with the fifteenth or sixteenth aspect, a precharge line for pre-charging the light receiving element circuit is provided on the input side of the canceling circuit.

According to a twenty-first aspect of the present invention, in the light receiving element circuit array according to the twentieth aspect, a means for adjusting a timing of connection between a precharge line and a read is further provided.

The light receiving element circuit array according to claim 22 of the present invention is the light receiving element circuit array according to any one of claims 14 to 16, wherein a plurality of horizontal scanning circuits are arranged.

According to a twenty-third aspect of the present invention, in the light receiving element circuit array according to any one of the thirteenth to sixteenth aspects, a circuit for correcting the potential of the light receiving element whose output is connected to the array output terminal is provided.

According to a twenty-fourth aspect of the present invention, in the light receiving element circuit array according to the thirteenth to sixteenth aspects, a current-voltage conversion circuit is provided at an array output terminal.

According to a twenty-fifth aspect of the present invention, a light receiving element circuit array according to the twenty-fourth aspect further comprises a circuit for converting an analog voltage into a digital value.

According to a twenty-sixth aspect of the present invention, there is provided a light-receiving element circuit array according to any one of the thirteenth to sixteenth aspects, wherein the light-receiving element circuit array is surrounded by a diffusion region connected to a power supply potential or a ground potential. is there.

According to a twenty-seventh aspect of the present invention, in the light receiving element circuit array according to any one of the thirteenth to sixteenth aspects, the means for resetting the light receiving element of the light receiving element circuit is an n-MOS
The transistor controls the n-MOS transistor, and the potential of the pulse signal sent from the vertical scanning circuit is defined by the threshold voltage of the n-MOS transistor.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a light receiving element circuit of one pixel according to an embodiment of the present invention. In the figure, the output from the photoelectric conversion element 3 is for the bias current of the differential amplifier.
Input to the gate terminal of n-MOS transistor 4. The differential amplifier includes the n-MOS transistor 4 and a negative output terminal (V
n) a negative output n-MOS transistor 5 controlled by 14; a positive output n controlled by a positive output terminal (Vp) 15
A MOS transistor 6; p-MOS transistors 7 and 8 for a mirror circuit; and read control MOS transistors 9 and 10 controlled by a read control terminal (V0) 16. 1 is a power supply line, 2 is a reset MOS transistor of the photoelectric conversion element 3 controlled by a reset terminal (Vr) 13, 11 is a ground line, 12 is a substrate contact, and 17 is a pixel output terminal (Vout). Note that a portion surrounded by a dotted line is a unit of one pixel.

Next, the operation will be described. First, the operation when the read control MOS transistors 9 and 10 are not included will be described. First, the photoelectric conversion element 3 is reset to the power supply potential of the power supply line 1 through the MOS transistor 2. When charge is accumulated in the photoelectric conversion element 3 due to light incidence, the conductance of the n-MOS transistor 4 changes. Thereby, the output of the photoelectric conversion element is amplified, and S / N
The ratio can be improved. Where the negative output terminal
When there is an input from (Vn) 14, the output current from the n-MOS transistor 4 is output (negative output) in the direction of drawing current from the output terminal (Vout) 17, and is input from the positive output terminal (Vp) 15. Is present, the output current from the n-MOS transistor 4 is inverted by the mirror circuit, and then the output terminal (Vou
t) Output (positive output) in the direction of sweeping current from 17.

Thus, the variable-sensitivity light-receiving element circuit can accumulate and amplify photocharges, and can also read data in both positive and negative polarities.

Although a p-MOS is used as the reset MOS transistor 2 in the drawing, a switch such as an n-MOS may be used.

A p-MOS is used as the reset MOS transistor 2.
Is used, the photoelectric conversion element 3 can be reset to the power supply potential of 1 without making the voltage pulse applied from the reset terminal (Vr) 13 higher than the potential of the power supply line 1.

Here, a read control MOS transistor 9 is inserted between the n-MOS transistor 4 and the input side transistor 7 of the mirror circuit in series with the positive output n-MOS transistor 6, and is connected to an output terminal. Control according to access to 17. Then, even when there is an input from the positive output terminal 15, no current flows to the input side of the mirror circuit except when a current is output from the output terminal 17, so that power consumption can be reduced.

Further, a read control MOS transistor 10 is inserted between the n-MOS transistor 4 and the output terminal 17 thereof in series with the n-MOS transistor 5 for negative output, and this is used to access the output terminal 17. Control according to. Then, both the positive and negative output circuits include three n-MOS transistors, and the symmetry of the circuit is improved, so that it is easy to make the magnitudes of the positive and negative output currents equal.

In the figure, the n-MOS is used as the read control MOS transistors 9 and 10, but the same effect can be obtained by using the p-MOS.

Also, in the figure, the read control MOS transistors 9 and 10 are inserted on the side closer to the mirror circuit than the output n-MOS transistors 5 and 6, but are inverted upside down as shown in FIG. The same effect can be obtained with a structure.

Embodiment 2 Hereinafter, another embodiment of the present invention will be described with reference to the drawings. In the first embodiment,
Although the two read control MOS transistors 9 and 10 were inserted into the positive and negative read circuits, one transistor 9a was inserted in series adjacent to the n-MOS transistor 4 as shown in FIG. It goes without saying that even if this is controlled, the same effect can be obtained.

In FIG. 3, the components corresponding to those in FIG. 1 are denoted by the same reference numerals.

Embodiment 3 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a diagram showing a configuration of a light receiving element circuit according to one embodiment of the present invention. In the figure, reference numerals 1 to 6 and 9 to 17 are the same as those in FIG. The differential amplifier according to the present embodiment includes a bias current n-MOS transistor 4, a negative output n-MOS transistor 5, and a positive output n-MOS transistor.
The transistor 6 and the n-MOS transistor 1 forming the first mirror circuit whose output side is connected to the output terminal 17 of the pixel
8, 19, p-MOS transistors 20 and 21 forming a second mirror circuit whose output side is connected to the output terminal 17 of the pixel, and a third mirror whose output side is connected to the input side of the first mirror circuit The circuit includes p-MOS transistors 22 and 23 and read control MOS transistors 9 and 10.

Reset operation of photoelectric conversion element 3 and n-MO
The amplification of the output by the S transistor 4 is the same as in the first embodiment. First, an output operation when the read control MOS transistors 9 and 10 are not included will be described.

When there is an input from the negative output terminal 14, the n-MOS
The output current from the transistor 4 first flows to the input side p-MOS transistor 22 of the third mirror circuit. The current from the corresponding output side p-MOS transistor 23 flows to the input side n-MOS transistor 18 of the first mirror circuit, and the output current is supplied from the output terminal 17 by the corresponding output side n-MOS transistor 19. Output (negative output) in the pull-in direction.
On the other hand, when there is an input from the positive output terminal 15, the output current from the n-MOS transistor 4 is applied to the input side p− of the second mirror circuit.
The output current flows through the MOS transistor 20 and is output (positive output) by the output side p-MOS transistor 21 in a direction to sweep out the current from the output terminal 17.

As described above, the variable-sensitivity light-receiving element circuit can accumulate and amplify photocharges, and can also read data in both positive and negative polarities.

Further, by stacking the mirror circuits in multiple stages as described above, when the characteristics of the transistor change due to manufacturing variations or temperature changes, the magnitude of the positive and negative output currents hardly shifts.

Further, in the above embodiment, the case where three mirror circuits are used has been described. However, it is needless to say that the same effect can be obtained when the mirror circuits are further stacked.

Here, between the n-MOS transistor 4 and the input-side transistor 20 of the second mirror circuit, the positive output n-
A read control MOS transistor 9 is inserted in series with the MOS transistor 6, and a negative output MOS transistor 9 is connected between the n-MOS transistor 4 and the input transistor 22 of the third mirror circuit.
A read control MOS transistor 10 is inserted in series with the n-MOS transistor 5 to control the MOS transistors 9 and 10 in accordance with access to the output terminal 17. Then, even when there is an input from the positive and negative output terminals 15 and 14, no current flows to the input side of the mirror circuit except when a current flows from the output terminal, so that power consumption can be reduced.

In the figure, although the n-MOS is used as the read control MOS transistors 9 and 10, the same effect can be obtained by using the p-MOS.

In the figure, the read control MOS transistors 9 and 10 are inserted on the side closer to the mirror circuit than the output n-MOS transistors 5 and 6. Even in this case, the same effect is obtained.

Further, instead of inserting the two read control MOS transistors 9 and 10 into the positive and negative read circuits, one transistor 9b is inserted in series above or below the n-MOS transistor 4 as shown in FIG. However, it is needless to say that the same effect can be obtained even if this is controlled by the read control terminal 16.

Embodiment 4 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a diagram showing a configuration of a light receiving element circuit according to one embodiment of the present invention. In the figure, reference numerals 1-3, 9-13, 16, and 17 are the same as those in FIG.
In the present embodiment, the output from the photoelectric conversion element 3 is input to the gate terminal of the bias current p-MOS transistor 24 of the differential amplifier. The differential amplifier uses this p-MOS transistor 2
4, p-MOS transistor 25 for negative output controlled by terminal 29 for negative output, p-MOS transistor 26 for positive output controlled by terminal 30 for positive output, n-MOS transistors 27 and 28 for mirror circuit, read Control MOS transistors 9 and 10 are provided. Reference numeral 31 denotes a diode-connected p-MOS transistor for adjusting the reset potential of the photoelectric conversion element 3.

First, the read control MOS transistors 9 and 10 and the reset potential adjustment p-MOS transistor 3
The output operation when 1 is not included will be described.

The reset operation of photoelectric conversion element 3 is the same as in the first embodiment. When charge is accumulated in the photoelectric conversion element 3 due to light incidence, the conductance of the p-MOS transistor 24 changes. Here, when there is an input from the negative output terminal (Vn) 29, the output current from the p-MOS transistor 24 is inverted (negative output) in a direction to draw the current from the output terminal 17 after being inverted by the mirror circuit, Positive output terminal (V
When there is an input from p) 30, the output current from the p-MOS transistor 24 is output (positive output) in a direction to sweep out the current from the output terminal 17.

With the above operation, the variable sensitivity light receiving element circuit can accumulate and amplify photocharges, and can also read data in both positive and negative polarities.

Here, as the photoelectric conversion element 3, it is assumed that an element having a lower potential as light intensity is higher, such as an n-source drain in a p-well fixed at a substrate potential, is used. In the first to third embodiments, the output current is controlled by the n-MOS transistor 4 whose gate receives the potential of the photoelectric conversion element 3. FIG. 8 shows the relationship between the output current and the light irradiation time (light accumulation time). As you can see from the figure,
The output current has an offset value in a reset state, and the light is strong. The longer the accumulation time is, the lower the output current becomes. Therefore, at the time of reading, it is necessary to store this offset value externally and perform an operation of obtaining a difference from the output current value. This means that the image deteriorates when the offset value shifts due to a temperature change or the like, or that the offset value changes when the current is added between pixels and taken out.

On the other hand, in the present embodiment, the potential of the photoelectric conversion element 3 is input to the p-MOS transistor 24,
When the output current is controlled in this manner, the output current value is 0 in the reset state, and the output becomes positive as the light becomes stronger and the accumulation time becomes longer, resulting in positive reading. Therefore, the operation of removing the offset is not required at the time of reading.

On the other hand, in this configuration, when the photoelectric conversion element 3 is first reset to the power supply potential and a change in the potential therefrom is to be monitored by the output current value of the p-MOS transistor 24, the potential of the photoelectric conversion element 3 The output current does not change from 0 until the voltage falls below the power supply potential by the threshold voltage of the p-MOS transistor 24, that is, if the light is weak and the accumulation time is not long enough, There is a concern that there is no signal.

Therefore, in the present embodiment, a diode-connected p-type transistor is connected in series with the reset MOS transistor 2.
-The MOS transistor 31 was inserted. As a result, the potential of the photoelectric conversion element 3 is reset only to a potential lower than the power supply potential by the threshold voltage of the p-MOS transistor 31, so that an output signal can be output even when the light is weak. FIG. 9 shows the relationship between the amount of light and the output current due to such a difference in structure. It can be seen that when the p-MOS transistor 31 is inserted, an output current can be obtained even with a small amount of light.

Further, the gate length of the p-MOS transistor 31
If the gate width is made the same as that of the p-MOS transistor 24, the threshold voltage can be made completely the same. Therefore, in FIG. They can be matched, and the accuracy of the light receiving element circuit is improved.

Further, in the configuration of the present embodiment, even if the threshold value of the p-MOS transistor 24 varies within the chip, the variation is compensated for by the reset potential of the photoelectric conversion element 3, so that the fixed pattern noise Reduction can be achieved.

In FIG. 7, the p-MOS transistor 31 is arranged closer to the power supply than the reset MOS transistor 2. However, even if the structure as shown in FIG. It goes without saying that it works.

Here, as shown in FIG. 7, the p-MOS transistor 2
The read control MOS is connected in series with the p-MOS transistor 25 for negative output between
The transistor 10 is inserted and is controlled according to the access to the output terminal 17. Then, even when there is an input from the negative output terminal 29, no current flows to the input side of the mirror circuit except when a current flows from the output terminal, so that power consumption can be reduced.

Further, a read control MOS transistor 9 is inserted between the p-MOS transistor 24 and its output terminal 17 in series with the positive output p-MOS transistor 26, and this is used to access the output terminal 17. Control according to. Then, since the symmetry of the positive and negative output circuits is improved, it is easy to make the magnitudes of the positive and negative output currents equal.

In FIG. 7, although the n-MOS is used as the read control MOS transistors 9 and 10, the same effect can be obtained by using the p-MOS.

In FIG. 7, the read control MOS transistors 9 and 10 are inserted closer to the mirror circuit than the output p-MOS transistors 26 and 25.
The same effect can be obtained even if it is turned upside down as described above.

Further, instead of inserting two read control MOS transistors 9 and 10 into the positive and negative read circuits, one transistor 9a is inserted in series above or below the p-MOS transistor 24 as shown in FIG. It goes without saying that the same effect can be obtained even if this is controlled by the read control terminal 16.

Also in this structure, the mirror circuits are stacked in multiple stages as in the third embodiment, so that when the characteristics of the transistor change due to manufacturing variations or temperature changes, the magnitude of the positive or negative output current can be reduced. It is possible to make the displacement hard to occur.

Embodiment 5 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a diagram showing a configuration of a light receiving element circuit array according to one embodiment of the present invention. In the figure, reference numeral 32 denotes a unit pixel of the light receiving element circuit described in the first to fourth embodiments. Vr in the unit pixel is a reset terminal 13, Vn is a negative output terminal 14 or 29, Vp is a positive output terminal 15 or 30, and Vo is a read control terminal 1.
6, OUT indicates an output terminal 17 of the pixel. Reference numeral 33 denotes a vertical scanning circuit for controlling the operation of the variable sensitivity light receiving element circuit array by sending a signal to the control terminal of the unit pixel 32. The reset line 35 of the pixel has Vr, and the negative output line 36 has V
n and the positive output line 37 controls Vp. The control terminals of the variable sensitivity light-receiving element circuits 32 arranged on one horizontal line share these control lines 35, 36, and 37, and one set of control lines 35, 36, and 37 is provided for each row. Assigned. The output terminals 17 of the variable sensitivity light receiving element circuits 32 arranged on one vertical line share an output line 38, and one output line 38 is assigned to each column. Numeral 34 denotes a horizontal scanning circuit for extracting an output current from the unit pixel 32, a read control line 39 controls Vo, and an output line 38 controls a transmission gate 40 controlled by the read control line 39. Through the output terminal 41 of the array. Note that a vertical scanning circuit,
As the horizontal scanning circuit, one or a plurality of scanners constituted by a shift register or the like, a random logic circuit, or the like may be used.

Next, the operation will be described. First, when the reset line 35 in a certain row is activated by the vertical scanning circuit 33, the photoelectric conversion elements 3 in the pixel cells 32 in that row are reset to the initial potential. To read a positive image, after a certain accumulation time, while the vertical scanning circuit 33 activates the positive output line 37 of that row, the horizontal scanning circuit 34 activates the read control line 39 by scanning, and the transmission gate 40 outputs the output current from each row to the output terminal 41 of the array. Similarly, the negative image may be read by activating the negative output line 36. At this time, when a pattern is applied to the negative output line 36 and the positive output line 37 of each row, the polarity of the output current of each row is determined by the pattern, and each pixel cell 32
The current output from the array is extracted while being added in the vertical direction, so that the output from the output terminal 41 of the array is a result obtained by automatically performing the operation between pixels in the vertical direction.

Here, a read control terminal Vo is applied to each pixel.
Controls the input and output of the mirror circuit in the pixel, so that current does not flow to the input side of the mirror circuit by the read control line 39 except when the transmission gate 40 is open in each column. Can be reduced.

As a result, the irradiated one-dimensional or two-dimensional light pattern can be taken out simultaneously, in parallel, and while performing the calculation between pixels in the vertical direction.

Further, since the transmission gate 40 is used for selecting a column to be output, the voltage drop at this output switch can be suppressed to a small value regardless of the potential of the output terminal 41.

The transmission gate is an n-MO
There is no difference in basic functions between S and p-MOS. In particular, when the output terminal potential is low, only the n-MOS is used, and when the output terminal potential is high, the p-MOS alone is used to sufficiently reduce the on-resistance.

Embodiment 6 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 14 is a block diagram of a light receiving element circuit showing an embodiment of the present invention. 1 to 3 and 12, 13, and 17 in the figure are the same as those in FIG. The potential of the photoelectric conversion element 3 is connected to the current output terminal 17 through a first circuit 49 for converting the potential into a current, which is controlled by a first output control terminal 45, and at the same time, a memory control terminal 52
Is connected to the capacitor 50 through a connection circuit 51 controlled by Further, the capacitor 50 is connected to the current output terminal 17 through a second circuit 53 for converting a potential into a current, which is controlled by a second output control terminal 46. Where circuit 53 or circuit
Either 49 includes a current reversing circuit so that the direction of the output current is reversed. The capacity of the capacitor 50 is sufficiently smaller than the capacity of the photoelectric conversion element 3.

FIG. 15 shows the circuit of FIG. 14 arranged in an array as shown in FIG. 33-38 and 40 in the figure,
41 is the same as FIG. Reference numeral 55 denotes a memory control line, 54 denotes a unit pixel formed by a variable sensitivity light receiving element circuit surrounded by a dotted line in FIG. 14, Vr denotes a reset terminal 13, and Vn denotes a second output control terminal 46 (or a first output control terminal 46). Terminal 45), Vp
Is the first output control terminal 45 (or the second output control terminal 4
6), Vm is the memory control terminal 52, OUT is the pixel output terminal 1
7 is shown. As in FIG. 13, the control terminals of the variable sensitivity light receiving element circuits 54 arranged on one horizontal line are the control lines 35, 36, 37, 55, and the variable sensitivity light receiving elements arranged on one vertical line. The output terminal 17 of the circuit 54 shares the output line 38.

Next, the time differentiation operation using this circuit will be described. The reset operation of the photoelectric conversion element 3 is the same as in the fifth embodiment. When charge is accumulated in the photoelectric conversion element 3 due to the incidence of light, the potential of the photoelectric conversion element 3 decreases accordingly. This potential is supplied to the circuit 49 by access from Vp.
After the data is read out through the connection circuit 51, the data is stored in the capacitor 50 through the connection circuit 51 by access from Vm before the reset operation. Next, after the reset and accumulation operations are performed, when Vp and Vn are simultaneously activated, the output terminal 17 corresponds to the difference between the potential of the previous frame stored in the capacitor 50 and the potential of the photoelectric conversion element 3. A current will be output.

Thus, it is possible to output a temporal change of the light amount between frames.

Next, an output operation (similar to the circuit according to the first to fourth embodiments) using this circuit will be described. When the memory control terminal 52 is always active, this circuit converts the potential of the photoelectric conversion element 3 into a current and connects it to the output terminal 17. This is equivalent to being configured by a circuit 53 that converts the current into a reverse direction and connects to the output terminal 17.
Therefore, the output operation is the same as that of the first to fourth embodiments.

Next, the operation of removing fixed pattern noise using this circuit will be described. The reset operation of the photoelectric conversion element 3 is the same as in the fifth embodiment. When charge is accumulated in the photoelectric conversion element 3 due to the incidence of light, the potential of the photoelectric conversion element 3 decreases accordingly. First, this potential is stored in the capacitor 50 through the connection circuit 51 by access from Vm, and then Vr, Vp, and Vn are simultaneously activated.
From the output terminal 17, the photoelectric conversion element 3 stored in the capacitor 50 is output.
And a current corresponding to the difference between the reset potential and the reset potential.

According to this operation, the accumulation time of each pixel is
Since the time is from resetting the photoelectric conversion elements 3 included in each row with Vr to accessing Vm, the accumulation times can be completely matched in the row.

Further, even if the reset potential of the photoelectric conversion element 3 varies within the array, the output signal value is a change in the potential of the photoelectric conversion element 3. Has the same effect.

As a result, output with less fixed pattern noise is possible.

Next, an electronic shutter operation using this circuit will be described. The reset operation of the photoelectric conversion element 3 is the same as in the fifth embodiment. When charge is accumulated in the photoelectric conversion element 3 due to the incidence of light, the potential of the photoelectric conversion element 3 decreases accordingly. When this potential is first stored in the capacitor 50 through the connection circuit 51 by access from Vm, and then the second output control terminal 46 is activated by access from Vn, the photoelectric conversion element 3 is output from the output terminal 17. Is output.

If the reset operation by the reset terminal 13 and the transfer of the potential of the photoelectric conversion element to the capacitor 50 by the memory terminal 52 are simultaneously performed for all the pixels in the array, the accumulation time of all the pixels is equal. The image at the time of accessing the memory terminal 52 is read from this array.

As a result, an operation like an electronic shutter can be performed.

Embodiment 7 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 16 is a diagram showing a configuration of a light receiving element circuit according to one embodiment of the present invention. In the figure, 1 to 3 and 12, 13 are the same as in FIG. Here, instead of providing the structure of the differential amplifier in the pixel 57, the potential of the photoelectric conversion element 3 is input to the circuit 42 for converting the potential into a current, and the output current is supplied to the first output control terminal 45. A first output terminal 47 through a controlled first output circuit 43
And output to a second output terminal 48 through a second output circuit 44 controlled by a second output control terminal 46.

FIG. 17 shows a specific example of this circuit configuration.
It is. A circuit 42 for converting the potential of FIG.
The MOS transistor 4 is used, and the output current is negative output MOS
The signal is output to a first output terminal 47 and a second output terminal 48 via the transistor 5 and the positive output MOS transistor 6. That is, the first output circuit 43 and the second output circuit 44 in FIG.
And the positive output MOS transistor 6.

By adopting such a structure, FIG.
Circuit for converting the potential of the current into a current, a first output circuit
43, the second output circuit 44 can be realized by a simple circuit configuration of three n-MOS transistors 4, 5, and 6.

Further, the same effects as in the first embodiment can be realized by a simple circuit. Further, it is not necessary to supply a power supply for the readout circuit in the pixel, and the power supply line for the output current and the power supply line 1 for resetting the photoelectric conversion element 3 can be completely separated, so that the reliability is improved. I can do it.

The reset MOS transistor 2 has n
When -MOS is used, the entire pixel can be constituted by n-MOS transistors, so that the pixel structure can be simplified and the pixel area can be reduced.

Embodiment 8 FIG. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. In the above-described embodiment, the structure shown in FIG. 17 is shown as an example of the specific configuration in FIG. 16, but a structure as shown in FIG. 18 may be used as another example. In FIG. 18, 1 to 3 and 11 to 13, 24 to 26, and 29 to 31 are the same as those in FIG. Here, in the structure of FIG. 7, instead of providing the structure of the differential amplifier in the pixel, the output current from the p-MOS transistor 24 is changed to the negative output MOS transistor 2.
The signal is output to the first output terminal 47 and the second output terminal 48 via the transistor 5 and the positive output transistor 26.

By adopting such a structure, FIG.
Circuit for converting the potential of the current into a current, a first output circuit
43, the second output circuit 44, three p-MOS transistors 2
It can be realized by a simple circuit configuration of 4, 25, 26.

Further, the same effects as in the fourth embodiment can be realized by a simple circuit.

Embodiment 9 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 19 shows Embodiment 7,
This shows a configuration of a light receiving element circuit array in which eight pixels 57 are arranged in an array. In the figure, reference numerals 33 to 37 and 41 are the same as those in FIG. Reference numeral 57 denotes a unit pixel formed by the variable sensitivity light receiving element circuit shown in FIG. 17, and OUT1 and OUT2 indicate two output terminals 47 and 48 of the pixel. As in FIG. 13, the control terminals of the variable sensitivity light receiving element circuits 54 arranged on one horizontal line are control lines 35, 36, and 37, and the variable sensitivity light receiving element circuits 57 arranged on one vertical line. Output terminals 47, 48 share respective output lines 58, 59. Reference numeral 60 denotes a MOS transistor circuit having two input terminals, connected to the output terminal 41 via the transmission gate without changing the direction of the input current from one input terminal, and the input current from the other input terminal. And connect it to the output terminal 41 via the transmission gate.
This is a canceling readout circuit constituted by a MOS transistor circuit and is controlled by the horizontal scanning circuit 34.

As described above, by providing the output current inverting circuit outside the pixel, the structure of the pixel is simplified and the pixel area is reduced while maintaining the function of the variable sensitivity light receiving element array of FIG. It becomes possible.

The power supply for resetting the photoelectric conversion element is a pixel.
Since the power is supplied only to the array unit 57 and the power for the output current is supplied only to the canceling readout circuit 60, the two types of power can be completely separated, and the reliability can be improved.

Embodiment 10 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 20 is a diagram showing a configuration of a light receiving element circuit 57a according to one embodiment of the present invention.
In the figures, 1-3 and 12, 13 are those of FIG. 1, and 45-48 are those of FIG.
6 and 49 to 52 are the same as those in FIG. The electric potential of the photoelectric conversion element 3 is controlled by a first output control terminal 45, and is supplied to a current output terminal through a first circuit 49 that converts the electric potential to a current.
At the same time as being connected to 47, it is connected to a capacitor 50 through a connection circuit 51 controlled by a memory control terminal 52. Further, the capacitor 50 is connected to the current output terminal 48 through a second circuit 56 for converting a potential into a current, which is controlled by a second output control terminal 46. Here, either the circuit 56 or the circuit 49 includes a current inverting circuit so that the direction of the output current is reversed. The capacity of the capacitor 50 is sufficiently smaller than the capacity of the photoelectric conversion element 3. FIG.
The difference from 6 is that two current output terminals 47 and 48 are provided, and neither the second circuit 56 nor the first circuit 49 for converting the potential of the capacitor 50 into a current includes a current inverting circuit. .

Next, a specific example of the circuit configuration of FIG. 20 is shown in FIG. Here, in the structure of FIG.
The circuit 49 is constituted by an n-MOS transistor 61, and the circuit 49 is an n-MOS transistor 62 in which the potential of the photoelectric conversion element 3 is led to the gate.
And an n-MOS transistor 63 configured by a first output transistor 64 controlled by the output control terminal 45 to guide the circuit 56 to the gate of the potential of the capacitor 50, and an output control terminal 4
It comprises a second output transistor 65 controlled by 6. With such a structure, the structure in FIG. 20 can be realized with a simple circuit configuration.

By providing the output current inverting circuit outside the pixel in this way, the structure of the pixel can be simplified and the pixel area can be reduced.

Further, it is not necessary to supply power for the readout circuit to the pixel, and the power supply line for the output current and the power supply line 1 for resetting the photoelectric conversion element 3 can be completely separated, so that the reliability is improved. Can be enhanced.

Although a p-MOS is used as the reset MOS transistor 2 in the figure, a switch such as an n-MOS may be used.

The same effects as in the sixth embodiment can be realized by a simple circuit.

Embodiment 11 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 22 shows a configuration of a light receiving element circuit array in which the pixels 57a of the tenth embodiment are arranged in an array. In the figure, reference numerals 33 to 37 and 41 and 55 are the same as those in FIG. Reference numeral 57 denotes a unit pixel formed by the variable sensitivity light receiving element circuit shown in FIG. 17, and OUT1 and OUT2 indicate two output terminals 47 and 48 of the pixel. As in FIG. 13, the control terminals of the variable sensitivity light receiving element circuits 54 arranged on one horizontal line are the control lines 35, 36, 37, 55, and the variable sensitivity light receiving elements arranged on one vertical line. Output terminals 47 and 48 of circuit 57a share respective output lines 58 and 59. The MOS transistor circuit 60 has two input terminals and is connected to the output terminal 41 via the transmission gate without changing the direction of the input current from one input terminal, and the input current from the other input terminal. And a MOS transistor circuit connected to the output terminal 41 via the transmission gate described above, and is controlled by the horizontal scanning circuit 34.

Further, as shown in FIG. 15 of the sixth embodiment, a memory control terminal 52 connected to a control line 55 is provided. Can be output over time.

By providing the output current inverting circuit outside the pixel in this manner, the structure of the pixel is simplified and the pixel area is reduced while maintaining the function of the variable sensitivity light receiving element array shown in FIG. It becomes possible.

The power supply for resetting the photoelectric conversion element is a pixel.
Since the power for the output current is supplied only to the array portion 57a and the power for the output current is supplied only to the canceling readout circuit 60, the two types of power can be completely separated, and the reliability can be improved.

Embodiment 12 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 23 shows a specific example of a circuit configuration used for the canceling circuit 60 in FIG. 19 of the ninth embodiment and FIG. 22 of the eleventh embodiment. In the figure, 1 and 7 to 10 are the same as in FIG. 66 is an input terminal for negative output, 67 is an input terminal for positive output.
9 and 22 are connected to output lines 58 and 59. Reference numeral 68 denotes a transmission gate, and 69 denotes an output terminal of FIGS.
Output terminal of the cancellation circuit connected to 41. Also,
The read control terminal 16a corresponds to 16 in FIG.
Connected to horizontal scanning circuit 34.

A read control MOS is provided between the positive output input terminal 67 and the input transistor 7 of the mirror circuit.
When the transistor 9 is inserted and controlled according to the access to the transmission gate 68, the output terminal 69
Since no current flows to the input side of the mirror circuit except when a current flows from the mirror circuit, power consumption can be reduced.

Further, when the read control MOS transistor 10 is inserted between the negative output input terminal 66 and the transmission gate 68 and is controlled in accordance with the access to the transmission gate 68, the symmetry of the positive and negative output circuits is obtained. Therefore, it is easy to make the magnitudes of the positive and negative output currents equal.

Further, in the figure, n-MOS is used as the read control MOS transistors 9 and 10, but the same effect can be obtained by using p-MOS.

Embodiment 13 FIG. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 24 shows another specific example of the circuit configuration used for the canceling circuit 60 in FIG. 19 of the ninth embodiment and FIG. 22 of the eleventh embodiment.
In the figure, 1 and 7 to 10 and 18 to 23 are the same as those in FIG. Also, 16a and 66 to 69 are the same as those in FIG.

By having a structure in which the mirror circuit shown in FIG. 22 has multiple stages, the canceling readout circuit 60 can be realized with a simple circuit configuration. Also, by stacking mirror circuits in multiple stages in this way, when the characteristics of the transistor change due to manufacturing variations or temperature changes,
The positive and negative output currents are less likely to shift.

It is needless to say that the same effect can be obtained when mirror circuits are further stacked in multiple stages.

A read control MO is connected between the positive output input terminal 67 and the input transistor 20 of the mirror circuit 2.
The S transistor 9 is connected between the input terminal 66 for the negative output and the input transistor 22 of the mirror circuit 3 for reading control.
If the MOS transistors 10 are inserted and controlled in accordance with the access to the transmission gate 68, no current flows to the input side of the mirror circuit except when a current flows from the output terminal 69, so that power consumption can be reduced. I can do it.

Further, in the figure, although the n-MOS is used as the read control MOS transistors 9 and 10, the same effect can be obtained by using the p-MOS.

Embodiment 14 FIG. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 25 shows another specific example of the circuit configuration used for the cancellation circuit 60 in FIG. 19 of the ninth embodiment and FIG. 22 of the eleventh embodiment.
In the figure, 9 to 11, 27 and 28 are the same as those in FIG. 16a and 66 to 69 are the same as those in FIGS. With such a structure, the offset readout circuit 60 can be realized with a simple circuit configuration.

Here, a read control MOS is provided between the negative output input terminal 66 and the input transistor 27 of the mirror circuit.
When the transistor 10 is inserted and controlled according to the access to the transmission gate 68, the output terminal 69
Since no current flows to the input side of the mirror circuit except when a current flows from the mirror circuit, power consumption can be reduced.

Further, a read control MOS transistor 9 is inserted between the positive output input terminal 67 and the transmission gate 68 and is controlled in accordance with the access to the transmission gate 68. Therefore, it is easy to make the magnitudes of the positive and negative output currents equal.

Further, in the figure, n-MOS is used as the read control MOS transistors 9 and 10, but the same effect can be obtained by using p-MOS.

Also in this structure, mirror circuits are stacked in multiple stages as shown in FIG. 24, so that when the transistor characteristics change due to manufacturing variations or temperature changes, the magnitudes of the positive and negative output currents are increased. Is less likely to occur.

Embodiment 15 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 26 shows a circuit configuration that is partially added to the circuit of FIG. 19 of the ninth embodiment and the circuit of FIG. 22 of the eleventh embodiment, and FIG. 23 of the twelfth embodiment and FIG. FIG. 2 of Embodiment 14
5 in FIG. 19 of the ninth embodiment and FIG. 2 in the eleventh embodiment.
2 is to improve the reading speed when applied to the middle cancellation circuit 60. 34 and 41 and 57 to 60 in the figure are the same as those in FIGS. Reference numeral 70 denotes a MOS transistor for precharging the wiring in the pixel array, and when the horizontal scanning circuit is accessing a certain column for reading, the potential of the wiring of the column to be read by the next clock is reduced to a certain potential. Precharge. Reference numeral 71 denotes a power line for precharging.

For example, consider the read speed when the read control MOS transistors 9 and 10 are inserted into the canceling read circuit 60 as shown in FIG. 23 of the twelfth embodiment. When a current is to flow from the terminal 67 of the circuit of FIG. 23 to the pixel array, the pixel array wiring is first charged to the read potential by the transistors 7 and 9 at the moment of access from the horizontal scanning circuit through the terminal 16a. Must. Here, since the input side transistor 7 of the mirror circuit is diode-connected, the driving ability is relatively weak. When the number of pixels is large, it takes a long time to charge, and high-speed reading may not be performed. Conversely, for example, when a current is to flow from the terminal 66 of the circuit of FIG. 23 to the pixel array, the potential of the output terminal having a large capacitance is changed to the potential of the wiring in the pixel array at the moment when the transmission gate 68 and the transistor 10 are opened. , The current may overshoot significantly, and it may take time for the current to stabilize.

With the configuration as shown in FIG. 26, the offset readout circuit itself does not need to charge the wiring, and the drive is such that the potential of the wiring in the pixel array is stabilized in advance and then the transmission gate is opened. Therefore, high-speed reading can be performed.

In the figure, an n-MOS transistor is used as the precharge MOS transistor 70, but a p-MOS transistor is used.
It may be a transistor.

Embodiment 16 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 26 of the above embodiment
In this configuration, a line that is read by the next clock is simply always precharged. This configuration is sufficient when the horizontal scanning circuit accesses only one column. In this embodiment, when simultaneously accessing two adjacent columns, the output terminal 41 and the precharge power supply terminal 71 are used.
There is no column connected to both. FIG. 27 illustrates this. The offset readout circuit 151 used here is obtained by adding a circuit for adjusting timing to the circuit 60 in FIG.

FIG. 28 shows the offset readout circuit 151 in FIG.
The following shows a specific example. In the figure, 1 and 7 to 10, 16a, 66 to
69 is the same as FIG. Reference numeral 152 denotes a terminal to which a read control signal for the immediately preceding column is input, and reference numeral 153 denotes a terminal connected to the precharge line 71. In this circuit configuration, the transistors 9 and 10 are open if either terminal 16 or 152 is accessed. Thereby, first, the wiring connected to the terminal 67 in the pixel array is precharged by the transistor 7 itself. The terminal 66 is connected to the precharge terminal 153 when the access is made to the terminal 152, but is prohibited when the access from the terminal 16 is made. As a result, it is possible to precharge a column read by the next clock, and to prevent a column performing output from being connected to the precharge line.

FIG. 29 shows another specific example of the offset reading circuit 151 in FIG. In the figure, 1 and 9-1
1, 16, 18 to 23 and 66 to 69 are the same as those in FIG. FIG.
Similarly, the transistors 9 and 10 are open if the terminal of either 16 or 152 is accessed.
Are precharged by the 22 and 20 transistors themselves, respectively. In this structure, 66, 67
Are connected to the output terminal 69 via the mirror circuit, so that a precharge terminal and a precharge line like 153 in FIG. 28 and 71 in FIG. 27 become unnecessary.

In FIGS. 28 and 29, if the transistors 9 and 10 are p-MOS transistors, one inverter connected to them can be omitted, so that the structure can be simplified.

The logical structure shown in FIGS. 28 and 29 can be applied to FIG. 25 and other canceling read circuits.
Needless to say, different circuits may be used as long as they have the same logical structure.

Embodiment 17 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 30 is a diagram showing a configuration of a light receiving element array circuit according to an embodiment of the present invention. Output lines 38 from each pixel 54 are connected in two directions. In the figure, reference numerals 33, 38 and 54 are the same as those in FIG.
The output line 38 is connected to a first output terminal 76 via a first transmission gate 72 controlled by a first horizontal scanning circuit 74, and a second horizontal scanning circuit 75
Second transmission gate 73 controlled by
Is also connected to the second output terminal 77. Reference numeral 78 indicates the control lines 35, 36, 37, and 55 in FIG. 15 collectively for convenience.

With such a configuration, the current value of each column is read out to the first output terminal 76 by the first horizontal scanning circuit 74, or is read by the second horizontal scanning circuit 75 to the second output terminal.
You can select whether to read to 77. Therefore the first output terminal
Give a pattern to the column to output from 76, and the selection of the column to output from the second output terminal 77, positive output to the output from the first output terminal 76, to the output from the second output terminal 77 Fifth Embodiment If a negative weight is given and taken out while adding, Embodiment 5
Similarly, the output is automatically the result of a horizontal inter-pixel operation determined by the column selection pattern.

Thus, the irradiated one-dimensional or two-dimensional light pattern can be taken out simultaneously, in parallel, and while performing the calculation between pixels in the horizontal direction.

When combined with the operation in the vertical direction by the vertical scanning circuit, a two-dimensional filter that can be defined by multiplication of two vectors can extract the result while automatically calculating the result.

Embodiment 18 FIG. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 31 is a diagram showing a configuration of a light receiving element array circuit according to an embodiment of the present invention. Two output lines 58 and 59 from each pixel 57 are connected in two directions. In the figure, 33 and 57 to 59 correspond to FIGS.
78 is the same as FIG. The output lines 58, 59 are connected to a first output terminal 76 via a first cancellation circuit 79 controlled by a first horizontal scanning circuit 74, and are controlled by a second horizontal scanning circuit 75. It is also connected to the second output terminal 77 via the second canceling circuit 80.

By providing the output current inverting circuit outside the pixel as described above, the structure of the pixel can be simplified and the pixel area can be reduced while maintaining the function of the variable sensitivity light receiving element array. .

Further, the reset power supply of the photoelectric conversion element is supplied only to the array section of the pixel 57, and the power supply for the output current is supplied only to the canceling readout circuits 79 and 80. Therefore, the two types of power supplies are completely separated. And increase reliability.

Embodiment 19 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 32 is a diagram showing a partial configuration of a light-receiving element array circuit according to an embodiment of the present invention, particularly showing a structure near an output terminal, where the array structure is shown in FIG. 34-38 and 40, 41, 54 in the figure,
55 is the same as FIG. Reference numeral 81 denotes a zero-point correction circuit in which the potential of the photoelectric conversion element is fixed to the power supply potential, for example, similar to the pixels shown in FIGS.

Next, the operation will be described. As described in the fourth embodiment, the normal output current has an offset value in a reset state, and is a negative-type readout in which the light intensity is lower and the longer the accumulation time, the lower the output value. For this reason, there has been a concern that the deviation of the offset value affects the accuracy of the pixel information. In the present embodiment,
This problem was solved by using the zero point correction circuit 81. For example, when a positive output current is flowing from one pixel to the output terminal 41, one of the zero point correction circuits 81 is accessed by Vn. Since a negative saturation current flows from here, the output terminal 41
Is the amount of change in the output current value from the saturation current value. That is, the output current is 0 in the reset state,
Positive reading can be realized, in which the light is strong and the longer the accumulation time is, the more the light rises there.

Also, unlike the case where the offset value at the time of reset is stored externally and the difference between the output current value and the output current value is externally stored, even if the offset value is deviated due to a temperature change or the like, the same offset circuit is used. Therefore, the image is hardly deteriorated. In addition, when taking out the current while adding the current between the pixels, the zero point correction circuit is equivalent to the number of pixels to be accessed.
Accessing 81 also keeps the offset value unchanged.

The zero point correction circuit 81 may use the same structure as the pixel to connect the potential of the photoelectric conversion element to a power supply, but may use only the output circuit.

Further, a zero point correction circuit 81 may be provided for each row. In this case, it is not necessary to count the number of pixels to be accessed.

Embodiment 20 FIG. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 33 is a diagram showing a partial configuration of a light-receiving element array circuit according to an embodiment of the present invention, particularly showing a structure near an output terminal, where the array structure is shown in FIG. In the figure 34-37 and 41, 55, 57
60 are the same as those in FIG. Reference numeral 82 denotes a zero-point correction circuit including pixels as shown in FIGS. 17 and 21 in which the potential of the photoelectric conversion element is fixed at the power supply potential. Reference numeral 83 denotes a zero-point correction enable terminal. Here, the zero point correction circuit 82 is arranged beside the array, and the terminals of Vp and Vn are reversed from those in the array.

Next, the operation will be described. First, the positive output of this configuration will be described. The zero point correction circuit in the row where the positive output is accessed automatically enters the negative output access state, from which a negative saturation current flows.When this output is enabled by the terminal 83, the output terminal The current value extracted from 41 is a variation of the output current value from the saturation current value. That is, the output current is zero in the reset state, is 0 in the reset state, the light is strong, and the longer the accumulation time is, the higher the output current is. In the case of a negative output with this configuration, the zero point correction circuit in the row to which the negative output has been accessed automatically enters the positive output access state, and the offset value is similarly removed and reading is realized.

In this embodiment, since the zero point correction circuit 82 is provided for each row, it is not necessary to specify the number of zero point correction circuits to be accessed from outside.

Further, even in the case where the canceling circuit is included, the zero point correcting circuit may be arranged separately from the array as in the nineteenth embodiment.

Embodiment 21 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 34 is a diagram showing a partial configuration of a light receiving element array circuit according to an embodiment of the present invention, particularly showing a structure near an output terminal, in which the array structure is shown in FIG. Reference numerals 34, 40 and 41 in the figure are the same as those in FIG. 84 is an amplifier that converts the output current into a voltage, 85 is a circuit that converts the analog voltage of the amplifier into a digital value, 86 is a reference voltage terminal 87 of the amplifier 84, a voltage output terminal from the amplifier 84, and 88 is a digital output terminal. is there. That is, an example is shown in which a current / voltage conversion amplifier 84 is provided in the array structure of FIG.

As described above, the current / voltage conversion amplifier 84 is internally provided.
Is provided, the output from the array can be a voltage instead of a current. Therefore, it is not necessary to convert the output current into a voltage in a subsequent stage, and data can be easily handled. That is, it is possible to output a signal that facilitates signal processing in a subsequent stage.

Further, an analog / digital conversion circuit is internally provided.
When 85 is provided, the output from the array can be converted to a digital value instead of an analog voltage, so that it is not necessary to convert the output to a digital signal at a subsequent stage, and the data can be easily handled.

Embodiment 22 FIG. Embodiment 5 and 6,
9, 11, 17, and 18, the light-receiving element circuit arrays shown in the respective embodiments (FIGS. 13, 15, 19, 22,.
30 and 31), for example, when Vp is accessed from the vertical scanning circuit to all the rows, the data corresponding to the sum of the currents from all the pixels in each column, that is, the sum of the light amounts applied to each column is obtained. Will be output. At this time, it is possible to obtain a one-dimensional projection in which the light pattern applied to the two-dimensional pixel array is projected on a horizontal scanning circuit. However, when extracting the output current from all the pixels in each column, more current is consumed by the number of pixels than in the normal readout. When reading out, the output current value for each pixel may be kept small.

As one method of suppressing the output current value for each pixel to be small, for example, FIG.
In the array of FIG. 15 and the arrays of FIGS. 19, 21 and 31 using the canceling readout circuit of FIG. 23, the potential of the output terminal 41 may be lower than usual, and output may be made through a path that does not pass through the mirror circuit. .

On the other hand, for example, in the arrays of FIGS. 13 and 30 using the pixel of FIG. 7 and the arrays of FIGS. 19, 22 and 31 using the canceling readout circuit of FIG.
What is necessary is just to raise the electric potential of 41 above normal, and to output by the path | route which does not pass a mirror circuit.

Embodiment 23 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 35 is a view for explaining an embodiment of the present invention, and is a conceptual diagram showing a basic circuit configuration of a pixel. In the figure, 1 to 3 and 12 are the same as in FIG. First, the photoelectric conversion element 3 is biased by the power supply terminal 1 through the reset switch 2. When charge is accumulated in the photoelectric conversion element 3 by light incidence, the photoelectric conversion element 3
Of the photoelectric conversion element is converted into a current, and the output terminal 90 outputs a current. A specific structure for reliably fixing the ground potential of the photoelectric conversion element 3 will be described below.

FIG. 36 is a circuit layout diagram showing an embodiment of the present invention, and is a plan view and a sectional view showing a layout of the photoelectric conversion element 3 in particular. 91 is the photoelectric conversion element 3
Numeral 92 is a p-type diffusion region whose potential is set to ground, and 93 is an n-type diffusion region whose potential is set to a power source.

In FIG. 36, the ground potential of the photoelectric conversion element 91 can be reliably fixed to ground by the p-type diffusion region 92 whose potential is grounded.

Here, if the photoelectric conversion element 91 receives strong light and generates too much electrons, it may affect the control circuit or the photoelectric conversion element of an adjacent pixel. The n-type diffusion region 93 having a potential applied to the power supply can prevent surplus electrons generated in the photoelectric conversion element 91 from entering a control circuit in a pixel or an adjacent pixel.

Conversely, n-type diffusion region 93 having a potential applied to the power supply
Surplus electrons generated in adjacent pixels
It is also possible to prevent the intrusion into 91 and output false image information.

Embodiment 24 FIG. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 37 is a circuit layout diagram showing another embodiment of the present invention, which is another layout of the photoelectric conversion element 3 in FIG. In the figure, 94 is a contact hole, and 95 is an aluminum wiring. The n-type diffusion region portion 91 of the photoelectric conversion element 3 forms a photodiode by joining with the p-well. A plurality of contact holes 94 are provided inside the diffusion region 91 and connected by an aluminum wiring 95.

If the potential inside the diffusion region 91 varies, a circuit 89 for converting the potential of the diffusion region 91 to the reset switch transistor 2 and the potential of the diffusion region 91 and the photoelectric conversion element to a current and outputting the current. And the inside of the photodiode may be at different potentials. By providing a plurality of contact holes inside the diffusion region 91 as shown in FIG. 37 and connecting them with aluminum wiring,
Such a variation in potential can be prevented.

It goes without saying that the arrangement of the contact holes is not limited to the shape shown in the figure.

Embodiment 25 FIG. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 38 is a circuit configuration diagram showing this embodiment. In the figure, reference numeral 96 denotes a unit pixel circuit, and reference numeral 97 denotes a pixel array in which the unit pixel circuits 96 are two-dimensionally arranged. Reference numeral 98 denotes a circuit that scans the pixel array 97 vertically, 99 denotes a circuit that scans the pixel array 97 horizontally, 100 denotes an n-type diffusion region having a potential at ground, and 101 denotes a p-type diffusion having a potential at the power supply. Area.

Here, by providing a p-type diffusion region 100 whose potential is grounded around the pixel array 97, the ground potential of the photoelectric conversion element 3 in the pixel array is reliably fixed to the ground potential. be able to.

By providing an n-type diffusion region 101 whose potential is taken as a power source around the pixel array 97, surplus electrons that overflow when the photoelectric conversion element 3 in the pixel array is exposed to strong light can be removed. Before overflowing out of the pixel array, the potential can be absorbed by the n-type diffusion region 101 that is powered.

Conversely, it is possible to prevent noise generated in a circuit outside the pixel array from entering the light receiving element array.

Although the embodiments 22 to 25 are based on the premise that an n-type diffusion region is formed on a p-well to form a photoelectric conversion element, n and p, and the ground potential and the power supply potential are reversed. Therefore, it is clear that the present invention is also effective when a p-type diffusion region is formed on an n-well to form a photoelectric conversion element. The same applies to a photodiode formed on a substrate.

Embodiment 26 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 39 is a diagram showing a circuit configuration according to this embodiment. In the figure, 1 to 3, 12 and 90 are the same as those in FIG. Further, 102 is a diode-connected p-MOS transistor, 103 is a p-MOS transistor that converts the potential of the photoelectric conversion element 3 into current, and 104 is a circuit that outputs current according to an external control signal.
The output signal is obtained as a current generated when the potential of the photoelectric conversion element 3 decreases according to the amount of light incident on the photoelectric conversion element 3 and is input to the gate of the p-MOS transistor 103.

Diode-connected p-MOS transistor 102
If there is no, the photoelectric conversion element 3 is reset to the power supply potential. When an attempt is made to monitor a potential change from the output current value of the p-MOS transistor 24, the output current remains at 0 until the potential of the photoelectric conversion element 3 falls below the power supply potential by the threshold voltage of the p-MOS transistor 103. That is, there is a problem that the output signal does not change if the light is weak and the accumulation time is not sufficiently long even if the light is applied.

Therefore, the diode-connected p-MOS transistor 102 is connected in series with the MOS transistor 2 for resetting the photoelectric conversion element 3 so that the potential of the photoelectric conversion element 3 is higher than the power supply potential by the threshold voltage of the p-MOS transistor 102. If only a low potential is reset, an output current can be made to appear as shown in FIG. 9 even when the amount of incident light is small.

Further, the gate length of the p-MOS transistor 102,
If the gate width is made the same as that of the p-MOS transistor 103, the threshold voltage can be made completely the same. Therefore, in FIG. Can be matched.

In this configuration, the p-MOS transistor 103
Even if the threshold voltage varies within the chip, the variation is compensated in the form of the reset potential of the photoelectric conversion element 3, so that the fixed pattern noise can be reduced.

In the figure, the p-MOS transistor 102
Are arranged closer to the power supply than the reset MOS transistor 2. However, it is needless to say that the same effect can be obtained even if the upper and lower sides are exchanged.

In FIG. 7 of the fourth embodiment,
Although a specific circuit is shown, it is not limited to the circuit of FIG.

Embodiment 27 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 40 is a diagram showing a circuit configuration according to this embodiment. Reference numerals 1 to 3, 12, 89 and 90 in the figure are the same as those in FIG. A switching transistor 105 is controlled by the horizontal scanning circuit when the light receiving element array is formed.

FIG. 13, FIG. 15, FIG. 19, FIG. 22, FIG.
0, 31 and 38, when each pixel does not have the switching transistor 105, the reset of the pixel is performed simultaneously in one row by a reset pulse from the vertical scanning circuit 98, In the reading, the output is read in the column direction by the horizontal scanning circuit 99 while applying the reading pulse from the vertical scanning circuit 98. Therefore, even in the pixels in the same row, there is a difference in the accumulation time by the time required for multiplexing. That is, the pixels on the left side of the row have a short accumulation time, and the pixels on the right side of the row have a long accumulation time. This is particularly noticeable when the accumulation time is short.

Therefore, as shown in FIG. 40, the switching transistor 105 controlled by a signal from the horizontal scanning circuit is connected in series with the transistor for resetting the photoelectric conversion element 3.
Is connected, the reset timing of the photoelectric conversion element 3 can be controlled also in the column direction, and the difference in the accumulation time in the same row can be eliminated.

Although the switching transistor 105 is arranged farther from the power supply than the reset MOS transistor 2 in the figure, it is needless to say that the same effect can be obtained even if the switching transistor 105 is switched upside down.

Embodiment 28 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 41 is a diagram showing a circuit configuration according to this embodiment. 1 to 3, 12,
89 and 90 are the same as those in FIG. In the figure, reference numeral 106 denotes an n-MOS transistor having a drain connected to the photoelectric conversion element 3 and a source connected to the power supply potential, and a gate fixed at a potential of 1 to 3 times the threshold voltage.

FIG. 42 is a sectional view of a portion including the n-MOS transistor 106 shown in FIG. 41 and an energy diagram of electrons. In the figure, 1 and 106 are the same as FIG. 41, and 91 is the same as FIG. More electrons are generated as the strong light impinges on the photoelectric conversion element 3. However, if the light is too strong and the electrons are generated too much, the overflowed electrons may enter the photoelectric conversion elements of peripheral circuits and other pixels.

Then, the n-MOS transistor 106 is connected,
If a potential that is 1 to 3 times the threshold voltage is applied to the gate, the electrons can be inductively absorbed into the power supply potential before overflowing as shown in FIG.

Embodiment 29 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 43 is a diagram showing a circuit configuration according to this embodiment. Reference numerals 96 to 98 in the figure are the same as those in FIG. Reference numeral 107 denotes a pulse level conversion circuit, reference numeral 108 denotes a power supply that applies a voltage equal to or higher than the sum of the power supply voltage and the threshold voltage of the reset switch, and reference numeral 109 denotes a power supply that applies a voltage one to three times the threshold voltage of the reset switch. In the figure, 108 is drawn as a 7V power supply and 109 is a 1V power supply, but any voltage may be used as long as the above conditions are satisfied.

In this circuit, the reset transistor 2
, A 0V-5V pulse from the vertical scanning circuit is converted to 1V-7V to reset n-MOS in the pixel 96.
In addition to the gate of the MOS transistor. That is, in the state where there is no access from the vertical scanning circuit and during the accumulation time,
A voltage of 1 to 3 times the threshold voltage is applied to the gate so that the overflowed electrons can be absorbed, and the photoelectric conversion element 3
When a reset operation is performed on the photoelectric conversion element 3 by applying a voltage equal to or higher than the sum of the power supply potential and the threshold to the gate.
Is surely reset to the power supply potential.

When an n-MOS is used as the reset transistor as described above, for example, if the output circuit is configured only with the n-MOS as shown in FIG. Since it can be configured, the structure of the pixel can be simplified and the pixel area can be reduced.

Embodiment 30 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 44 is a diagram showing a unit pixel circuit configuration according to this embodiment. 1,
3, 12, 89 and 90 are the same as those in FIG. 110 is a power supply for the readout circuit. When a common power supply line is used as the reset bias power supply 1 of the photoelectric conversion element 3 and the power supply 110 for the readout circuit, when a certain pixel performs a reset operation, reading is performed by another pixel sharing the power supply line. If it is performed, a potential drop corresponding to the output current value may occur in the power supply line, and the photoelectric conversion element 3 may not completely rise to the power supply potential. This means that when reading in the next cycle, the previous image information is read out while remaining, which causes a so-called ghost phenomenon.

This problem can be avoided by separating the reset power supply 1 from the read circuit power supply 110.

Embodiment 31 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 45 is a sectional view of a pixel in the light receiving element circuit according to this embodiment.
1 to 3 are the same as in FIG. 1, and 50 and 63 are the same as in FIG. Reference numeral 111 denotes a light-shielding metal film, and reference numeral 112 denotes a p-well.

When the memory capacitor 50 is made of a pn diode, the drain of the n-MOS transistor can be used as a capacitor as it is, so that the pixel structure can be simplified and the pixel area can be reduced. .

Also, by covering the portion other than the photoelectric conversion portion with the light shielding metal film 111, unnecessary photocharges are generated in the circuit portion to output a false signal and the capacitance 50 is discharged. Can be avoided.

[0204]

As described above, the light-receiving element circuit according to claim 1 of the present invention absorbs light and takes out a photocurrent corresponding to a control voltage to the outside as a positive or negative output signal. A differential amplifier comprising a mirror circuit that controls the output signal, the light receiving element circuit being provided in series with an element connected to a positive output terminal in the mirror circuit, Since read control means is controlled in synchronization with the output, even when there is an input from the positive output terminal, no current flows to the input side of the mirror circuit except when outputting a current from the output terminal. , Power consumption can be reduced.

Further, the light receiving element circuit according to claim 2 of the present invention further comprises second reading control means in series with the element to which the negative output terminal in the mirror circuit is connected. So the symmetry of the mirror circuit is better,
The magnitudes of the positive and negative output currents can be made equal.

Further, according to a third aspect of the present invention, in the light receiving element circuit according to the first or second aspect, the differential amplifier has an n-MOS transistor having at least a source fixed to a substrate potential. A multi-stage mirror circuit including a circuit and second and third mirror circuits having p-MOS transistors whose sources are fixed to the power supply potential is provided. When the characteristics change, the magnitude of the positive and negative output currents is less likely to shift.

A light receiving element circuit according to claim 4 of the present invention absorbs light and takes out a photocurrent corresponding to a control voltage to the outside as a positive or negative output signal, and controls the output signal. And a reset means for setting the potential of the light receiving element to the potential adjusted by the reset potential adjusting means, so that an output signal is output even when the light is weak. It is possible to obtain a positive reading as follows.

Further, the light receiving element circuit according to claim 5 of the present invention according to any one of claims 1 to 4, absorbs light and externally outputs a photocurrent according to a control voltage as a positive or negative output signal. A light-receiving element circuit including a light-receiving element to be extracted and a differential amplifier for controlling the output signal, and having a means for adjusting the timing of reset means for resetting the potential of the light-receiving element, has an array structure. Sometimes the reset timing can also be controlled in the column direction, so that the difference in the accumulation time in the same row can be eliminated, and a highly accurate light receiving element circuit can be realized.

A light-receiving element circuit according to claim 6 of the present invention is a light-receiving element which absorbs light and takes out a photocurrent corresponding to a control voltage to the outside as a positive or negative output signal, and controls the output signal. Control circuit and means for storing the potential generated in the light receiving element in accordance with the amount of light absorption, so that output of a temporal change in the amount of light between frames and output with less fixed pattern noise can be performed. Also, an operation like an electronic shutter can be realized.

A light-receiving element circuit according to claim 7 of the present invention is a light-receiving element that absorbs light and takes out a photocurrent corresponding to a control voltage to the outside as a positive or negative output signal, and controls the output signal. And a control circuit for transmitting a plurality of output signals to a plurality of output terminals controlled by an external control signal, so that the control circuit is simple. The pixel structure can be simplified, and the reliability of the pixel can be improved.

[0211] The light-receiving element circuit according to claim 8 of the present invention, in any one of claims 1 to 7, has a structure in which the light-receiving element is surrounded by a diffusion region connected to a ground potential or a power supply potential. Therefore, surplus electrons generated in the light receiving element can be prevented from entering the control circuit in the pixel or an adjacent pixel, and the reliability of the pixel is improved.

Further, in the light receiving element circuit according to claim 9 of the present invention, in any one of claims 1 to 7, the light receiving element has a plurality of contact holes and the contact holes are connected to each other. In addition, variations in the potential of the light receiving element can be prevented, and the reliability of the light receiving element circuit is improved.

According to a tenth aspect of the present invention, there is provided a light receiving element circuit according to any one of the first to seventh aspects, wherein the excess electrons accumulated in the light receiving element are provided in parallel with reset means for resetting the potential of the light receiving element. Since the removing means is provided, excess electrons generated in the light receiving element can be induced to the power supply potential so as not to enter a peripheral circuit or another pixel.

The light-receiving element circuit according to claim 11 of the present invention is characterized in that, in any one of claims 1 to 7, a power supply potential connected to reset means for resetting a potential of the light-receiving element and a control circuit connected to a control circuit. Since the power supply potential is independent from the power supply potential, even if a potential drop depending on the output current occurs in the power supply line, the light receiving element can be sufficiently reset.

According to a twelfth aspect of the present invention, there is provided a light receiving element circuit according to any one of the first to eleventh aspects, wherein the control circuit is shielded by a metal film via an insulating film. Noise due to photocharge can be avoided.

According to a thirteenth aspect of the present invention, there is provided a light-receiving element circuit array according to any one of the first to third aspects, wherein the light-receiving element circuits are arranged in a two-dimensional array and arranged in a horizontal direction. The connection terminal connected to the reset means, the positive output terminal, and the negative output terminal are shared for each row, connected to the vertical scanning difference circuit, and read out of the light receiving element circuits arranged in the vertical direction. The read control terminal connected to the control means is shared by one column and connected to a horizontal scanning circuit, and the output terminals of the light receiving element circuits arranged in the vertical direction are shared by one column, and the horizontal scanning circuit When connected to the array output terminal via the transmission gate controlled by the above, when irradiating one-dimensional or two-dimensional light pattern simultaneously, in parallel, and taking out while performing vertical pixel-to-pixel operation , Since no current flows to the input side of the mirror circuit except when that transmission gate opens at each column, it is possible to reduce the power consumption.

According to a fourteenth aspect of the present invention, there is provided a light-receiving element circuit array, wherein the light-receiving element circuits according to the sixth aspect are arranged in a two-dimensional array and are arranged in a horizontal direction. , A positive output terminal, a negative output terminal, and a memory control terminal connected to a means for storing a potential generated in the light receiving element, for each row, and the vertical scanning difference. Since the output terminals of the respective light receiving element circuits connected in a vertical direction are connected to each other in a row and connected to an array output terminal via a transmission gate controlled by a horizontal scanning circuit, the connection between the frames can be prevented. It is possible to output a change in the amount of light over time and output with less fixed pattern noise, and also to realize an operation like an electronic shutter.

According to a fifteenth aspect of the present invention, there is provided a light-receiving element circuit array, wherein the light-receiving element circuits according to the seventh aspect are arranged in a two-dimensional array and are arranged in a horizontal direction. A plurality of output terminals of each of the light receiving element circuits which are connected to a vertical scanning difference circuit by sharing a connection terminal, a positive output terminal, and a negative output terminal for each row, and are arranged in a vertical direction. Are shared by each column, and a plurality of output terminal lines composed of the shared output terminals are connected to one line.
Each column is connected to the array output terminal via a canceling circuit controlled by a horizontal scanning circuit. Therefore, by providing an output current inverting circuit outside the pixel, the structure of the pixel (light receiving element) is simplified, The area can be reduced.

The light receiving element circuit array according to a sixteenth aspect of the present invention is the light receiving element circuit according to the fifteenth aspect, wherein the light receiving element circuit includes means for storing a potential generated in the light receiving element in accordance with an amount of light absorption. Since the memory control terminal connected to the means for storing the potential generated in the element is shared for each row and connected to the vertical scanning difference circuit, the output current inverting circuit is provided outside the pixel. The structure of the (light receiving element) can be simplified, the pixel area can be reduced, and the array can have a memory function to output a temporal change in the amount of light between frames.

According to a seventeenth aspect of the present invention, in the light-receiving element circuit array according to the fifteenth or sixteenth aspect, the canceling circuit has a p-MOS transistor whose source is fixed to a power supply potential, and is arranged in a vertical direction. A plurality of output terminal lines of the light receiving element circuit to be input, and a mirror circuit whose reading is controlled by a horizontal scanning circuit; and a transmission gate connected to an output side from the mirror circuit and controlled by the horizontal scanning circuit. Therefore, the current can be prevented from flowing to the input side of the mirror circuit except when the current flows from the output terminal, so that the power consumption can be reduced.

[0221] In the light-receiving element circuit array according to claim 18 of the present invention, in the claim 15 or 16, the canceling circuit is a first mirror circuit having an n-MOS transistor whose source is fixed to the substrate potential. And second and third mirror circuits each having a p-MOS transistor whose source is fixed to the power supply potential. The plurality of output terminal lines of the light receiving element circuits arranged in the vertical direction are input, and the reading is performed. Since a multi-stage mirror circuit controlled by the horizontal scanning circuit and a transmission gate connected to the output side of the mirror circuit and controlled by the horizontal scanning circuit are provided, in the canceling circuit, manufacturing variations and temperature changes Therefore, when the characteristics of the transistor change, the magnitude of the positive and negative output currents is less likely to shift.

According to a nineteenth aspect of the present invention, in the light receiving element circuit array according to the fifteenth or sixteenth aspect, the canceling circuit has an n-MOS transistor whose source is fixed to the substrate potential and is arranged in a vertical direction. A plurality of output terminal lines of the light receiving element circuit to be input, and a mirror circuit whose reading is controlled by a horizontal scanning circuit; and a transmission gate connected to an output side from the mirror circuit and controlled by the horizontal scanning circuit. Therefore, the current can be prevented from flowing to the input side of the mirror circuit except when the current flows from the output terminal, so that the power consumption can be reduced.

Further, in the light receiving element circuit array according to claim 20 of the present invention, since a precharge line for pre-charging the light receiving element circuit is provided on the input side of the canceling circuit in claim 15 or 16, The canceling readout circuit itself does not need to charge the wiring, and can drive the wiring in the pixel array in advance by stabilizing the potential, so that high-speed reading can be performed.

Further, in the light receiving element circuit array according to claim 21 of the present invention, since means for adjusting the timing of connection between the precharge line and the readout is further provided in claim 20, two adjacent columns are simultaneously accessed. Will be able to

Further, in the light receiving element circuit array according to claim 22 of the present invention, since a plurality of horizontal scanning circuits are arranged in any one of claims 14 to 16, the illuminated one-dimensional or two-dimensional light pattern is formed. At the same time, they can be extracted in parallel and while performing inter-pixel operations in the horizontal direction.

Also, in the light receiving element circuit array according to claim 23 of the present invention, since the circuit for correcting the potential of the light receiving element whose output is connected to the array output terminal is provided in any one of claims 13 to 16, Reading can be of a positive type, and the accuracy of the light receiving element circuit array is improved.

In the light-receiving element circuit array according to claim 24 of the present invention, since the current-voltage conversion circuit is provided at the array output terminal in any one of claims 13 to 16,
The output from the array can be a voltage instead of a current. Therefore, it is not necessary to convert the output current into a voltage in a subsequent stage, and data can be easily handled. That is, it is possible to output a signal that facilitates signal processing in a subsequent stage.

Further, the light receiving element circuit array according to claim 25 of the present invention further comprises a circuit for converting an analog voltage into a digital value, so that the output from the array is converted into a digital value instead of an analog voltage. Therefore, there is no need to perform digital conversion in the subsequent stage, and data handling becomes easy.

According to a twenty-sixth aspect of the present invention, in the light receiving element circuit array according to any one of the thirteenth to sixteenth aspects, the light receiving element circuit array is surrounded by a diffusion region connected to a power supply potential or a ground potential. Therefore, the ground potential of the light receiving element in the pixel array can be reliably fixed to the ground potential. In addition, the excess electrons that have overflowed when the light receiving element in the pixel array is irradiated with strong light can be absorbed by the diffusion region that is supplied with the electric power before the extra electrons overflow the outside of the pixel array. Further, it is possible to prevent noise generated in a circuit outside the pixel array from entering the light receiving element array.

According to a twenty-seventh aspect of the present invention, in the light receiving element circuit array according to any one of the thirteenth to sixteenth aspects, the means for resetting the light receiving element of the light receiving element circuit is n-type.
It is composed of MOS transistors and controls the n-MOS transistor. Since the potential of the pulse signal sent from the vertical scanning circuit is defined by the threshold voltage of the n-MOS transistor, there is no access from the vertical scanning circuit. In the state during the accumulation time, a voltage of 1 to 3 times the threshold voltage is applied to the gate so that the overflowed electrons can be absorbed. When the photoelectric conversion element 3 is reset, a voltage higher than the sum of the power supply potential and the threshold is applied. Is applied to the gate to surely reset the photoelectric conversion element 3 to the power supply potential.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a light receiving element circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of another light receiving element circuit according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a light receiving element circuit according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a light receiving element circuit according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram of another light receiving element circuit according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of another light receiving element circuit according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a light receiving element circuit according to a fourth embodiment of the present invention.

FIG. 8 is a diagram illustrating a relationship between a light irradiation time (accumulation time) and an output current of the light receiving element circuits according to the first to third embodiments.

FIG. 9 is a diagram illustrating a relationship (output characteristic) between a light irradiation time (light amount) and an output current of a light receiving element circuit according to a fourth embodiment of the present invention.

FIG. 10 is a configuration diagram of another light receiving element circuit according to a fourth embodiment of the present invention.

FIG. 11 is a configuration diagram of another light receiving element circuit according to a fourth embodiment of the present invention.

FIG. 12 is a configuration diagram of another light receiving element circuit according to Embodiment 4 of the present invention.

FIG. 13 is a configuration diagram of a light receiving element circuit array according to a fifth embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a light receiving element circuit according to a sixth embodiment of the present invention.

FIG. 15 is a configuration diagram of a light receiving element circuit array according to a sixth embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a light receiving element circuit according to a seventh embodiment of the present invention.

FIG. 17 is a configuration diagram of a light receiving element circuit according to a seventh embodiment of the present invention, showing a specific example of FIG. 16;

FIG. 18 is a configuration diagram of a light receiving element circuit according to an eighth embodiment of the present invention.

FIG. 19 is a configuration diagram of a light receiving element circuit array according to a ninth embodiment of the present invention.

FIG. 20 is a block diagram showing a configuration of a light receiving element circuit according to a tenth embodiment of the present invention.

FIG. 21 is a configuration diagram of a light receiving element circuit according to a tenth embodiment of the present invention, showing a specific example of FIG. 20;

FIG. 22 is a configuration diagram of a light receiving element circuit array according to an eleventh embodiment of the present invention.

FIG. 23 is a configuration diagram of a cancellation circuit used in a light receiving element circuit array according to a twelfth embodiment of the present invention.

FIG. 24 is a configuration diagram of a cancellation circuit used in a light receiving element circuit array according to a thirteenth embodiment of the present invention.

FIG. 25 is a configuration diagram of a cancellation circuit used in a light receiving element circuit array according to Embodiment 14 of the present invention.

FIG. 26 is a partial schematic configuration diagram of a light receiving element circuit array according to Embodiment 15 of the present invention.

FIG. 27 is a partial schematic configuration diagram of a light receiving element circuit array according to Embodiment 16 of the present invention.

FIG. 28 is a diagram showing a specific configuration of a cancellation circuit in FIG. 27;

29 is a diagram showing another specific configuration of the cancellation circuit in FIG. 27.

FIG. 30 is a configuration diagram of a light receiving element circuit array according to a seventeenth embodiment of the present invention.

FIG. 31 is a configuration diagram of a light receiving element circuit array according to Embodiment 18 of the present invention.

FIG. 32 is a partial schematic configuration diagram of a light receiving element circuit array according to a nineteenth embodiment of the present invention.

FIG. 33 is a partial schematic configuration diagram of a light receiving element circuit array according to a twentieth embodiment of the present invention.

FIG. 34 is a partial schematic configuration diagram of a light receiving element circuit array according to a twenty-first embodiment of the present invention.

FIG. 35 is a block diagram showing a configuration of a light receiving element circuit according to Embodiment 23 of the present invention.

FIG. 36 is a plan view and a sectional view showing a layout of a specific light receiving element according to a twenty-third embodiment of the present invention.

FIG. 37 is a plan view showing a specific light receiving element layout according to the twenty-fourth embodiment of the present invention.

FIG. 38 is a plan view showing a layout of a specific light receiving element circuit array according to the twenty-fifth embodiment of the present invention.

FIG. 39 is a block diagram showing a configuration of a light receiving element circuit according to Embodiment 26 of the present invention.

FIG. 40 is a block diagram showing a configuration of a light receiving element circuit according to Embodiment 27 of the present invention.

FIG. 41 is a block diagram showing a configuration of a light receiving element circuit according to Embodiment 28 of the present invention.

FIG. 42 is an energy diagram for explaining effects of the light receiving element circuit according to the twenty-eighth embodiment of the present invention;

FIG. 43 is a block diagram showing a configuration of a light receiving element circuit according to Embodiment 29 of the present invention.

FIG. 44 is a block diagram showing a configuration of a light receiving element circuit according to Embodiment 30 of the present invention.

FIG. 45 is a cross-sectional view showing a configuration of a light receiving element circuit according to Embodiment 31 of the present invention.

FIG. 46 is a diagram showing a configuration of a conventional light receiving element circuit.

FIG. 47 is a diagram showing a configuration of a conventional light receiving element circuit array.

FIG. 48 is a diagram showing a configuration of a conventional light receiving element circuit array and peripheral circuits.

FIG. 49 is a diagram showing a configuration of another conventional light receiving element circuit.

[Explanation of symbols]

1 Power supply line, 2 MOS for resetting photoelectric conversion element
Transistor, 3 photoelectric conversion element, 4 n-MOS transistor for differential amplifier bias current, 5 n-MOS for negative output
Transistor, 6 N-MOS transistor for positive output, 7
Input side p-MOS transistor of current mirror circuit, 8
Output side p-MOS transistor of current mirror circuit, 9
Positive output side read control MOS transistor, 10 Negative output side read control MOS transistor, 11 Ground line, 12 Substrate contact, 13 Reset terminal, 14
Negative output terminal, 15 Positive output terminal, 16, 16a Readout control terminal, 17 pixel output terminal, 18 Input n-MOS transistor of current mirror circuit 1, 19 Output n-MOS transistor of current mirror circuit 1 , 20 the input side n-MOS transistor of the current mirror circuit 2, 21 the output side n-MOS transistor of the current mirror circuit 2, 22
Input side n-MOS transistor of current mirror circuit 3, 23
Output side n-MOS transistor of current mirror circuit 3, 2
4 p-MOS transistor for bias current of differential amplifier, 25
P-MOS transistor for negative output, 26 p-MOS transistor for positive output, 27 input n-MOS transistor for current mirror circuit, 28 output n-MOS transistor for current mirror circuit, 29 negative output terminal, 30 positive output Terminal,
31 Diode-connected p-MOS transistor for adjusting the reset potential of the photoelectric conversion element, 32 Unit pixel with variable sensitivity photodetector circuit, 33 Vertical scanning circuit, 34 Horizontal scanning circuit, 35 pixel reset line, 36 Negative output Line, 37 positive output line, 38 output line, 39
Readout control line, 40 transmission gate, 41 array output terminal, 42 circuit for converting the potential of the photoelectric conversion element to current, 43 first output circuit, 44 second output circuit, 45 first output control terminal, 46 second output control terminal, 47 first output terminal, 48 second output terminal, 49 first circuit for converting electric potential to current, 50
Capacitance, 51 a circuit for connecting the potential of the photoelectric conversion element to the capacitance,
52 Control terminal for memory, 53 Second circuit for converting potential to current, 54 Unit pixel with variable sensitivity photodetector circuit, 55
A control line for memory, 56 a second circuit for converting a potential into a current, 57, 57a a unit pixel with a variable sensitivity light receiving element circuit, 58 a first output line, 59 a second output line
60 canceling readout circuit, 61 n-MOS transistor connecting the potential of the photoelectric conversion element to the capacitance, 62 n-MOS transistor guiding the potential of the photoelectric conversion element to the gate, 63 capacitance 50
N-MOS transistor that led the potential to the gate, 64 first output transistor, 65 second output transistor, 66 input terminal for negative output, 67 input terminal for positive output, 68 transmission gate, 69 cancellation Output terminal from circuit, MO for pre-charging 70 pixel array wiring
S transistor, 71 Power supply for precharge, 72 First transmission gate, 73 Second transmission gate, 74 First horizontal scanning circuit, 75 Second horizontal scanning circuit, 76 First output terminal, 77 Second 78, control lines 35, 36, 37, and 55 in FIG. 8, 79 first offset readout circuit, 80 second offset readout circuit, 81 zero point correction circuit, 82 zero point correction circuit, 83 zero point Correction enable terminal, 84 Amplifier that converts output current to voltage, 85 Analog / Digital conversion circuit, 86 Reference voltage terminal, 87 Voltage output terminal, 88
Digital output terminal, 89 Circuit for converting the potential of photoelectric conversion element to current, 90 Output terminal, 91 N-type diffusion area of photoelectric conversion element, 92 P-type diffusion area with grounded potential, 93
N-type diffusion region with potential as power supply, 94 contact hole, 95 aluminum wiring, 96 contact hole inside diffusion region 9, 95 aluminum wiring, 96 unit pixel circuit, 97
A pixel array, a circuit that vertically scans the 98 pixel array,
99 A circuit for scanning the pixel array horizontally, 100 An n-type diffusion region with a potential at ground, 101 A p with potential at power
Type diffusion region, 102 diode-connected p-MOS transistor, 103 p-MOS transistor that converts the potential of the photoelectric conversion element to current, 104 circuit that outputs current by an external control signal, 105 controlled by the horizontal scanning circuit Switching transistor, 106 gate has threshold voltage of 1 to 1
N-MOS transistor fixed to triple the potential, 107 pulse level conversion circuit, 108 power supply that supplies a voltage equal to or higher than the sum of the power supply voltage and the threshold voltage of the reset switch, 109 one to three times the threshold voltage of the reset switch Power supply for applying voltage, power supply for 110 readout circuit

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H04B 10/04 10/06

Claims (27)

[Claims] 1. A light receiving device comprising: a light receiving element that absorbs light and takes out a photocurrent according to a control voltage as a positive or negative output signal to the outside; and a differential amplifier including a mirror circuit that controls the output signal. An element circuit, which is arranged in series with an element to which a positive output terminal in the mirror circuit is connected,
A light-receiving element circuit comprising: a read control unit that is controlled in synchronization with an output from the mirror circuit. 2. The light-receiving element circuit according to claim 1, further comprising a second read control unit in series with an element connected to the negative output terminal in the mirror circuit. 3. A first differential amplifier having an n-MOS transistor having at least a source fixed to a substrate potential.
And a p-M whose source is fixed to the power supply potential
3. The light receiving element circuit according to claim 1, further comprising a multi-stage mirror circuit including a second mirror circuit and a third mirror circuit having an OS transistor. 4. A light-receiving element circuit comprising: a light-receiving element that absorbs light and extracts a photocurrent corresponding to a control voltage to the outside as a positive or negative output signal; and a differential amplifier that controls the output signal. And a reset means for setting the potential of the light receiving element to a potential adjusted by reset potential adjusting means. 5. A light-receiving element circuit comprising: a light-receiving element that absorbs light and extracts a photocurrent corresponding to a control voltage to the outside as a positive or negative output signal; and a differential amplifier that controls the output signal. The light receiving element circuit according to any one of claims 1 to 4, further comprising: means for adjusting timing of reset means for resetting a potential of the light receiving element. 6. A light-receiving element which absorbs light and takes out a photocurrent according to a control voltage as a positive or negative output signal to the outside, a control circuit for controlling the output signal, and a control circuit for controlling the output signal. Means for storing a potential generated in the light receiving element. 7. A light-receiving element circuit comprising: a light-receiving element that absorbs light and extracts a photocurrent corresponding to a control voltage to the outside as a positive or negative output signal; and a control circuit that controls the output signal. And a control circuit for transmitting a plurality of output signals to a plurality of output terminals controlled by an external control signal. 8. The light-receiving element circuit according to claim 1, wherein the light-receiving element is surrounded by a diffusion region connected to a ground potential or a power supply potential. 9. The light receiving element circuit according to claim 1, wherein the light receiving element has a plurality of contact holes, and the contact holes are connected to each other. 10. The device according to claim 1, further comprising: an excess electron removing unit that is accumulated in the light receiving element, in parallel with the resetting unit that resets the potential of the light receiving element. Light receiving element circuit. 11. The power supply potential connected to the reset means for resetting the potential of the light receiving element and the power supply potential connected to the control circuit are made independent. The light receiving element circuit as described in the above. 12. The light receiving element circuit according to claim 1, wherein the control circuit is shielded by a metal film via an insulating film. 13. A connection terminal connected to reset means of each of the light-receiving element circuits, wherein the light-receiving element circuits according to claim 1 are arranged in a two-dimensional array and arranged in a horizontal direction. The output terminal and the negative output terminal are shared for each row and connected to the vertical scanning difference circuit, and the read control terminal connected to the read control means of each of the light receiving element circuits arranged in the vertical direction is connected to one. An output terminal of each of the light receiving element circuits arranged in the vertical direction is connected to a horizontal scanning circuit and shared by each column, and an output terminal of each of the light receiving element circuits arranged in the vertical direction is shared by each column. A light-receiving element circuit array, wherein 14. A light-receiving element circuit according to claim 6, wherein the light-receiving element circuits are arranged in a two-dimensional array and are arranged in a horizontal direction. A negative output terminal and a memory control terminal connected to a means for storing a potential generated in the light receiving element, shared by each row, connected to a vertical scanning difference circuit, and arranged in a vertical direction. A light receiving element circuit array, wherein output terminals of the circuit are shared for each column and connected to an array output terminal via a transmission gate controlled by a horizontal scanning circuit. 15. A light-receiving element circuit according to claim 7, wherein the light-receiving element circuits are arranged in a two-dimensional array and are arranged in a horizontal direction. A negative output terminal is shared for each row and connected to a vertical scanning difference circuit, and a plurality of output terminals of each of the light receiving element circuits arranged in the vertical direction are shared for each column, and the shared output is output. Multiple output terminal lines
A light receiving element circuit array connected to an array output terminal via a canceling circuit controlled by a horizontal scanning circuit for each column. 16. A light receiving element circuit, comprising: means for storing a potential generated in the light receiving element in accordance with an amount of light absorption; and a memory control terminal connected to the means for storing the potential generated in the light receiving element. 16. The light receiving element circuit array according to claim 15, wherein each row is shared and connected to a vertical scanning difference circuit. 17. The canceling circuit has a p-MOS transistor whose source is fixed to a power supply potential, inputs a plurality of output terminal lines of a light receiving element circuit arranged in a vertical direction, and controls reading by a horizontal scanning circuit. Mirror circuit
17. The light receiving element circuit array according to claim 15, further comprising a transmission gate connected to an output side of the mirror circuit and controlled by a horizontal scanning circuit. 18. A cancellation circuit comprising: a first mirror circuit having an n-MOS transistor whose source is fixed at a substrate potential; and a second and a second circuit having a p-MOS transistor having a source fixed at a power supply potential. A plurality of mirror circuits, and a plurality of output terminal lines of a light receiving element circuit arranged in the vertical direction are input, and a multi-stage mirror circuit in which reading is controlled by a horizontal scanning circuit; and an output side from the mirror circuit. 17. The light receiving element circuit array according to claim 15, further comprising a transmission gate connected to the transmission gate and controlled by a horizontal scanning circuit. 19. The canceling circuit has an n-MOS transistor whose source is fixed to a substrate potential, inputs a plurality of output terminal lines of a light receiving element circuit arranged in a vertical direction, and controls reading by a horizontal scanning circuit. Mirror circuit
17. The light receiving element circuit array according to claim 15, further comprising a transmission gate connected to an output side of the mirror circuit and controlled by a horizontal scanning circuit. 20. The light receiving element circuit array according to claim 15, wherein a precharge line for pre-charging the light receiving element circuit is provided on the input side of the canceling circuit. 21. The light receiving element circuit array according to claim 20, further comprising means for adjusting timing of connection between the precharge line and the readout. 22. The light-receiving element circuit array according to claim 14, wherein a plurality of horizontal scanning circuits are arranged. 23. The light receiving element circuit array according to claim 13, further comprising a correction circuit for correcting the potential of the light receiving element whose output is connected to the array output terminal. 24. The light receiving element circuit array according to claim 13, wherein a current-voltage conversion circuit is provided at the array output terminal. 25. The light receiving element circuit array according to claim 24, further comprising a circuit for converting an analog voltage to a digital value. 26. The light receiving element circuit array according to claim 13, wherein the light receiving element circuit array is surrounded by a diffusion region connected to a power supply potential or a ground potential. 27. A means for resetting a light-receiving element of a light-receiving element circuit comprises an n-MOS transistor.
2. A control circuit for controlling a MOS transistor, wherein the potential of the pulse signal sent from the vertical scanning circuit is defined by the threshold voltage of the n-MOS transistor.
17. The light receiving element circuit array according to any one of items 3 to 16.