JPH1097471A - Error correction method and error correction method for memory data - Google Patents

Abstract

(57) [Summary] The present invention relates to a data block transfer method for transmitting data blocks.
An error correction method and method for memory data that can reduce the size of a buffer for storing data and reduce the amount of data added to detect and correct data abnormalities when generating CC data. The task is to provide A data block (10) is divided into a plurality of data strings (20a, 20b, ...). The parity bits (P) 30a, 30b,... For detecting data abnormality are added to the divided data strings 20a, 20b,. Further, in order to correct the data abnormality of the entire data block 10, ECC data 40 is added to the data block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data structure of memory data and an error correction method suitable for application to, for example, a memory chip used in an information processing apparatus, or another memory device, or a device having a memory access mechanism. , And an error correction method.

[0002]

2. Description of the Related Art In a memory device such as a flash memory, when a data error that cannot be normally written at the time of writing data or a data error that destroys data after data writing occurs, the written data is read. There is a disadvantage that the data to be output is different.

For this reason, a parity check means for adding a parity bit to the write data to detect a data error or an ECC data (Error Correction Code) to the write data in a block unit to detect and correct the data error. ECC (Error Checking and Cor
It is necessary to confirm that the read data is normal by providing means and the like.

The parity check method described above is a method in which a parity bit is added to data that can be handled in one read operation, and the data is recorded, and when data is read, a data abnormality is detected (parity check). is there.

In this parity check method, since data abnormality can be determined each time data is read, there is no need to prepare a buffer for storing data, and there is no need for a complicated circuit for detecting data abnormality. On the other hand, however, there is a problem that data abnormalities cannot be corrected.

In the ECC data system, memory data is divided into block units, and the block data
C data is added and recorded. After reading the data in block units, the ECC data generated from the data is compared with the ECC data generated and recorded at the time of writing to detect a data abnormality and specify a data abnormality location. It is possible to correct the data abnormal part based on these information.

However, the ECC data method is
Only after reading the data of one block, the data abnormality can be determined. In addition, there is a problem that a buffer for storing one block of data is required to correct the data abnormality.

When the data size of one block is reduced, a buffer for storing data may be small, but there is a problem that the amount of ECC data added to memory data increases.

[0009]

As described above, in order to avoid the inconvenience that the written data and the data to be read are different from each other, the parity check method is used when confirming that the read data is normal. In this case, since data abnormality can be determined every time data is read, there is no need to prepare a buffer for storing data, and there is an advantage that a complicated circuit for detecting data abnormality is not required, but data There was a problem that the abnormality could not be corrected. In the above ECC data system,
While it is possible to correct data abnormalities,
There is a problem that a data abnormality cannot be determined until data of one block is read out, and a buffer for storing data of one block is required to correct the data abnormality. Further, when the data size of one block is reduced, the buffer for storing data can be small, but the EC added to the memory data can be reduced.
There is a problem that the data amount of C becomes large.

The present invention has been made in view of the above circumstances,
Provided are a data structure of memory data, an error correction method, and an error correction method that can reduce the size of a buffer for storing data and reduce the amount of data added to detect and correct data abnormalities. The purpose is to:

[0011]

According to the present invention, in a data structure of memory data, ECC data for correcting data abnormality of the entire data block is added to data in block units, and the data block is added to the data block. It is characterized in that it is divided into a plurality of data strings, and a parity bit for detecting data abnormality is added to each data string.

Further, according to the present invention, in an error correction method for memory data, ECC data for correcting data abnormality of the entire data block is generated and added to a data block to be written, The data block is divided into a plurality of data strings, and a parity bit for data abnormality detection is generated and added to each of the data strings. At the time of reading the data block, a parity check is performed for each data string, and an error When there is no data, the data string is transferred and output as read data. When an error occurs, the data string is temporarily saved in a buffer area, ECC data is generated from a read data block including the data string, and an error is generated. After the correction, the data is transferred and output as read data.

According to the present invention, in an error correction method for memory data, at the time of data writing, ECC data for correcting data abnormality of the entire data block is generated and added to a data block to be written. , The data block is divided into a plurality of data strings,
Processing means for generating and adding a parity bit for data abnormality detection to each of the data strings, and performing a parity check for each data string of the data block at the time of reading the data block so that no parity error occurs Processing means for outputting the data string as read data, and saving the data string to a buffer area when a parity error occurs, generating ECC data of a read data block including the data string, and correcting the error. After that, a parity check is performed on the data string remaining at the head of the data string, and processing means for outputting the data string as read data when no parity error occurs is provided.

According to another aspect of the present invention, there is provided an ECC circuit for generating and adding, to a data block to be written, ECC data for correcting data abnormality of the entire data block in a data write operation in a memory device. And a parity circuit that divides the data block into a plurality of data strings, generates and adds a parity bit for data abnormality detection to each data string, and a parity check that occurs according to the parity bit. A data buffer having a data size of one data string for holding the data string, and saving the data string to the data buffer when the parity error occurs, and reading the ECC data from the read data block including the data string. Means for generating, correcting and outputting an error.

Further, according to the present invention, in a memory device, at the time of writing data, ECC data for correcting data abnormality of the entire data block is added to a data block to be written, and Means for dividing the block into a plurality of data strings and adding a parity bit for detecting data abnormality to each data string, and a parity check for each data string of the data block when reading the data block Means for outputting the data string as read data when a parity error does not occur, and saving the data string to a buffer area when a parity error occurs, and reading the ECC data of a read data block including the data string. After the error is corrected and the data string is Performs I check, characterized by comprising and means for outputting the data string as read data when causing no parity error.

By applying the present invention described above, a buffer size corresponding to a data string may be prepared as a buffer for storing data, so that the size of the buffer for storing data can be reduced, and data abnormality can be detected. In addition, the amount of data added to perform the correction can be reduced. Further, since the size of the buffer for storing data can be reduced, an error correction function can be added as an internal circuit to a memory element which has been difficult in the past.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a data structure of memory data according to the embodiment of the present invention. The data applied in the present invention is composed of a plurality of data blocks.

One data block 10 includes a plurality of data strings (here, for example, four data strings (1),
(Showing (2), (3), (4)) 20a, 20b, 20
c, 20d.

The divided data strings 20a, 20b,
Parity bits (P) 30a, 30b, 30c, 30d for detecting data anomalies are added to 20c, 20d, respectively.

Further, in order to correct the data abnormality of the entire data block 10, ECC data 40 is added to the data block. FIG. 2 is a diagram for explaining an operation procedure of the error correction processing in the embodiment.

Here, the second data string (2) 20b
Indicates a data block in which data is abnormal. When reading this data, error correction is performed according to the following processing procedure.

(A). First data string (1) 20a
Is determined to be normal by the parity bit 30a. The data string (1) 20a is transferred as normal read data.

(B). Second data string (2) 20b
Is determined to be abnormal by the parity bit 30b. The data string (2) 20b is stored in a data buffer (see reference numeral 35 in FIG. 3).

(C). Third data string (3) 20c,
Then, the fourth data string (4) 20d is read, and ECC data of the entire data block 10 in which the data string (2) 20b has an error is generated. At this time, all data strings (4) 20a to 20 of one data block 10
d sequentially passes through the ECC circuit (see reference numeral 33 in FIG. 3), whereby E of the entire read data block 10 is changed.
CC data is generated. Following this data block 10, ECC data 40 added to the data block
Is read.

The ECC data generated from the entirety of the read data block 10 is compared with the read ECC data 40 added at the time of writing the data block 10 to determine a data location where a data abnormality has occurred. Identify.

(D). Data string (2) stored in the data buffer (see 35 in FIG. 3) in (b) above
Correct the data abnormal part of 20b. The data string (2) 20b is transferred as normal read data.

(E). Third data string (3) 20c,
The fourth data string (4) 20d is transferred as normal read data. FIG. 3 is a block diagram showing a hardware configuration of the embodiment.

In FIG. 3, reference numeral 31 denotes a CPU for controlling the system, and 32 denotes a memory bus. Reference numerals 33 to 35 are components provided in the memory controller to realize a function of detecting and correcting a data abnormality.
3 is an ECC circuit, 34 is a parity circuit, and 35 is a data buffer.

The ECC circuit 33 adds the ECC data 40 to the data block 10 to be written in FIG. 1 in order to correct the data abnormality of the entire data block.

Further, the ECC circuit 33 is provided in the above-mentioned FIG.
In (d), an error is determined by the parity bit 30b, and an error bit of the data string (2) 20b stored in the data buffer 35 is specified, and the relevant part is corrected.

The parity circuit 34 in FIG.
Divided data strings 20a, 20b, 20c, 20d
Are added with parity bits (P) 30a, 30b, 30c, and 30d for detecting data anomalies, respectively.

The parity circuit 34 is provided in the above-mentioned FIG.
In (a) and (b), a parity check is performed using the parity bit (P). The data buffer 35 holds the data string having a parity error in the parity check until it is transferred after error correction. At this time, conventionally, as described above, a data buffer for one block (a buffer size including a reference numeral 35 shown by a broken line in FIG. 3) is required to correct the data abnormality.
In the above embodiment, 1
The buffer size may be equivalent to the data string 20i.

As described above, according to the embodiment of the present invention,
The size of the data buffer can be reduced (in the embodiment, it can be reduced to 1/4), and the capacity of additional data required for correcting a data abnormality can be reduced.

Also, by applying the above-described embodiment of the present invention to, for example, a memory chip, the size of a data buffer is reduced, and a function logic for detecting and correcting a data abnormality according to the present invention in a vacant area thereof. Can be placed.

[0035]

As described above in detail, according to the present invention, when realizing the function of detecting and correcting memory data abnormalities, it is possible to reduce the size of a buffer for storing data and to detect data abnormalities. In addition, the amount of data added to perform the correction can be reduced. Further, since the size of the buffer for storing data can be reduced, an error correction function can be added as an internal circuit to a memory element which has been difficult in the past.

That is, according to the present invention, ECC data for correcting the data abnormality of the entire data block is added to the data in block units, and the data block is divided into a plurality of data strings, By using a data structure of memory data in which a parity bit for detecting data abnormality is added to a data string, the size of a buffer for storing data can be reduced when ECC data is generated during data block transfer. In addition to this, the amount of data added for detecting and correcting data abnormalities can be reduced.

According to the present invention, in a memory data error correction method, ECC data for correcting data abnormality of the entire data block is generated and added to a data block to be written. Divides the data block into a plurality of data strings, generates and adds a parity bit for data abnormality detection to each data string, and performs a parity check for each data string when reading the data block. When there is no error, the data string is transferred and output as read data. When an error occurs, the data string is temporarily saved in a buffer area, and ECC data is generated from the read data block including the data string. After correcting the error, the method of transferring and outputting as read data is adopted, There are, in generating the ECC data, it is possible to reduce the size of the buffer to store the data, it is possible to reduce the amount of data to be added to perform the detection and correction of data error.

According to the present invention, in an error correction method for memory data, when data is written, ECC data for correcting data abnormality of the entire data block is generated and added to a data block to be written. Processing means for dividing the data block into a plurality of data strings, generating and adding a parity bit for data abnormality detection to each data string, and reading the data block when reading the data block. Processing means for performing a parity check for each of the data strings, and outputting the data string as read data when a parity error does not occur, and saving the data string to a buffer area when a parity error occurs, and After generating the ECC data of the read data block including the column and correcting the error, A parity check is performed on the data string remaining at the top of the data string, and processing means for outputting the data string as read data when a parity error does not occur is provided. When ECC data is generated, the size of a buffer for storing data can be reduced, and the amount of data added to detect and correct data abnormalities can be reduced.

According to the present invention, in a memory device, at the time of data writing, ECC data for correcting data abnormality of the entire data block is generated and added to a data block to be written. An ECC circuit, a parity circuit that divides the data block into a plurality of data strings, and generates and adds a parity bit for data abnormality detection to each of the data strings, and a parity error generated by a parity check according to the parity bits A data buffer having a data size of one data string for holding the data string, and saving the data string to the data buffer when the parity error occurs, from a read data block including the data string. Means for generating ECC data, correcting errors, and outputting the ECC data. Accordingly, the data because it can reduce the size of the buffer to store the can be added an error correction function as an internal circuit in the prior art which was difficult memory device.

According to the present invention, in a memory device, at the time of data writing, ECC data for correcting data abnormality of the entire data block is added to a data block to be written, Means for dividing the data block into a plurality of data strings, adding a parity bit for data abnormality detection to each data string, and reading the data block;
Means for performing a parity check for each data string of the data block, outputting the data string as read data when no parity error occurs, and saving the data string to a buffer area when a parity error occurs, E of the read data block containing the data string
Means for generating CC data, correcting the error, performing a parity check on the data string remaining at the head of the data string, and outputting the data string as read data when no parity error occurs. By doing so, the size of the buffer for storing data can be reduced, so that an error correction function can be added as an internal circuit to a memory element that has been difficult in the past.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of memory data according to an embodiment of the present invention.

FIG. 2 is a view for explaining an operation procedure of an error correction process in the embodiment.

FIG. 3 is a block diagram showing a hardware configuration of the embodiment.

[Description of Signs] 10 data block, 20 (ad) data string, 30 (ad) parity bit (P), 40 ECC data, 31 CPU, 32 memory bus, 33 ECC Circuit 34 parity circuit 35 data buffer

Claims (5)

[Claims] An ECC data for correcting a data abnormality of the entire data block is added to data in a block unit, and the data block is divided into a plurality of data columns, and a data abnormality is detected in each of the data columns. A data structure characterized by adding a parity bit for the data. 2. Generating and adding ECC data for correcting data abnormality of the entire data block to a data block to be written, dividing the data block into a plurality of data strings, and A parity bit for detecting data abnormality is generated and added to the data string, and a parity check is performed for each data string when reading the data block, and when there is no error, the data string is transferred and output as read data. When an error occurs, the data string is temporarily saved in a buffer area, ECC data is generated from a read data block including the data string, the error is corrected, and the data is transferred and output as read data. Error correction method for memory data. 3. At the time of data writing, ECC data for correcting data abnormality of the entire data block is generated and added to a data block to be written, and the data block is divided into a plurality of data strings. Processing means for generating and adding a parity bit for data abnormality detection to each data string; and performing a parity check for each data string of the data block at the time of reading the data block, thereby obtaining a parity error. Processing means for outputting the data string as read data when no error occurs, and saving the data string in a buffer area when a parity error occurs, and generating ECC data of a read data block including the data string. After correcting the error, the parity check of the data string remaining at the top of the data string The performed, memory data error correction method characterized by comprising comprises a processing means for outputting the data string as read data when causing no parity error. 4. An ECC circuit for generating and adding ECC data for correcting data abnormality of the entire data block to a data block to be written at the time of data writing; And a parity circuit for generating and adding a parity bit for data abnormality detection to each of the data strings; and a parity row for holding the data string when a parity error occurs in a parity check according to the parity bit. A data buffer having a data size of, and a means for saving the data sequence in the data buffer when the parity error occurs, generating ECC data from a read data block including the data sequence, correcting the error, and outputting the ECC data. A memory device comprising: 5. At the time of data writing, ECC data for correcting data abnormality of the entire data block is added to a data block to be written, and the data block is divided into a plurality of data strings. Means for adding a parity bit for data abnormality detection to each data string; and performing a parity check for each data string of the data block at the time of reading the data block. Means for outputting a data string as read data, and when a parity error occurs, the data string is saved in a buffer area, ECC data of a read data block including the data string is generated, and the error is corrected. A parity check is performed on the data string remaining at the beginning of the data string, and parity check is performed. Memory device characterized by comprising and means for outputting the data string as read data when causing no over.