JPH1098101A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique, which is a self-align contact forming technique using a mask pattern as an etching stopper, for manufacturing a desirable semiconductor device even when a space between adjacent gate electrodes is made smaller. SOLUTION: A gate-insulating film 15 and gate electrodes 17 are formed on a semiconductor substrate 11. A side wall film 23 is formed on the side wall of the gate electrode 17. A diffusion layer is formed on a semiconductor substrate, where the formation of the side wall film 23 has been completed. After the diffusion layer has been formed, the side wall film 23 is removed by a specified amount, so as to widen a space dimension between the adjacent gate electrodes. After the removal of a specified amount of the wide wall film 23 has been completed, a mask pattern 25 is formed on the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a feature in a step of forming a contact hole.

[0002]

2. Description of the Related Art As one of manufacturing methods for further increasing the degree of integration of a semiconductor device, there is a method described below with reference to FIG. In this method, first, an inter-element isolation insulating film 13 and a gate insulating film 15 are formed on a silicon substrate 11, and a stacked body 21 including a gate electrode 17 and an insulating film 19 provided on the upper surface thereof is formed. Next, impurity ions are implanted into the silicon substrate portions on both sides of the laminate 21,
A diffusion layer (not shown) having a low impurity concentration is formed. Next, an insulating sidewall film 23 is formed on the sidewall of the stacked body 21. Next, impurity ions are implanted into silicon substrate 11 again to form a diffusion layer (not shown) having a high impurity concentration. Next, a contact hole is formed by the following characteristic technique (herein referred to as "self-aligned contact technique"). That is, for example, a nitride film pattern 25 is formed as a mask pattern 25 having high resistance to etching means when forming a later contact hole over the gate electrode 17 and over the silicon substrate portion between the adjacent gate electrodes 17. 6 (A)). In FIG. 6A, a P portion is a gate electrode structure portion reaching another transistor in the integrated circuit, that is, an adjacent gate electrode, and 27 is a thermal oxide film. Next, for example, a BPSG film 29 is formed as an interlayer insulating film 29 on the sample. Next, a resist pattern 31 for forming a contact hole is formed on interlayer insulating film 29 (FIG. 6).
(B)). Then, in the first step, the BPSG film 29 is etched using the nitride film pattern 25 as a stopper under the condition of high BPSG / nitride film selectivity (FIG. 6).
(C)). As a second step, the nitride film 25 and the thermal oxide film 27 at the bottom of the contact hole are removed under the condition that the etching rate difference between the nitride film and SiO ₂ is small and the etching rate of Si is small, and a contact hole (not shown) is formed. You. Thereafter, arbitrary components such as a storage node are formed. According to this method, a part of the contact hole can be overlapped on the gate electrode. Therefore, the distance between the adjacent gate electrodes can be reduced by that much, so that high integration of the semiconductor device can be achieved.

[0003]

However, according to the above-mentioned prior art, when the distance between adjacent gate electrodes is further reduced due to the higher integration of the semiconductor device, it is difficult to form a contact hole for the following reasons. become.

As shown in FIG. 7A, as the distance d between adjacent ends of adjacent gate electrodes is reduced, the opening size between adjacent gate electrodes (actually, the width of the adjacent side wall film 2 is reduced).
3 interval between) W ₁ becomes narrow. The smaller the opening dimension W ₁ , the smaller the nitride film pattern 2 used as an etching stopper
5 is buried in a thick film between adjacent gate electrodes. Then, when the BPSG film 29 is etched using the nitride film pattern 25 as a stopper in a first step in an etching process for forming a contact hole, a thick nitride film remains at the bottom (FIG. 7B). Therefore, in the next second step, it is necessary to perform etching for a long time to completely remove the nitride film 25 and the thermal oxide film 27 at the bottom. As a result, the insulating film 19 on the gate electrode 17 is also etched, so that the shoulder 17a of the gate electrode 17 is exposed (FIG. 7C). Shoulder 17
If a storage node is formed in the contact hole where a is exposed, it short-circuits with the gate electrode 17.

As a countermeasure against the above problem, the nitride film pattern 25
It is also conceivable to reduce the extent to which the nitride film pattern 25 is buried between the gate electrodes by setting the film thickness to be small. However, when the thickness of the nitride film pattern 25 is reduced, a higher selectivity is required in the first step of the etching process for forming the contact hole, and an expensive etching apparatus is required. In addition, in the case of etching with high selectivity, the amount of plasma reaction products generated is large and the frequency of maintenance of the apparatus is increased, so that the process stability is reduced.

There is a demand for a method that can apply the self-aligned contact technique even when the distance between adjacent gate electrodes becomes narrow.

[0007]

Therefore, according to the present invention, there is provided a step of forming a gate electrode, a step of forming an insulating side wall film on a side wall of the gate electrode, and a step of forming the gate electrode after forming the side wall film. Forming a mask pattern having high resistance to etching means when forming a contact hole later over the semiconductor substrate portion above the electrode and between adjacent gate electrodes; and forming an interlayer on the semiconductor substrate on which the mask pattern has been formed. Forming an insulating film, forming the contact hole in the interlayer insulating film by a method that allows a part of the contact hole to overlap the gate electrode, and forming the mask pattern portion in the formed contact hole. Removing the adjacent gate electrodes before the step of forming the mask pattern. Removing a predetermined amount of said side wall film to broaden the size opening between, characterized in that comprises. However, the step of removing a predetermined amount of the sidewall film may be a step of removing the entire sidewall film.

In practicing the present invention, it is preferable to provide a step of forming an insulating film on the upper surface of the gate electrode before the step of forming a mask pattern.

According to the present invention, the opening dimension between adjacent gate electrodes is increased by removing a predetermined amount of the side wall film. Therefore, the opening size between the gate electrodes can be widened while the interval between the adjacent gate electrodes remains small. Then, a mask pattern is formed on the wafer in such a state. Therefore, the extent to which the mask pattern is buried between the adjacent gate electrodes is reduced as compared with the case where the predetermined amount of the sidewall film is not removed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.
However, the drawings used in this description merely schematically show the dimensions, shapes and arrangements of the components so that the present invention can be understood. In each figure, the same components as those in FIG. 7 are denoted by the same symbols as those used in FIG. 7, and the description thereof may be omitted.

1. First Embodiment First, a first embodiment will be described with reference to FIGS. Note that this manufacturing process diagram is a cross-sectional view (a cross-sectional view focusing on a cut) obtained by cutting the sample in the main process along the gate length direction.

First, as shown in FIG. 1A, an isolation insulating film 13 is formed on a silicon substrate 11 by a known method, and further a gate insulating film 15 is formed. Next, on the silicon substrate on which the gate insulating film 15 has been formed,
For example, a polysilicon film and a CVD oxide film (both not shown) are formed in this order as a thin film for forming a gate electrode. Next, the polysilicon film and the CVD oxide film are patterned into a shape of a gate electrode. Thus, a stacked body 21 including the gate electrode 17 and the upper surface insulating film 19 remaining thereon is obtained. In order to form a low impurity concentration layer (not shown) for obtaining an LDD structure, impurity ions are implanted into the silicon substrate on which the stacked body 21 has been formed. Next, on the silicon substrate, for example, a CVD oxide film is formed as an insulating film for forming a side wall film (not shown), and thereafter, the CVD oxide film is removed by, for example, anisotropic etching to form the stacked body 21. A sidewall film 23 is formed on the sidewall.
Next, an oxide film 27 is formed on the exposed portion of the silicon substrate 11 by thermal oxidation. Next, a high impurity concentration layer (not shown)
Is formed, impurity ions are implanted into the sample. Thus, the structure shown in FIG. 1A is obtained. However, here, it is assumed that the distance d between the adjacent gate electrodes has a small dimension for high integration. Therefore, in the structure shown in this FIG. 1 (A), the dimension W ₁ open between the adjacent gate electrodes is in a narrow size. Here, the narrow dimension W _1, is dimensioned so that the mask pattern 25 will be embedded in the thick film between the gate electrodes adjacent to be formed later. Specifically, the dimension W ₁ open between the adjacent gate electrodes was 200nm, for example. If the dimension W ₁ of opening of the degree, to form a mask pattern 25 having a thickness of about 100nm in the next step gate it is thus embedded by the mask pattern 25.

Therefore, in order to widen the opening dimension between adjacent gate electrodes, a predetermined amount of the sidewall film 23 is removed. This is etched using, for example, an aqueous solution of hydrofluoric acid having a concentration of 1% (volume%) or less (hereinafter abbreviated as hydrofluoric acid) to a thickness of, for example, a CVD oxide film of 60 nm. As a result, the opening size between the adjacent gate electrodes can be increased to W ₂ (W ₁ <W ₂ ), in this case, to 320 nm (FIG. 1B). The reason why hydrofluoric acid having a concentration of 1% or less is used is that the concentration of the hydrofluoric acid is less than the film thickness Δt of the inter-element isolation insulating film (thermal oxide film) 13 (see FIG. 1B). 23 (CVD oxide film) can be etched at about six times the speed. Therefore, the side wall film 23 is
Film thickness Δ of insulating film 12 for element isolation during etching
Since t can be as small as about 10 nm, the influence on the device characteristics can be ignored. The inventor of the present application has confirmed that such selective etching is possible for at least 0.3% hydrofluoric acid. However, it is considered that hydrofluoric acid with a slightly lower concentration, for example, about 0.1% can be used.

Next, a mask pattern 25 having high resistance to etching means for forming a contact hole later is formed on at least a portion of the wafer corresponding to a region where a contact hole is to be formed. Here, a nitride film pattern 25 having a thickness of, for example, 100 nm is formed by a known technique as a mask pattern. Since the sidewall film 23 is etched by a thickness of 60 nm in the previous step, the opening dimension between the adjacent gate electrodes is increased to the expanded dimension W _2, that is, 320.
Since the thickness is on the order of nm, the nitride film pattern 25 does not increase in thickness between the adjacent gate electrodes (FIG. 1C). Therefore, thereafter, a contact hole can be formed by applying the conventional self-aligned contact technology. This will be described briefly.

A nitride film pattern 2 as a mask pattern
A BPSG (Boro-Phosph Silicate glass) film 29 having a predetermined thickness, for example, is formed as an interlayer insulating film on the wafer on which the film 5 is formed. Next, the BPSG film is flattened by high-temperature flow processing. Thereafter, a resist pattern 31 for forming a contact hole is formed on the BPSG film 29 (FIG. 2A). Next, as a first step for forming a contact hole, the BPSG film 29 is etched using the nitride film pattern 25 as a stopper under conditions of high BPSG / nitride film selectivity (FIG. 2B). Next, as a second step, the contact hole 33 is formed by etching the nitride film 25 and the thermal oxide film 27 at the bottom of the contact hole under the condition that the etching rate difference between the nitride film and SiO ₂ is small and the etching rate of Si is small (FIG. 2 (C)).

Next, after removing the resist pattern 31, a pattern 35 of, eg, a polysilicon film serving as a storage node, for example, is formed by a known film forming technique, lithography technique, and etching technique (FIG. 3A). next,
A capacitor dielectric film 37 is formed (FIG. 3B), and then a cell plate 39 serving as a counter electrode of the storage node 35 is formed by a known method. Thereby, a capacitor cell is formed. However, the structure formed after the formation of the contact hole is not limited to the capacitor cell, but may be any other desired structure.

The impurity ions implanted into the silicon substrate in the process described with reference to FIG.
A diffusion layer (not shown) for the drain is generated. The semiconductor device formed by the manufacturing method of the present invention is different from the semiconductor device manufactured by the conventional method described with reference to FIG. In this case, the degree of overlap with the bottom of the contact hole is different. That is, in the present invention, since the sidewall film is removed after the impurity ions are implanted, the plane area of the bottom of the contact hole is increased by the removal of the sidewall film.
Therefore, as shown in FIG.
Is more overlapped with the high impurity concentration portion 41a of the diffusion layer 41. Further, in some cases, the diffusion layer 41 is provided in the plane at the bottom of the contact hole.
In some cases (see FIG. 4B). In other words, the plane area at the bottom of the contact hole may be larger than the plane area of the high impurity concentration portion of the diffusion layer.
The semiconductor device manufactured in the second embodiment described later is such an example.

2. Second Embodiment Next, a second embodiment will be described with reference to FIG. Here, FIG. 5 is a main part process diagram for explaining the second embodiment.

In the above-described first embodiment, an example has been described in which the side wall film 23 is partially removed along the gate length direction. However, when it is desired to further increase the opening size between the gate electrodes after the sidewall film 23 is formed, or when the distance d between the gate electrodes is smaller than that in the first embodiment, the gap between the gate electrodes after the sidewall film 23 is formed. In the case where the opening dimension W ₁ becomes narrower than in the first embodiment, the opening dimension is expanded by removing the entire side wall film 23 (FIG. 5A,
(B)). Specifically, the dimension W ₁ open between the adjacent gate electrodes were for example 100nm or less. In this case as opening size W ₁ is narrow, the inter also gates as to form a nitride film pattern 25 as a mask pattern 25 for example with a thin film thickness of about 50nm in the next step will be embedded by the nitride film pattern 25. Further, if the thickness of the nitride film pattern 25 is too small, the problem described in the section of the problem already occurs. Therefore, the thickness of the nitride film pattern 25 is a certain thickness, but is not limited to at least 100 n.
I want to have a film thickness of about m.

Therefore, in the second embodiment, the side wall film 23 is completely removed (FIG. 5B). This is performed, for example, by using hydrofluoric acid having a concentration of 1% or less used in the first embodiment and extending the etching time. As a result, the opening size between the gate electrodes can be extended to about twice that of the side wall film 23. That is, in this case, the opening dimension is extended to the distance d between the adjacent gate electrodes. Then C
Since the etching rate of the VD oxide film with respect to the hydrofluoric acid is about six times the etching rate of the thermal oxide film, when the thickness of the sidewall film 23 made of the CVD oxide film is 150 nm, the insulating film for element isolation is used. 13 is about 25 nm, but the thermal oxide films 13 and 27 on the silicon substrate 11
If the initial value of is set large, the influence on the device characteristics can be suppressed.

In the case of the second embodiment, since the amount of removal of the side wall film 23 is large, the degree of removal of the upper surface insulating film 19 in the step of removing the side wall film 23 also increases. Therefore, if the upper insulating film 19 is formed of a CVD oxide film, it is preferable that the upper insulating film 19 has a larger thickness than that of the first embodiment. Alternatively, the upper insulating film 19 may be formed of a thermal oxide film obtained by thermally oxidizing the surface of the polysilicon gate 17. This is because, when the upper oxide film is formed by the thermal oxide film, the upper oxide film has higher resistance to hydrofluoric acid used in the step of removing the side wall film 23 than when the upper oxide film is formed by the CVD oxide film.

Next, a nitride film pattern 25 having a thickness of, for example, 100 nm is formed as the mask pattern 25. Since previous dimension W ₂ opened between gate for completely removing the side wall film 23 in the step is secured to or higher than 300 nm, does not occur that the thicker part of the gate electrode nitride film pattern 25 are adjacent to each other ( (FIG. 5 (C)).

Thereafter, an interlayer insulating film 29 and a resist pattern 31 are formed in the same procedure as in the first embodiment, a contact hole 33 is formed, and a storage node 3 is formed.
5 and the like may be formed.

In the case of the second embodiment, after the etching of the nitride film pattern 25 is completed, the nitride film remains on the side walls of the stacked body 21 (not shown). This nitride film remaining on the side wall of the stacked body 21 becomes an insulating film for electrically insulating the gate electrode 17 from the storage node.

In each of the first and second embodiments, the opening between the gate electrodes can be expanded by a simple process of etching the side wall film 23. Therefore, even if the interval between adjacent gate electrodes is reduced with the increase in integration, it is possible to easily suppress the mask pattern 25 from being buried between the gate electrodes thickly. Therefore, even if the distance between the gate electrodes becomes narrower due to the higher integration of the semiconductor device, the self-aligned contact technique can be applied to the manufacture thereof.

Although the embodiment of the method of manufacturing a semiconductor device according to the present invention has been described above, the present invention is not limited to the above-described embodiment.

In the above description, an example has been described in which the side wall film 23 is etched with a predetermined concentration of hydrofluoric acid in order to extend the opening dimension between the gate electrodes, but instead of hydrofluoric acid, ammonia, hydrogen peroxide and water are used. May be used.

In the above-described embodiment, the example in which the side wall film 23 is formed by the CVD oxide film has been described.
The constituent material 3 may be any other suitable material as long as it can be selectively removed from the thermal oxide film.

In the above description, an example is considered in which the side wall film is formed to obtain an LDD structure, but the side wall film is not limited to this. The present invention can be widely applied to a sidewall film formed on a sidewall of a gate electrode in a manufacturing process of a semiconductor device.

In the above-described embodiment, an example in which the gate electrode is formed of a polysilicon film has been described. However, the gate electrode may be formed of a refractory metal, silicide, or polycide. Configuration. The material for forming the mask pattern is not limited to the nitride film, but may be any other material that can be selectively etched. However, in the case of the second embodiment, it is assumed that the mask pattern forming material also has insulating properties.

[0031]

As is apparent from the above description, according to the present invention, the resistance to the etching means when a later contact hole is formed on the semiconductor substrate after the formation of the insulating film on the side wall of the gate electrode is completed. A step of forming a high mask pattern, a step of forming an interlayer insulating film on the semiconductor substrate on which the mask pattern has been formed, and that the contact hole partially overlaps the gate electrode in the interlayer insulating film. Forming a mask pattern by a method (self-aligned contact method) and removing the mask pattern portion in the formed contact hole. Removing a predetermined amount of the side wall film (including the case of completely removing the sidewall film) so as to widen an opening dimension between adjacent gate electrodes. , Comprising. Therefore, the size of the opening between the gate electrodes can be easily widened while keeping the distance between the adjacent gate electrodes small. Therefore, the extent to which the mask pattern is buried between the adjacent gate electrodes is reduced as compared with the case where the predetermined amount of the sidewall film is not removed. Therefore, the self-aligned contact technique using a mask pattern can be applied to the manufacture of a semiconductor device having a smaller gate electrode interval.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram for explaining a manufacturing method according to a first embodiment.

FIG. 2 is a manufacturing process diagram for explaining the manufacturing method according to the first embodiment, following FIG. 1;

FIG. 3 is a manufacturing step diagram for explaining the manufacturing method according to the first embodiment, following FIG. 2;

FIGS. 4A and 4B are diagrams illustrating characteristic structural portions of a semiconductor device manufactured by the manufacturing method of the present invention.

FIG. 5 is a main part process view for describing the manufacturing method of the second embodiment.

FIG. 6 is an explanatory diagram of a conventional technique.

FIG. 7 is a diagram for explaining a problem.

[Explanation of symbols]

 11: Silicon substrate 13: Insulating film for element isolation 15: Gate insulating film 17: Gate electrode 19: Upper surface insulating film 21: Stack 23: Side wall film 25: Mask pattern 27: Thermal oxide film 29: Interlayer insulating film 31: Contact hole forming resist pattern 33: Contact hole 35: Storage node 37: Dielectric film for capacitor 39: Cell plate 41: Diffusion layer 41a: High impurity concentration portion of diffusion layer

Claims (2)

[Claims] A step of forming a gate electrode, a step of forming an insulating side wall film on a side wall of the gate electrode, and a step of forming a semiconductor substrate on the gate electrode and between adjacent gate electrodes after forming the side wall film. Forming a mask pattern having high resistance to etching means when forming a later contact hole over the portion; forming an interlayer insulating film on the semiconductor substrate on which the mask pattern has been formed; A method of manufacturing a semiconductor device, comprising: forming a contact hole in a film by a method allowing a part of the contact hole to overlap the gate electrode; and removing the mask pattern portion in the formed contact hole. In the method, before the step of forming the mask pattern, the side wall film is formed in order to increase an opening dimension between adjacent gate electrodes. The method of manufacturing a semiconductor device, characterized in that it comprises the steps of a predetermined amount is removed (although there may be a case to remove any side wall film.). 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of removing the side wall film, the entire side wall film is removed, and the mask pattern is formed of a material having an insulating property. A method of manufacturing a semiconductor device, comprising: removing a portion of the mask pattern on a side wall of the gate electrode when removing the mask pattern portion;