JPH1098149A - Semiconductor package - Google Patents

Abstract

(57) [PROBLEMS] To provide a semiconductor package having a super multi-pin structure capable of more stably connecting a ground line or a power supply line from a package mounting substrate to an electrode pad of a semiconductor chip. SOLUTION: A semiconductor chip 2 having a plurality of electrode pads 3 on the chip surface and arranged inside a conductive outer ring 1, a film circuit 5 arranged and formed on the chip surface side, and a film circuit 5 on the chip surface side A plurality of external connection terminals 8, a first lead 9 electrically connecting the electrode pads 3 and the external connection terminals 8, an electrode pad 3a for ground or power supply, and the outer ring 1. A second lead 11 electrically connected to the outer ring 1 and an external connection terminal 8a for ground or power and the third lead 11 electrically connected to the outer ring 1.
And a conductive stage 14 joined to the chip back surface and the outer ring 1 via conductive adhesive layers 13a and 13b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package having a super lead structure by joining a semiconductor chip to a novel lead frame.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional semiconductor package that can be mounted on a printed wiring board or the like via an organic substrate having external connection terminals such as solder balls. In FIG. 5, a semiconductor chip 51 is mounted on the surface of a multi-layer organic wiring substrate 50 of about 2 to 6 layers using an organic material. The electrode pads of the semiconductor chip 51 and the wiring film 52 formed on the surface of the multilayer organic wiring substrate 50 are connected by wire bonding using gold wires 53 or the like.

A solder ball (external connection terminal) 55 that is electrically connected to the wiring film 52 on the front surface through a through hole 54 is provided on the back surface of the multilayer organic wiring board 50. It faces outside from the opening of the solder resist film 56. The semiconductor chip 51 is sealed together with the gold wire 53 by a sealing resin 57.

[0004] In the semiconductor package 58 having the above structure, the solder balls 55 formed on the back surface are connected to the printed wiring board 59. Further, the multilayer organic wiring board 50 is often called a ball grid array (BGA) because a large number of solder balls 55 are arranged in a grid pattern. It is called a BGA package.

[0005]

However, in the above-mentioned conventional semiconductor package 58, since the electrode pads of the semiconductor chip 51 and the wiring film 52 of the multilayer organic wiring substrate 50 are connected by wire bonding, the wiring pitch is reduced. There was a limit to reducing the size of Also, in the case of a semiconductor package called TCP (tape carrier package), since the metal layer attached to the insulating film is etched to form the lead, there is a restriction such as thinning of the lead due to side etching. Multi-pin had limitations.

Therefore, the present applicant has already proposed a semiconductor package having a super multi-pin structure by joining a novel lead frame structure and a semiconductor chip. FIG. 6 is a side sectional view showing an example of a semiconductor package having a super multi-pin structure. In FIG. 6, a semiconductor chip 62 is arranged inside an outer ring 61. On the surface of the semiconductor chip 62, a plurality of electrode pads 63 are formed over the periphery thereof. A film circuit 65 is provided at the center of the chip surface excluding the pad formation region via an adhesive layer 64.
Is mounted and fixed. The film circuit 65 includes an insulating film 66 serving as a base and the insulating film 6.
6 and a lead pattern 67 formed in the inside. Further, on the film circuit 65, an external connection terminal (solder ball) 68 is provided at the end of each lead pattern 67. Further, a lead 69 extends from the film circuit 65 in a form in which the lead pattern 7 is extended, and a leading end 69a of the lead 69 is connected to the electrode pad 63 on the chip surface. The space between the semiconductor chip 62, the adhesive layer 64, the film circuit 65 and the outer ring 61 is filled with a sealing resin 70.

In the semiconductor package having the above configuration,
Lead pattern 6 of film circuit 65 including lead 69
7 is formed by electrolytic plating using a metal base (not shown), and external connection terminals 69 are also formed on the lead pattern 67 by electrolytic plating. Has been realized. In addition, since a part of the metal base is left as the outer ring 61 and the outer shape of the package is formed by the outer ring 61, the positional accuracy between the outer shape of the package and the external connection terminals 68 is ensured. Alignment during mounting can be easily performed. Further, a so-called CSP (chip size package) structure in which the package size is kept at the same level as the chip size has also been realized.

In the semiconductor package shown in FIG. 6, a ground (GND) line or a power supply line of a printed wiring board for mounting a package (hereinafter, referred to as a package mounting board) is connected from a predetermined external connection terminal 68 to a lead pattern 67. Through the electrode pads 63 of the semiconductor chip 62
However, depending on the signal to be handled, the potential of the power supply or the ground may be unstable, and improvement thereof has been desired.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to connect a ground line or a power supply line from a package mounting board to an electrode pad of a semiconductor chip in a more stable manner. It is an object of the present invention to provide a semiconductor package having a super multi-pin structure.

[0010]

In a semiconductor package according to the present invention, a semiconductor chip having a plurality of electrode pads on a peripheral portion of a chip surface and arranged inside a conductive outer ring is provided. The film circuit disposed on the front surface side, a plurality of external connection terminals protrudingly formed on the film circuit, the electrode pads formed on the semiconductor chip, and the external connection terminals formed on the film circuit are electrically connected. Lead, which is electrically connected, and a second lead, which is an electrical connection between the ground or power supply electrode pad and the outer ring of the plurality of electrode pads formed on the semiconductor chip. A third lead electrically connecting the external connection terminal for ground or power supply to the external ring among a plurality of external connection terminals formed on the film circuit; and a semiconductor chip. Respectively to the back surface and outer ring-flop via the conductive adhesive layer has a configuration in which a bonded conductive stage.

In the semiconductor package having the above structure, the ground or power supply electrode pad is short-circuited to the back surface of the chip via the second lead, the outer ring and the conductive stage. Is short-circuited to the back surface of the chip via the third lead, the outer ring and the conductive stage. As a result, the back surface of the chip serves as a common ground or power supply, and the outer ring connected to the back surface of the chip and the conductive stage have the same potential, so that the ground line or the power supply line from the package mounting substrate can be more stably formed. Can be connected to the electrode pad.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a side sectional view showing an embodiment of a semiconductor package according to the present invention, and FIG. 2 is a plan view thereof. 1 and 2, a semiconductor chip 2 is arranged inside an outer ring 1 having a laminated structure. A plurality of electrode pads 3 are formed on the surface (upper surface in the figure) of the semiconductor chip 2 over the periphery thereof. A film circuit 5 is mounted and fixed at the center of the chip surface excluding the pad formation region via an adhesive layer 4 made of an adhesive sheet or the like. The film circuit 5 includes an insulating film 6 serving as a base and a lead pattern 7 formed in the insulating film 6. Further, a small hole is provided on the film circuit 5 at the end of each of the lead patterns 7, and an external connection terminal 8 protrudes through the small hole. The above-mentioned adhesive layer 4 has an appropriate elasticity, and thus, besides bonding the components to each other, the adhesive layer 4 also serves as a cushioning material for protecting the element formation region existing inside the pad formation region of the semiconductor chip 2. It also has a role.

The insulating film 6 serving as a base of the film circuit 5 has a substantially rectangular shape in plan view, and a plurality of leads (hereinafter, referred to as first leads) 9 extend from four sides thereof. Suspended leads 10 extend from the four corners.
On the other hand, from the outer ring 1, the first lead 9
The second lead 11 and the third lead 12 extend in parallel to the first and second leads. Among them, the first lead 9 is a lead in the insulating film 6 for electrically connecting the electrode pad 3 formed on the semiconductor chip 2 and the external connection terminal 8 formed on the film circuit 5. The pattern 7 extends outward from the film in an extended manner, and the lead end 9 a of the lead 7 is connected to the electrode pad 3 of the semiconductor chip 2. On the other hand, the second lead 11 is provided on the inner peripheral edge of the outer ring 1 to electrically connect the ground electrode pad 3 a and the outer ring 1 among the plurality of electrode pads 3 formed on the semiconductor chip 2. , And extends toward the insulating film 6, and the lead end 12a is connected to the ground electrode pad 3a. Further, the third lead 12 is connected to the film circuit 5.
Of the plurality of external connection terminals 8 formed above, the external connection terminal 8a for grounding and the external ring 1 are bridged between the insulating film 6 and the external ring 1 so as to be electrically connected. .

In addition, on the back surfaces of the outer ring 1 and the semiconductor chip 2, conductive adhesive layers 13a and 13b are provided, respectively.
The conductive stage 14 is joined via the. The conductive adhesive layers 13a and 13b are formed by a conductive adhesive, a conductive paste, a conductive adhesive tape, or the like. On the other hand, the conductive stage 14 is made of a conductive material such as copper, aluminum or the like, and has a substantially concave cross-section in accordance with the step between the outer ring 1 and the semiconductor chip 2 in the illustrated example. For both the outer ring 1 and the semiconductor chip 2 to be joined, the outer peripheral upper end surface of the conductive stage 14 is connected to the outer ring 1 via the conductive adhesive layer 13a.
The bottom surface of the concave portion of the conductive stage 14 is bonded to the back surface of the semiconductor chip 2 via the conductive adhesive layer 13b. The conductive stage 14 serves not only to electrically connect the outer ring 1 and the back surface of the semiconductor chip 2 but also to enhance the strength of the entire semiconductor package, that is, to function as reinforcement.

Further, the electrode pads 3 of the semiconductor chip 2
In the area around the connection between (3a) and the first and second leads 9 and 12 (the area surrounded by the outer ring 1, the conductive stage 14, the semiconductor chip 2, the adhesive layer 4, and the film circuit 5), Sealing resin 15 such as epoxy resin or silicone resin
Is filled. An appropriate number of through holes 14a are formed in the bottom surface of the concave portion of the conductive stage 14 at the peripheral edge thereof. The through-holes 14a have a gas releasing function when the sealing resin 15 is injected or when the semiconductor package is mounted, and play a role of preventing sealing failure due to non-filling and reducing thermal stress.

Next, a method of manufacturing a semiconductor package according to the present invention will be described. First, as shown in FIG. 3A, a metal base 16 composed of a laminated plate having a three-layer structure is prepared. This metal base 16 forms an aluminum film 18 having a thickness of about 4.5 μm on the surface of a substrate (hereinafter, referred to as a copper substrate) 17 made of copper or a copper alloy having a thickness of about 150 μm, for example, by vapor deposition. A nickel film 19 of about 1 to 2 μm is formed.

The aluminum film 18 corresponds to an etching stop film for preventing the surface of the metal base 16 from being etched when the copper substrate 17 is etched in a subsequent step. On the other hand, the nickel film 19 corresponds to a copper plating base for forming a lead portion (described later) on the surface of the metal base 16, that is, a nickel base film. The metal base 16 is
Although it does not become a lead itself and is eventually cut away except for the outer ring portion, it is indispensable for forming a very fine lead.

As the metal base 16, for example, a chromium film having a thickness of about 0.5 μm is formed as an adhesion film between the aluminum film 18 and the nickel film 19 in order to enhance the adhesion between them. Is also good. Further, as the plating base film, a copper thin film may be formed instead of the nickel film 19.

Next, as shown in FIG. 3B, the lead portions 20a, 20b, 20c made of copper are formed on the surface of the metal base 16, that is, the surface of the nickel film 19 by selective plating.
Is patterned. Of these, the lead portion 20a is
In a portion corresponding to the lead pattern 7 and the first lead 9, a large number are formed so as to extend in four directions corresponding to the electrode pads 3 of the semiconductor chip 2. On the other hand, the lead portion 20b is a portion corresponding to the second lead 11, and is formed from a portion corresponding to the outer shape position of the outer shape ring 1 toward the center of a base partition region (described later). Further, the lead portion 20c is a portion corresponding to the third lead 12, and is formed from the portion corresponding to the outer position of the outer ring 1 to the patterning region of the lead portion 20a. Although not shown, the lead portion 20 described above is used.
The suspension leads 10 are formed by selective plating at the same time as a, 20b, and 20c.

Here, the selective plating is performed on the metal base 16.
Is selectively covered with a resist pattern or the like, and electrolytic plating is performed using the resist pattern as a mask. By selectively plating copper on the metal base 16 by the electrolytic plating method in this manner, the lead portions 20a, 20b, and 20 having a good film quality and a fine pattern are formed.
20c is obtained.

Next, as shown in FIG. 3C, a slit 21 for defining the partition area of the metal base 16 is formed by etching, and then, as shown in FIG. Except for (the part to be the first lead 9), the insulating film 6 having a thickness of, for example, about 40 μm is formed by patterning. At this time, a part of the lead portion 20c corresponding to the third lead 12 is also covered with the insulating film 6, and at this time, the film circuit 5 based on the insulating film 6 is obtained. Next, as shown in FIG. 3E, the lead portion 20 covered with the insulating film 6 is formed.
External connection terminals 8 made of, for example, solder balls are formed at the ends of the terminals a and 20c using the insulating film 6 as a mask. The external connection terminal 8 is formed by forming a base film made of a metal material such as copper, nickel, or gold at the end of the lead portion 20a exposed on the insulating film 6 by, for example, an electrolytic plating method. It is obtained by laminating a tin-lead alloy solder material thereon by electrolytic plating, and reflowing the solder material to form a ball shape.
At this time, an external connection terminal 8a for ground (see FIG. 2) is formed at the end of the lead portion 20c.

Subsequently, as shown in FIG. 3 (F), the copper substrate 17 of the metal base 16 is removed by selective etching while excluding the portion serving as the outer ring 1. In this etching, the aluminum film 18 acts as an etching stopper, and only the copper substrate 17 is removed.
Next, as shown in FIG. 3 (G), the aluminum film 18 of the metal base 16 is removed by selective etching, and the nickel film 19 is further removed by selective etching to make each lead portion 20a, 20b, 20c independent. . Note that FIG.
In the state (G), the film circuit 5 is represented as being separated from the external ring 1, but actually, the suspension lead 10 is shown.
(See FIG. 2). Then
As shown in FIG. 3H, a bump 22a made of aluminum is formed at the tip of a lead portion (a portion corresponding to the first lead 9) 20a extending from the insulating film 6 by, for example, a sputtering method or a vapor deposition method. Similarly, another lead portion (a portion corresponding to the second lead 11) 20
A bump 22b is also formed at the tip of b. At this point, the lead frame before mounting the semiconductor chip is completed.

Next, a manufacturing procedure for assembling the semiconductor chip to the lead frame will be described with reference to FIG. In FIG. 4, a lead portion 20c (third lead 1) not directly involved in assembling the semiconductor chip is used.
2) is omitted. First, as shown in FIG.
The semiconductor chip 2 is positioned and fixed on the lead pattern forming surface side of the film substrate 5 via the adhesive layer 4. At this time,
The lead portion 20 a extending from the insulating film 6, that is, the first lead 9, is connected to the bump 2 formed at the tip of the lead.
2 a faces the electrode pad 3 on the semiconductor chip 2. Also, a lead portion 20 extending from the outer ring 1
b, that is, the second lead 11 is in a state where the bump 22b formed at the tip of the lead faces the ground electrode pad 3a on the semiconductor chip 2. Next, FIG.
As shown in (B), the tip of the first lead 9 is connected to the electrode pad 3 of the semiconductor chip 2 via the bump 22a, and the tip of the second lead 11 is connected to the electrode pad 3 of the semiconductor chip 2 via the bump 22b. Each is connected to the ground electrode pad 3a by single point bonding.

Next, as shown in FIG. 4C, a conductive stage 14 is bonded to the outer ring 1 and the back surface of the semiconductor chip 2 via conductive adhesive layers 13a and 13b, respectively. As shown in ()), a sealing resin 15 such as an epoxy resin or a silicone resin is injected by potting into a region surrounded by the outer ring 1, the conductive stage 14, the semiconductor chip 2, the adhesive layer 4, and the film circuit 5,
By curing this, each component is integrated. Lastly, as shown in FIG. 4E, unnecessary portions are cut off at the outer position of the outer ring 1 to obtain the semiconductor package shown in FIG.

As described above, the semiconductor package of this embodiment has a structure in which the ground electrode pad 3a is short-circuited to the back surface of the chip via the second lead 11, the outer ring 1, and the conductive stage 14. The external connection terminal 8a is also short-circuited to the back surface of the chip via the third lead 12, the outer ring 1, and the conductive stage 14. As a result, the back surface of the chip becomes a common ground, and furthermore, the outer ring 1 and the conductive stage 14 connected to the back surface of the chip have the same potential, so that the ground line or the power supply line from the package mounting substrate can be more stably formed. It becomes possible to connect to the two electrode pads 3a.

Further, depending on the structure of the semiconductor chip 2,
Since the ground can be taken out from the chip back side to the chip front side (circuit formation side), the degree of freedom in circuit design is increased. Further, the heat generated in the semiconductor chip 2 is efficiently radiated from the rear surface to the outside via the conductive stage 14, so that the heat dissipation is also excellent.

In the above embodiment, the ground electrode pad 3a and the external connection terminal 8a are electrically connected to the outer ring 1 via the second lead 11 and the third lead 12, respectively. However, the present invention is not limited to this, and the same effect can be obtained by electrically connecting the power supply electrode pad and the external connection terminal to the outer ring instead of the ground. Further, in the above-described embodiment, the fan-in type semiconductor package in which the external connection terminal 8 exists inside the semiconductor chip 2 is illustrated.
Conversely, the present invention can be similarly applied to a fan-out type semiconductor package in which external connection terminals exist outside the semiconductor chip.

[0028]

As described above, according to the present invention, the ground or power supply electrode pad is electrically connected to the outer ring via the second lead, and the ground or power supply external connection is provided. Since the terminal is electrically connected to the outer ring via the third lead, and the conductive stage is bonded to the back surface of the semiconductor chip and the outer ring via a conductive adhesive layer, respectively, the package The ground line or the power supply line from the mounting substrate can be connected to the electrode pads of the semiconductor chip in a more stable manner. As a result, the fluctuation in the potential of the ground or the power supply in the package is reduced, so that it is possible to provide a semiconductor package having a super multi-pin structure having excellent electrical characteristics.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing one embodiment of a semiconductor package according to the present invention.

FIG. 2 is a plan view showing one embodiment of a semiconductor package according to the present invention.

FIG. 3 is a manufacturing process diagram of the lead frame in the embodiment.

FIG. 4 is a manufacturing process diagram of the semiconductor package in the embodiment.

FIG. 5 is a side sectional view showing a conventional BGA package.

FIG. 6 is a side sectional view showing an example of a semiconductor package having a super multi-pin structure.

[Explanation of symbols]

Reference Signs List 1 outer ring 2 semiconductor chip 3 electrode pad 5 film circuit 9 external connection terminal 9 first lead 11 second lead 12 third lead 13a, 13b conductive adhesive layer 14 conductive stage

Claims (1)

[Claims] 1. A semiconductor chip having a plurality of electrode pads on a peripheral portion of a chip surface and arranged inside a conductive outer ring; a film circuit arranged and formed on a surface side of the semiconductor chip; A plurality of external connection terminals protrudingly formed on the film circuit, and a first lead electrically connecting the electrode pads formed on the semiconductor chip to the external connection terminals formed on the film circuit A second lead formed by electrically connecting a grounding or power supply electrode pad and the outer ring among a plurality of electrode pads formed on the semiconductor chip; and forming a second lead on the film circuit. A third lead electrically connecting the external connection terminal for ground or power supply and the external ring among the plurality of external connection terminals, and a back surface of the semiconductor chip and the external lead. A semiconductor package, comprising: a shaped ring; and conductive stages each bonded via a conductive adhesive layer.