JPH1098363A - Output buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output buffer circuit with few noises at the time of output level change-over and also with small reliability with respect to a power voltage of an output delay. SOLUTION: The output buffer circuit is constituted of a first output circuit 1 which is driven by an input signal Sin, so as to output an output signal Sout corresponding to the input signal Sin. A first pulse output circuit 2 which delays the input signal Sin and outputs a first pulse signal Sa with pulse width corresponding to a delay quantity when the input signal Sin rises, the second pulse output circuit 3 which delays the input signal Sin and outputs the second pulse signal Sb with pulse width, corresponding to the delay quantity when the input signal Sin falls and the second output circuit 4 which is driven by the pulse signals Sa and Sb from the first and the second pulse output circuits 2 and 3. Therefore, the delay time Δt of an output signal Sout when the power voltage Vdd is low is proportional to the product of the power voltage Vdd and pulse width d and the delay time Δt' of the output signal Sout, when the power voltage Vdd is high is proportional to the product of the power voltage Vdd and pulse width d'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS (Comp
The present invention relates to an output buffer circuit configured using a complementary metal oxide semiconductor (circuit) circuit.

[0002]

2. Description of the Related Art Conventionally, in an output buffer circuit constituted by using CMOS, an output buffer circuit shown in FIG.
As shown in (b), when the signal Sa rises and falls, ringing may occur in the output signal Sout. Conventionally, a circuit may be designed with measures against noise to prevent such ringing from causing a malfunction of a peripheral circuit.

FIG. 8 is a circuit diagram showing an example of the configuration of a conventional output buffer in which such noise countermeasures are taken.
(A) is a figure showing an example of an output waveform outputted from this output buffer. The input signal Sin is output from the inverter 2
1 and a waveform adjusting circuit 22 to supply the output circuit 23 composed of CMOS. When the input signal Sin falls, the load capacitance of the waveform adjustment circuit 22 becomes the resistance R
Is charged via the N channel M of the output circuit 23.
The ON operation of the OS transistor 23N becomes slow, and the falling of the output signal Sout is prevented, thereby preventing the occurrence of ringing. When the input signal Sin rises, the P-channel MOS transistor 23P of the output circuit 23 is immediately turned on via the inverter 21 and thus ringing occurs. Difficult to do. The delay at the time of falling of the input signal Sin depends on the resistance R of the waveform adjusting circuit 22 and the MOS transistor 2 forming the output circuit 23.
Although it is determined by the size of 3P, 23N, etc., it also varies depending on the value of the power supply voltage Vdd.

Generally, a CMOS circuit 24 has a structure shown in FIG.
As shown in FIG. 11A, when the power supply voltage Vdd is high, although the delay is small, the noise is large and the power supply voltage Vdd is high, as shown in FIG.
Is low, the noise is small, but the delay is large. Therefore, when it is desired to reduce noise, the channel width of the CMOS 24 must be designed to be small, and when it is desired to reduce delay, the channel width of the CMOS 24 must be designed to be large.

[0005]

However, in the conventional output buffer circuit described above, if the circuit is designed to reduce noise generated when the power supply voltage Vdd is high, the delay generated when the power supply voltage Vdd is low is large. If the circuit is designed to reduce the delay that occurs when the power supply voltage Vdd is low, the noise that occurs when the power supply voltage Vdd is high becomes too large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to provide an output buffer circuit which has less noise at the time of switching output levels and has a small dependence of an output delay on a power supply voltage. I do.

[0007]

According to the present invention, there is provided an output buffer circuit comprising a first output circuit constituted by a CMOS circuit driven by an input signal and outputting an output signal corresponding to the input signal; A second output circuit composed of a CMOS circuit having an output terminal and an output terminal connected in common, and a pulse signal for driving the second output circuit at least when the output signal falls, and the pulse A pulse output circuit for controlling the pulse width of the signal so as to increase as the power supply voltage decreases.

Another output buffer circuit according to the present invention is:
A first output circuit configured by a CMOS circuit driven by an input signal and outputting an output signal corresponding to the input signal, and a delay signal obtained by delaying the input signal by a delay time that increases with a decrease in power supply voltage And a first pulse output circuit that outputs a pulse signal having a width corresponding to the delay time at a rising timing of the input signal based on the input signal and the input signal based on the delay signal and the input signal. A second pulse output circuit that outputs a pulse signal having a width corresponding to the delay time at the falling timing of the second pulse, an N-channel MOS transistor driven by a pulse signal from the first pulse output circuit, and the second pulse output circuit. Including a CMOS circuit composed of a P-channel MOS transistor driven by a pulse signal from a pulse output circuit and an output terminal thereof Characterized by comprising a second output circuit connected to the output of the first output circuit.

According to the output buffer circuit of the present invention, the second output circuit is provided so that the output terminal is commonly connected to the first output circuit driven by the input signal. Is driven by a pulse signal at least at the time of falling of the output signal, preferably at the time of rising and falling of the input signal, so as to supplement the driving capability of the first output circuit. Since the width increases with decreasing power supply voltage, the first
In addition, the total drive capability of the second output circuit can be constant regardless of the power supply voltage. Therefore, the delay amount can be set so that the output delay does not depend on the power supply voltage, and noise at the time of output level switching can be prevented by setting an appropriate delay amount independent of the power supply voltage.

According to another output buffer circuit of the present invention, the N-channel MOS transistor is driven by the pulse signal from the first pulse output circuit at the rising timing of the input signal, and the second transistor is driven at the falling timing of the input signal. Since the P-channel MOS transistor is driven by the pulse signal from the pulse output circuit described above, it is possible to set an appropriate delay amount at both the rise and the fall.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of an output buffer circuit according to one embodiment of the present invention. This output buffer circuit is driven by an input signal Sin, and outputs an output signal Sout corresponding to the input signal Sin.
And a first pulse output circuit 2 that delays the input signal Sin and outputs a first pulse signal Sa having a pulse width corresponding to the amount of delay when the input signal Sin rises. A second pulse output circuit 3 that delays the input signal Sin and outputs a second pulse signal Sb having a pulse width corresponding to the amount of delay when the input signal Sin falls, and the first and second pulses A second output circuit 4 driven by pulse signals Sa and Sb from the output circuits 2 and 3.

The first and second output circuits 1 and 4 are each composed of a CMOS circuit, and the second output circuit 4 mainly controls the delay amount at the time of rising and falling of the output signal Sout. The channel width of the CMOS transistors 1P and 1N constituting the first output circuit 1 is designed to be smaller than the standard, and the channel width of the CMOS transistors 4P and 4N constituting the second output circuit 4 is designed to be larger than the standard.

The first pulse output circuit 2 is composed of a delay circuit 11 in which an odd number of inverters 11 ₁ , 11 ₂ , 11 ₃ ,..., 11 _N are connected in cascade, and an AND circuit 12.
The logical product of the input signal Sin and the signal Sc obtained by inverting and delaying the input signal Sin by the delay circuit 11 is output as a first pulse signal Sa. The second pulse output circuit 3 includes an OR circuit 14 and a delay circuit 13 in which an odd number of inverters 13 ₁ , 13 ₂ , 13 ₃ ,..., 13 _N are connected in cascade, and an input signal Sin A logical sum of the signal and a signal Sd obtained by inverting and delaying the inverted signal by the delay circuit 13 is output as a second pulse signal Sb.

FIG. 2 is a diagram showing an example of the relationship between the power supply voltage Vdd and the delay time d in the delay circuits 11 and 13. The power supply voltage Vdd and the delay time d increase and decrease in a reverse direction, and when the power supply voltage Vdd is low, the delay time d increases, and when the power supply voltage Vdd is high, the delay time d increases.
Becomes smaller. The slope of the straight line in FIG.
₁ , 11 ₂ , 11 ₃ ,..., 11 _N , 13 ₁ , 13 ₂ , 13 ₃ ,
.., Determined by a delay time of 13 _N.

Next, the operation of the output buffer circuit thus configured will be described. FIG. 3 is a diagram illustrating an example of a signal waveform of each unit of the circuit. The input signal Sin and the signals Sc and S inverted and delayed by the delay circuits 11 and 13, respectively.
d is ANDed in the first pulse output circuit 2 and ORed in the second pulse output circuit 3, so that d is
As shown in Sb, the pulse signal is output at the rise and fall of the input signal Sin. Here, when the power supply voltage Vdd is low, as shown in FIG.
The pulse signal S output from each of the pulse output circuits 2 and 3
When the power supply voltage Vdd is high and the pulse width d of the pulse signals Sa and Sb output from the pulse output circuits 2 and 3 is large, the pulse width d 'of the pulse signals Sa and Sb is high, as shown in FIG. Narrows. The delay times Δt and Δt ′ of the output signal Sout output from the second output circuit 4 are proportional to the product of the power supply voltage Vdd and the pulse widths d and d ′.

According to this embodiment, the delay time .DELTA.t of the output signal Sout when the power supply voltage Vdd is low is proportional to the product of the power supply voltage Vdd and the pulse width d, and the output signal Sout when the power supply voltage Vdd is high is high. The delay time Δt ′ is proportional to the product of the power supply voltage Vdd and the pulse width d ′. For this reason, the pulse output circuits 2 and 2 satisfy Δt = Δt ′.
3, the power supply voltage Vdd of the delay time Δt of the output signal Sout is set as shown in FIG.
Can be reduced. At this time,
As shown in FIG. 5A, conventionally, the overall specification is determined by the output delay time when the power supply voltage Vdd, which is the worst condition, is low, but the slope at the rising timing and the falling timing of the output signal Sout is changed. You can control and improve it. In other words, from a different point of view, as shown in FIG. 5B, this also corresponds to a gradual change in the output waveform when the power supply voltage Vdd is high, which has a noise reduction effect.

Further, according to this embodiment, the delay circuit 1
Since the first and second pulse output circuits 1 and 13 are provided in the first and second pulse output circuits 2 and 3, respectively, the rising delay time and the falling delay time can be controlled separately. Is unnecessary, one circuit can be omitted to simplify the circuit, as shown in FIG. When the noise margin at the time of rising of the output signal is wide and control is not required, as shown in FIG.
The above-described control may be performed only when the output signal falls, omitting the channel MOS transistor.

[0018]

As described above, according to the present invention,
A second output circuit is provided so that an output terminal is commonly connected to a first output circuit driven by an input signal, and the second output circuit is turned on at least when the output signal falls.
Preferably at the time of rising and falling of the input signal,
It is driven by a pulse signal to supplement the driving capability of the first output circuit, and the pulse width of the pulse signal increases with a decrease in power supply voltage, so that noise at the time of switching output levels is reduced. It is possible to provide an output buffer circuit having a small dependence on the power supply voltage of the output delay.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an output buffer according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a relationship between a power supply voltage and a delay time in a delay circuit.

FIG. 3 is a diagram illustrating an example of an output waveform output from an output buffer.

FIG. 4 is a diagram for explaining a relationship between an output delay and a power supply voltage.

FIG. 5 is a diagram showing an example in which the output buffer in the embodiment and a conventional output buffer are compared.

FIG. 6 is a circuit diagram showing a configuration of an output buffer according to another embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of an output buffer according to still another embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example of a configuration of a conventional output buffer.

FIG. 9 is a diagram showing an example of a conventional output waveform.

FIG. 10 is a diagram showing a configuration of a CMOS circuit.

FIG. 11 is a diagram for explaining a relationship between an output delay and a power supply voltage.

[Explanation of symbols]

1. First output circuit, 2. First pulse output circuit, 3.
2nd pulse output circuit, 4... 2nd output circuit, 11, 1
3. Delay circuit, 11 ₁ , 11 ₂ , 11 ₃ , 11 _N , 13 ₁ ,
13 ₂ , 13 ₃ , 13 _N … inverter, 12… AND circuit, 14… OR circuit.

Claims (2)

[Claims] 1. A first output circuit comprising a CMOS circuit driven by an input signal and outputting an output signal corresponding to the input signal, and a CMO having a common connection between the first output circuit and an output terminal.
A second output circuit constituted by an S circuit; outputting a pulse signal for driving the second output circuit at least at the time of falling of the output signal, and changing a pulse width of the pulse signal with respect to a decrease in power supply voltage. An output buffer circuit comprising: a pulse output circuit for controlling the output to increase. 2. A first output circuit comprising a CMOS circuit driven by an input signal and outputting an output signal corresponding to the input signal, and a delay time which increases the input signal with respect to a decrease in power supply voltage. A first pulse output circuit that outputs a pulse signal having a width corresponding to the delay time at a rising timing of the input signal based on the delayed delay signal and the input signal; and A second pulse output circuit for outputting a pulse signal having a width corresponding to the delay time at the falling timing of the input signal based on the input signal; and an N-channel MOS transistor driven by the pulse signal from the first pulse output circuit A CMOS circuit comprising a P-channel MOS transistor driven by a pulse signal from the second pulse output circuit; And a second output circuit having an output terminal connected to the output terminal of the first output circuit.