JPH11102921A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a field effect transistor which is enhanced in reliability without deteriorating in high-frequency characteristics under operating conditions such as a high applied-voltage, a large current, and high temperature by a method wherein recesses are varied in depth in the direction of gate fingers so as to make a threshold voltage low at the center and high at edges in the direction of the gate fingers. SOLUTION: A region where a source electrode 9 and a drain electrode are formed is opened on a semi-insulating GaAs substrate 1. Then, Si ions are implanted to form an N<+> -GaAs region 5. An operation opening is formed of resist, and the first implantation of Si ion is performed. Then, a pattern used for opening only operating layers each located at the edges of a comb- shaped gate is formed of resist, and the second ion implantation of Si ions is carried out. Thereafter, an activation annealing process is carried out at a temperature of 800 deg.C for 30 minutes or so. By this setup, a channel region 6 located at the center of the fingers is of impurity concentration 1.5E17 cm<-3> , and the edges of the finger which are subjected to an ion implantation process twice are of impurity concentration 2.0E17 cm<-3> .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly, to a high power GaAs field effect transistor which requires high reliability under high voltage, high current and high temperature operating conditions.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor (hereinafter referred to as "F
ET ”. ) Used a comb-shaped gate structure having a uniform gate finger length. But,
In this structure, the element itself is heated by the applied high voltage and the induced large current, and the characteristic is deteriorated and sometimes destroyed.

[0006] As shown in FIGS. 6 and 7, the mechanism of this deterioration is extremely extreme at the center of the chip, especially at the center when viewed in the finger direction of the comb gate, when focusing on the temperature inside the device. You can see that it is getting higher. This is because heat dissipation is poor at the center of the element, and heat tends to accumulate. At such a high temperature, device characteristics such as threshold voltage and gate leak current change, and the gate current increases. As a result, the gate potential changes more and more,
A phenomenon in which the drain current increases, thermal runaway occurs, and in some cases, leads to destruction.

Therefore, the conventional finger shape (FIG. 8 (a)) of the comb gate FET is shortened at the center as shown in FIG. 7 (c), or the gate pitch is reduced as shown in FIG. 8 (b). By changing the temperature, the heat generated in the central portion is reduced, so that only the central portion is prevented from becoming high in temperature, thereby preventing thermal runaway (Japanese Patent Laid-Open No. 7-283235).

[0005]

In particular, high-power FETs are
To obtain a large output, FIGS. 2, 6 (a) and 7
As shown in FIG. 1A, the unit cell is composed of a large number of fingers, and has a unit cell configuration in which several fingers are collectively fed in order to make the feeding path the same for each finger.

However, if the finger length is increased, the gate resistance (Rg) or the like is increased, and the gain, which is one of the high-frequency characteristics, is inversely proportional to these. Therefore, increasing the finger length decreases the gain. Will be.
On the other hand, shortening the finger length increases the gain. Therefore, when the finger length of the comb-shaped gate is made non-uniform as in the conventional example, the high-frequency characteristics such as gain from each finger are different, so that the high-frequency characteristics in the unit cell and between the cells, particularly the output, are low. Deterioration has occurred.

Also, when the pitch of the gate fingers is changed, the high-frequency characteristics of each cell become non-uniform, and the optimum matching conditions are different, so that the actual gain is reduced. Also, increasing (changing) the distance between the fingers has led to an increase in the chip area.

It is an object of the present invention to provide a high-output FET with improved reliability without deteriorating high-frequency characteristics even under high applied voltage, high current, and high-temperature operating conditions.

[0009]

SUMMARY OF THE INVENTION The present invention relates to a field effect transistor having a comb-shaped gate electrode structure, wherein the threshold voltage is shallow at the center and deep at the end along the gate finger direction. The present invention relates to a field-effect transistor having a different recess depth along a direction.

Further, according to the present invention, in a field effect transistor having a comb-shaped gate electrode structure, a threshold voltage is reduced along a gate finger direction such that a threshold voltage is shallow at a center portion and deep at an end portion along the gate finger direction. The present invention relates to a field-effect transistor characterized in that channel layers have different impurity concentrations.

Further, according to the present invention, in a field effect transistor having a comb-shaped gate electrode structure, the threshold voltage is reduced along the gate finger direction such that the threshold voltage is shallow at the center portion and deep at the end portions along the gate finger direction. The present invention relates to a field effect transistor having a different insulating film configuration.

In the above invention, the channel layer is formed along a direction substantially perpendicular to the gate finger direction so that the threshold voltage is shallow on the middle side and deep on the outside along the direction substantially perpendicular to the gate finger direction. The impurity concentration may be low on the middle side and high on the outside.

Further, according to the present invention, in a field effect transistor having a comb-shaped gate electrode structure, the threshold voltage of the gate finger located on the middle side is shallow and the threshold voltage of the gate finger located on the outside is deepened. like,
The present invention relates to a field-effect transistor characterized in that the impurity concentration of a channel layer is low on the middle side and high on the outside.

Further, according to the present invention, in a field effect transistor having a comb-shaped gate electrode structure, the gate voltage is set so that the threshold voltage is shallow on the middle side and deep on the outside along the direction substantially perpendicular to the gate finger direction. The present invention relates to a field effect transistor characterized in that the impurity concentration of the channel layer is low on the middle side and high on the outside along the direction substantially perpendicular to the finger direction.

In each of the above inventions, the recess at the finger outer portion of the comb gate of the high-output FET is made shallower and the center portion is made deeper, or the impurity concentration at the outer portion of the comb gate finger is made higher and the concentration at the center portion is made lower, or By forming a passivation film and varying its configuration to induce piezo-electricity, the threshold voltage (hereinafter, referred to as “Vt”) on the outer side of the gate finger is deepened, and the V at the center is increased.
t can be made shallower. As a result, it is possible to balance heat generation and heat radiation in the entire gate finger without deteriorating high-frequency characteristics, and to make the temperature of each channel portion uniform.

The amount of heat generated from various parts of the device is substantially determined by the drain voltage and the drain current applied to that part. Further, the FET characteristics at high frequencies, particularly the gain, depend on the gate finger length, and in order to achieve matching at the output side, the balance between each finger and between cells is important. Therefore, it is required to keep the finger length and finger pitch constant. Therefore, while keeping the finger length and the pitch constant, the Vt at the center of the FET is
Only the shallow portion and the peripheral portion are made deeper to control the drain current flowing through the FET portion, so that the drain current at the center portion of the finger with poor heat dissipation is reduced and the drain current at both ends of the finger with good heat dissipation is increased. As a result, the heat distribution in each part of the FET becomes uniform,
It is possible to suppress the partial degradation of
Since it is possible to prevent a sudden rise in the temperature of the central part, a device that is unlikely to undergo thermal runaway can be realized.

Further, since the Vt in the same FET chip is different, the rising portion of the transfer characteristic becomes gentle, and the distortion characteristic in the case where the operation is performed with a reduced current can be improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments.

(Embodiment 1) Finger of FET of this embodiment
FIG. 3 shows the cross-sectional shape of the central part. This production first,
On the semi-insulating GaAs substrate 1,
To open the source and drain electrode formation regions.
Was. Next, implantation (irradiation) of Si ions into this portion
Amount: 1E13cm^-3, Acceleration voltage: 50 kV, and irradiation
Amount: 1E13cm ^-3, Acceleration voltage: 200 kV)
n⁺-GaAs region 5 was produced.

Next, the opening of the operating portion is formed of a resist, and first Si ions are implanted therein (irradiation amount: 3.
0E12 cm ^-3 , acceleration voltage: 70 kV), and then a pattern for opening only the operation layers at both ends of the comb gate is formed by a resist, and second Si ions are implanted (irradiation amount: 0.4E12 cm ^-3). , Acceleration voltage: 70 kV)
Was done. Thereafter, activation annealing was performed at 800 ° C. for about 30 minutes.

As described above, as shown in FIG.
Channel region (n-GaAs region) 6 at the center of the finger
Then the impurity concentration is 1.5E17cm^-3, Re-ion implantation (No.
2), at both ends of the finger
Impurity concentration 2.0E17cm ^-3You can get the structure
Was. Note that FIG. 1A shows the AA of the chip shown in FIG.
FIG. 5 is a diagram showing a relationship between impurity concentration and Vt in a line cross section.
Here, the recess depth was constant in this embodiment.

Thereafter, an opening shape is formed by photolithography to form a source electrode and a drain electrode by photolithography, Au / GeNi is deposited, a source electrode 9 and a drain electrode 10 are formed by a lift-off method, and then ohmic formation is performed. For annealing was performed. Next, the gate electrode 8 was formed by vapor deposition, a lift-off method, or the like.

Example 2 An undoped GaAs layer serving as a buffer layer is grown on a semi-insulating GaAs substrate 1 by MBE or MOCVD at 8000 A, and then n-type GaAs having an impurity concentration of 2.0E17 cm ^-3 serving as a channel layer is formed.
The s layer was grown to a thickness of 2000-3000A. Next, ohmic contact is performed, and the impurity concentration is 2.0E17c.
An n ⁺ -GaAs layer 4 of m ⁻³ and a thickness of 1500 A was epitaxially grown.

Thereafter, in order to perform a first recess etching (formation of the first recess 11) in which only the region corresponding to the center of the gate finger of the comb gate is recessed, a pattern having an opening shape using a photoresist having low adhesion is used. Was formed, and a recess etching of about 100 A was performed using this as a mask. After the resist is stripped, in order to perform a second recess etching, a pattern in which the entire surface of the comb gate finger formation region is opened by photolithography is formed, and a second recess etching (formation of the second recess 12) of about 1900 A is performed. went. Here, in the first recess etching, by using a resist having weak adhesion, the cross-sectional shape along the line AA in FIG. 1C, that is, the cross-sectional shape in the finger direction is shown in FIG. As described above, since a gentle recess having an inclination angle of 30 degrees or less is formed, concentration of an electric field due to a step can be prevented.

Next, using photolithography, A
After depositing a multilayer metal film of u / GeNi, a source electrode and a drain electrode were formed by lift-off, then annealing was performed, a gate opening shape was formed by photolithography, and a gate electrode was formed by lift-off after Al deposition. .

As a result, Vt in the gate finger direction
As shown in FIG. 1A, a structure in which Vt is shallow at the center of the finger and Vt is deep at the end of the finger is formed. In FIG. 1A, in this embodiment, the impurity concentration is constant.

In the gentle recess formation of this embodiment, a gentle recess formation can be realized by using anodic oxidation instead of using a resist having weak adhesion. Further, by combining a resist having low adhesion and anodic oxidation, it is possible to further reduce the inclination angle and reduce the electric field concentration due to the step.

In forming the recess, the first recess etching and the second recess etching can be performed in reverse.

(Embodiment 3) This embodiment is the same as the conventional one until the gate electrode 8, source electrode 9 and drain electrode 10 are formed as shown in FIG. It is changed at the periphery.

When pressure from the passivation film is applied to the gate electrode 8, a piezo charge is induced under the gate electrode, so that a shift in pinch-off voltage is observed (PM
Asbeck, C. Lee, and MFChang, "Pezoelectric Effect
in GaAs FET's and Their Role in Orientation-Depend
ent Device Characteristics ", IEEE Trans. Electron
Device, vol.ED-31, No.10, pp.1377-1380, 1984).

As shown in the document, the sign of the electric charge is
It depends on the direction of the stress and the crystal orientation, and (1,0,0)
On the crystal, the gate width direction of the gate finger is (0, 1,
When formed in the direction of 1), a positive fixed charge is induced immediately below the gate in the case of tensile stress, and a negative fixed charge is induced in the case of compressive stress. These fixed charges change the charge amount of the channel and change the thickness of the depletion layer immediately below the gate, so that the pinch-off voltage shifts to a deep side and a shallow side, respectively.

In this embodiment, the gate width direction is set to (0, 1,
5) As shown in FIG. 5A, a CVD oxide film is grown on the entire surface as the first insulating film 13 to generate a tensile stress and induce a positive piezo charge immediately below the gate electrode. Was. Subsequently, the oxide film at the center was selectively removed using a photolithography method and a dry etching technique while leaving the oxide films at both ends of the gate finger. Next, a second insulating film 14 (for example, a CVD SiN film) is formed on the entire surface.
Grew. A compressive stress is generated immediately below the gate electrode covered with the second insulating film 14. According to the above-mentioned literature, the compressive stress of the insulating film is set to 5E9 dyn / cm ^-2 and the film thickness is set to 0.
If the gate length is 2 μm and the gate length is 1 μm, the change in pinch-off voltage is about 0.2 V. As described above, at the both ends of the finger (FIG. 5B), the stress of the first insulating film 13 and the stress of the second insulating film 14 are offset, but the center of the finger (FIG. 5B).
In (c)), since the pinch-off voltage changes due to the piezo charge, Vt becomes shallow by about 0.2 V.

In the present embodiment, the first insulating film 1
3 (FIG. 5A) and a gate electrode portion covered with the first and second insulating films (FIG. 5B).
And a gate electrode portion covered with a second insulating film (FIG. 5).
(C)) It is also possible to change the pinch-off voltage in three stages. Further, the invention of this embodiment can also be used for an FET by ion implantation.

Also, by combining the first or second embodiment with the third embodiment, the heat distribution in the chip can be reduced.

The first to third embodiments are described with reference to FIG.
As shown in (b), by controlling the impurity concentration, the Vt of the outermost cell can be made deep, and the temperature distribution in the finger lateral direction (substantially perpendicular to the finger direction) can be made uniform. . FIG. 1B is a diagram showing the relationship between the impurity concentration and Vt in a cross section taken along the line BB of the chip of FIG. 1C.

[0036]

According to the present invention, by balancing the heat generation and the heat radiation from the FET, the temperature of the element becomes uniform, so that the local deterioration of the characteristics can be prevented and the reliability is improved. At the same time, the high-frequency characteristics of the FET can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a field effect transistor of the present invention.

FIG. 2 is a schematic enlarged partial plan view near the gate of the field effect transistor of the present invention and a conventional field effect transistor.

FIG. 3 is a partial cross-sectional view near a gate of the field effect transistor of the present invention.

FIG. 4 is a sectional view showing a recess shape in a gate finger direction of the field effect transistor of the present invention.

FIG. 5 is a partial cross-sectional view near the gate of the field effect transistor of the present invention.

FIG. 6 is an explanatory diagram of a temperature distribution in a vertical direction (gate finger direction) of a conventional field effect transistor.

FIG. 7 is an explanatory diagram of a temperature distribution in a lateral direction of a conventional field effect transistor.

FIG. 8 is an explanatory diagram of a comb gate structure of a conventional field effect transistor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 GaAs substrate 2 buffer layer 3 channel layer 4 n ⁺ -GaAs layer 5 n ⁺ -GaAs region 6 channel region 8 gate electrode 9 source electrode 10 drain electrode 11 first recess 12 second recess 13 first insulating film 14 second Insulating film 101 Gate electrode pad 102 Source electrode pad 103 Drain electrode pad 104 Gate finger region

Claims (9)

[Claims] In a field effect transistor having a comb-shaped gate electrode structure, a recess depth along a gate finger direction is set so that a threshold voltage is shallow at a center portion and deep at an end portion along a gate finger direction. A field-effect transistor characterized by being different. 2. The field effect transistor according to claim 1, wherein the recess depth is deep at the center of the gate finger and shallow at the end of the gate finger. 3. In a field effect transistor having a comb-shaped gate electrode structure, an impurity of a channel layer is formed along a gate finger direction such that a threshold voltage is shallow at a center portion and deep at an end portion along a gate finger direction. A field-effect transistor characterized by different concentrations. 4. The field effect transistor according to claim 3, wherein the impurity concentration of the channel layer is low at the center of the gate finger and high at the end of the gate finger. 5. A field effect transistor having a comb-shaped gate electrode structure, wherein a threshold voltage is different along a gate finger direction and an insulating film is formed along a gate finger direction so as to be shallow at a center portion and deep at an end portion. A field-effect transistor characterized in that: 6. The field effect transistor according to claim 5, wherein the insulating film is configured to generate a compressive stress at the center of the gate finger and a tensile stress at the end of the gate finger. 7. The impurity concentration of a channel layer substantially perpendicular to the gate finger direction so that the threshold voltage is shallow on the middle side and deep on the outside along the direction substantially perpendicular to the gate finger direction. The field effect transistor according to any one of claims 1 to 6, wherein is higher at the middle and lower at the outside. 8. In a field effect transistor having a comb-shaped gate electrode structure, a channel is set such that a threshold voltage of a gate finger located on the middle side is shallow and a threshold voltage of a gate finger located on the outside side is deep. A field-effect transistor wherein the impurity concentration of the layer is lower on the middle side and higher on the outer side. 9. A field effect transistor having a comb-shaped gate electrode structure, wherein the threshold voltage is shallow on the middle side and deeper on the outside along the direction substantially perpendicular to the gate finger direction. A field effect transistor wherein the impurity concentration of the channel layer is low on the middle side and high on the outside along the substantially vertical direction.