JPH11111650A - Semiconductor device manufacturing method, semiconductor device, and jig used for the manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate dealing at carrying of a semiconductor chip in a manufac turing process of a semiconductor device by cutting out a chip block collectively having at least a plurality of semiconductor chips as one unit, and carrying the chip block by accommodating it in one jig. SOLUTION: A plurality of semiconductor chips 2 are formed on a main surface of a semiconductor wafer. In this step, starting from the state of a polished wafer, the respective processes such as film formation, photolithography, etching and impurity introduction have been appropriately repeated, a DRAM element is formed on the main surface, a wiring is formed on it, and the processes for protective film formation is completed. Continuuingly, a semiconductor chip 2 is cut out from the semiconductor wafer. That is, cutting-out is performed in units of chip block in a batch having at least a plurality of the semiconductor chips 2. For example, one chip block CB has four semiconductor chips 2. This chip block CB is accommodated in a carrier (jig) and carried to a inspecting equipment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, a semiconductor device and a jig technology used in the manufacturing method, and more particularly, to a multi-device configured to house two or more semiconductor chips in one package. Chip module (Mu
ltichip Module: hereinafter abbreviated as MCM) and a technology effective when applied to a manufacturing method thereof.

[0002]

2. Description of the Related Art A major problem in the production of an MCM is to judge the quality of a semiconductor chip. In the case of the MCM, it is difficult to repair a defective semiconductor chip.
This is because the entire M becomes defective. That is, the use of a semiconductor chip that has been determined to be completely non-defective by inspection leads to an improvement in the yield of the MCM.

For this reason, in the process of manufacturing the MCM, individual semiconductor chips are cut out from a semiconductor wafer, and before the semiconductor chip mounting process, the individual semiconductor chips are individually housed in a carrier, and the quality is evaluated. Inspection for sorting may be performed. This allows
The amount of rework of the MCM is reduced to reduce manufacturing costs.

[0004] In the manufacture of the MCM, the carrier accommodating the semiconductor chip prior to the inspection for the quality check of the semiconductor chip is disclosed in, for example, Japanese Patent Application Laid-Open No. 6-2442.
No. 53 describes this.

[0005]

However, the present inventor has found that the above-described technique for individually inspecting semiconductor chips individually cut from a semiconductor wafer has the following problems.

That is, in a semiconductor chip pass / fail selection step after cutting individual semiconductor chips from a semiconductor wafer, the individual semiconductor chips are individually accommodated in a carrier, transported, inspected, and the like. There is a problem in that the pass / fail selection process is troublesome and time-consuming.

[0007] In addition, there is a problem that it takes time and effort to carry out the quality judgment processing of the semiconductor device, and also requires the same number of expensive carriers as the number of semiconductor chips, thereby increasing the manufacturing cost of the semiconductor device.

[0008] Although not limited to the MCM,
With the recent increase in the diameter of semiconductor wafers, the following problems have arisen. First, it is difficult to handle semiconductor wafers. Second, the semiconductor wafer is liable to crack, chip, or the like during the transfer of the semiconductor wafer. Third, in order to cope with a large-diameter semiconductor wafer, new and dedicated facilities and apparatuses are required in the facilities and apparatuses in the subsequent process.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique which facilitates handling of a semiconductor chip in a semiconductor device manufacturing process at the time of transport and simplifies the semiconductor device manufacturing process.

Another object of the present invention is to provide a technique capable of shortening the manufacturing time of a semiconductor device.

Another object of the present invention is to provide a technique capable of reducing the cost of a semiconductor device.

Another object of the present invention is to provide a technique capable of easily handling a large-diameter semiconductor wafer.

Another object of the present invention is to provide a technique capable of suppressing the occurrence of defects such as cracks and defects during the transfer of a large-diameter semiconductor wafer.

Still another object of the present invention is to provide a technique capable of handling a large-diameter semiconductor wafer without a significant change in equipment and devices in a subsequent process.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the method of manufacturing a semiconductor device of the present invention, when a semiconductor chip is cut from a semiconductor wafer on which a plurality of semiconductor chips are formed, a step of cutting a chip block integrally having two or more semiconductor chips as one unit is provided. And transporting the chip block in a state of being housed in one jig.

Further, a method of manufacturing a semiconductor device according to the present invention
A step of cutting a chip block integrally having two or more semiconductor chips as a unit when cutting a semiconductor chip from a semiconductor wafer on which a plurality of semiconductor chips are formed; The method includes a step of simultaneously inspecting a plurality of semiconductor chips, a step of directly mounting the chip block on a mounting board, and a step of packaging the chip block mounted on the mounting board.

Further, a method of manufacturing a semiconductor device according to the present invention
A step of dividing the semiconductor wafer into a plurality of sub-wafers having two or more semiconductor chips and transporting the divided sub-wafers.

Further, the semiconductor device of the present invention is obtained by sealing a chip block integrally having two or more semiconductor chips in a package.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions in all drawings for describing the embodiments are denoted by the same reference numerals.) , And the repeated explanation is omitted).

(Embodiment 1) FIG. 1 is a flow chart showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a plan view of the semiconductor wafer after the pre-process of FIG. 1, and FIG.
4 is a plan view of the chip block after the first dicing step, FIG. 4 is a perspective view of a carrier used in the manufacturing process of the semiconductor device of FIG. 1, FIG. 5 is a cross-sectional view of the carrier of FIG. 4, and FIG. 7 to 11 are explanatory views for explaining a manufacturing process of the semiconductor device of FIG. 1, and FIG. 12 is a view showing a chip block after the second dicing process of FIG. Explanatory diagrams for explaining, FIGS.
FIG. 15 is an explanatory diagram for describing a manufacturing process of the semiconductor device according to the embodiment.

In the first embodiment, a case where the present invention is applied to, for example, a method of manufacturing a dynamic random access memory (DRAM) module (semiconductor device) will be described with reference to FIGS. I do.

First, as shown in FIG.
A plurality of semiconductor chips 2 are formed on the main surface of (2) (pre-process 100).

That is, at this stage, starting from the state of the mirror-polished wafer, predetermined semiconductor manufacturing steps such as a film forming step, a photolithography step, an etching step, an impurity introducing step and the like are appropriately repeated, and the main surface thereof is formed. To DR
The process of forming an AM element, forming a wiring thereon, and further forming a surface protective film thereon has already been completed.

The semiconductor wafer 1 is made of, for example, a p-type silicon (Si) single crystal. The semiconductor chips 2 are formed, for example, in a planar rectangular shape, and are regularly arranged on the main surface of the semiconductor wafer 1 in the vertical and horizontal directions of FIG. For example, on the circuit formation surface of each semiconductor chip 2, 1
A 6 Mbit DRAM is formed.

In addition, between the semiconductor chips 2 adjacent to each other, there is provided a cutting area where a dicing blade is applied and cut when cutting each semiconductor chip 2 from the semiconductor wafer 1. The planar shape of the semiconductor chip 2 is not limited to a rectangular shape but may be a square.

Subsequently, the semiconductor chips 2 are cut out from the semiconductor wafer 1 (first dicing step 101).

In the first embodiment, the semiconductor chips 2 are not individually cut out but cut out in units of a chip block having a plurality of semiconductor chips 2 integrally. FIG. 3 shows an example of the chip block CB.

Although not particularly limited, one chip block CB has, for example, four semiconductor chips 2. The four semiconductor chips 2 are arranged, for example, on a straight line along the longitudinal direction. The semiconductor chips 2 in the chip block CB are electrically independent of each other.

The reason that one chip block CB is composed of four semiconductor chips 2 is that in the first embodiment,
This is because a 16 Mbit DRAM is configured in each of the semiconductor chips 2, and a 64 Mbit DRAM can be configured with four semiconductor chips 2. Therefore, the number of semiconductor chips 2 constituting the chip block CB at this stage is not limited to four, but can be variously changed.

On the circuit forming surface of each semiconductor chip 2,
In the vicinity of both sides in the width direction, a plurality of bonding pads 3BP1 are regularly arranged along the longitudinal direction of the semiconductor chip 2. Note that the bonding pads 3BP1 are not disposed near both sides in the longitudinal direction of the semiconductor chip 2.

The bonding pads 3BP1 are used to connect the electrodes of the DRAM formed on the semiconductor chip 2 to the semiconductor chip 2.
And is made of, for example, aluminum (Al) or an Al alloy.

Thereafter, an inspection such as a burn-in test is performed on the semiconductor chip 2 (inspection step 10).
2).

When shifting to the inspection step, in the first embodiment, first, the chip block CB is transported to the inspection apparatus in a state of being accommodated in the carrier (jig) 4 as shown in FIGS. I do. That is, in the first embodiment, a plurality of semiconductor chips can be transported collectively as one chip block CB.

For this reason, the handling of the semiconductor chip 2 in the manufacturing process of the DRAM module is facilitated, and the transport of the semiconductor chip 2 is facilitated. Therefore, the manufacturing process of the DRAM module can be simplified. Further, it is possible to shorten the manufacturing time of the DRAM module. Furthermore, D
Expensive carrier 4 used in RAM module manufacturing process
Can be greatly reduced, so that the price of the DRAM module can be reduced.

The carrier 4 has a carrier base 4a,
And a carrier lid 4b. Carrier base part 4
The chip block CB (see FIG. 5) can be accommodated in the chip block accommodating portion 4a1 with the circuit forming surface thereof facing the carrier base portion 4a.

An opening 4a2 is formed in the center of the lower surface of the carrier base 4a, and the bonding pad 3 of each semiconductor chip 2 in the chip block CB (see FIG. 5) accommodated in the chip block accommodating area 4a1.
The structure is such that BP1 is exposed from the opening 4a2.

The carrier lid 4b is connected to the carrier base 4
It is attached to a so that it can be opened and closed. A pressurizing section 4c is provided between the inner wall surface of the carrier lid 4b and the chip block CB (see FIG. 5).

The pressing section 4c is made of, for example, a coil spring and presses the chip block CB against the carrier base section 4a. However, the pressing portion 4c is not limited to a coil spring but can be variously changed, and may be a leaf spring, for example.

A pressing plate 4d is provided between the pressing portion 4c and the back surface of the chip block CB. This pressing plate 4d is a plate for making the pressure applied to the back surface of the chip block CB by the pressing portion 4c uniform within the back surface and for preventing the back surface of the chip block CB from being damaged by the pressing force of the pressing portion 4c. It is.

The chip block CB (see FIG. 5) accommodated in such a carrier 4 is carried to the inspection device and is accommodated in the carrier 4 and accommodated in a socket on a test board in the inspection device. FIG. 6 shows an example of the socket 5.

The socket 5 includes a socket base 5a,
And a socket lid 5b. Socket base 5
A contact portion 5c is provided at the center of the bottom surface of a.

A plurality of contact terminals 5c1 made of a predetermined conductive material are provided on the upper surface of the contact portion 5c near the side in the width direction along the longitudinal direction of the chip block CB shown in FIG. They are arranged regularly so as to correspond to the bonding pads 3BP1. The contact terminal 5c1 is electrically connected to an inspection device through a test board.

The carrier 4 having the above-described chip block CB is accommodated in a state where the opening 4a2 faces the socket base 5a. When the socket cover 5b is closed in this state, the contact 5c of the socket 5 is closed.
The contact terminals 5c1 on the upper surface and the bonding pads 3BP1 on the chip block CB exposed from the openings 4a2 of the carrier 4 come into firm contact with each other. Thereby, each semiconductor chip 2 of the chip block CB and the inspection device are electrically connected.

After the carrier 4 is accommodated in the socket 5, the semiconductor chips 2 (see FIG. 3) in the chip block CB in the carrier 4 are simultaneously inspected. Here, for example, a burn-in test is performed. That is, for example, a current is applied to the semiconductor chip 2 under a high-temperature condition, and the semiconductor chip 2 that may be defective in the future is screened to obtain a KGD (Known Good Die).

As a result of this inspection, when no defect occurs in all the semiconductor chips 2 of the chip block CB, that is, when it is determined that the entire chip block CB is a non-defective product, the mounting is performed in the first embodiment. The process proceeds to a step (step 103b).

First, the carrier 4 is taken out from the socket 5 (see FIG. 6), and the carrier 4 is transported to the mounting device. Then, a non-defective chip block CB is taken out of the carrier 4 and mounted on a module board (mounting board) 6 shown in FIGS. 7 and 8 with its circuit formation surface facing upward.

FIGS. 7 and 8 show a state where the module substrate 6 is mounted on the lead frame 7. FIG. 7 does not show a chip block to make the drawing easier to see. FIGS. 8A and 8B show cross sections corresponding to the lines VIIIA-VIIIA and VIIIB-VIIIB in FIG. 7, respectively.

The module substrate 6 is formed by providing a wiring layer on a single rectangular Si crystal, for example, by a thin film technique. However, the module substrate 6 is not limited to the one based on Si but can be variously modified. For example, a printed wiring board having a laminated structure may be used, May be used, or a multilayer wiring board in which a wiring layer is provided by a thin film technique on a ceramic substrate or a metal plate may be used.

At the center on the main surface of the module substrate 6, a chip mounting area 6a is arranged. In the first embodiment, the chip mounting area 6a is formed to extend along the longitudinal direction of the module substrate 6 so that the chip block CB can be mounted. The surface of the chip mounting area 6a is plated with, for example, gold (Au).

On both sides of the chip mounting area 6a on the main surface of the module substrate 6, a plurality of bonding pads 6BP1 are regularly arranged along the longitudinal direction of the chip mounting area 6a. This bonding pad 6
BP1 is the bonding pad 3BP1 of the semiconductor chip 2.
(See FIG. 3 and the like) and an electrode to which a wire for electrically connecting the wiring of the module substrate 6 is connected.

In the vicinity of both sides in the width direction of the module substrate 6, a plurality of bonding pads 6BP2 are regularly arranged along the longitudinal direction. The bonding pad 6BP2 is an electrode to which a wire for electrically connecting the lead 7a of the lead frame 7 and the wiring of the module substrate 6 is connected. The bonding pad 6BP1 is electrically connected to the bonding pad 6BP1 through the wiring of the module substrate 6. It is connected to the.

The area A surrounded by a broken line in FIG.
Indicates an area where another electronic component such as a capacitor is mounted.

The lead frame 7 is made of, for example, 42 alloy or the like, and the module substrate 6 is mounted on the substrate mounting portion 7a. A plurality of leads (external terminals) 7b are regularly arranged along the long sides of the substrate mounting portion 7a in the vicinity of both long sides thereof so as to surround the substrate mounting portion 7a. I have.

Subsequently, after a non-defective chip block CB is mounted on the module substrate 6, as shown in FIGS. 9 and 10, the bonding pad 3BP1 of each semiconductor chip 2 of the chip block CB and the bonding of the module substrate 6 The pads 6BP1 are electrically connected by bonding wires 8a, and the other bonding pads 6BP2 of the module substrate 6 and the leads 7b are electrically connected by bonding wires 8b. Thereby, the semiconductor chip 2 and the leads 7b are electrically connected.

The bonding wires 8a, 8b
Is made of, for example, Au. In addition, FIG.
(B) is a sectional view taken along the line XA-XA and the line XB-XB in FIG. 9, respectively.

Thereafter, the mounted chip block CB
11 (a) and 11 (b), after sealing with a package 9 made of, for example, an epoxy resin or the like (step 104), the lead 7b is cut from the lead frame 7,
Further, the portion of the lead 7b protruding from the package 9 is formed into, for example, a gull wing shape, and the manufacture of the DRAM module is completed. The cross sections of FIGS. 11A and 11B correspond to the cross sections of FIGS. 10A and 10B, respectively.

In the first embodiment, for example, a chip block CB integrally including four semiconductor chips 2
Is sealed in a package 9 to form a DRAM module, which makes it possible to promote downsizing of the DRAM module as compared with a case where the individual semiconductor chips 2 are separately mounted and sealed. I have. For this reason,
It is possible to promote downsizing of an electronic device having a DRAM module.

Further, since the wiring length between adjacent semiconductor chips 2 can be shortened, the high-speed performance of each semiconductor chip 2 can be brought out without impairing the entire DRAM module. It is possible to promote speeding up.

Further, since the wiring length between the adjacent semiconductor chips 2 can be reduced, the influence of noise and the like can be reduced. Further, since the heat transfer path can be shortened, it is possible to suppress the deterioration of element characteristics due to heat during the operation of the DRAM module.

In the above description, the inspection step 10
After 2, the case where the chip block CB having the four semiconductor chips 2 is directly packaged has been described.

However, in some cases, the chip block C
In some cases, it is better to further divide B. For example, there is a case where a predetermined semiconductor chip 2 of the chip block CB becomes defective due to mounting convenience or an inspection when mounting on a module substrate.

In this case, the process proceeds to the second dicing step 103a after the inspection step 102 in FIG.

FIG. 12A shows the second dicing step 10.
FIG. 2B is a plan view of the chip block CB before 2a, and FIG. 2B shows an example in which the chip block CB of FIG. 1A is divided into two good chip blocks CB1. In this case, the chip block CB1 has two good semiconductor chips 2 integrally.

FIG. 12C shows an example in which the chip block CB shown in FIG. 12A is divided into one good chip block CB 1 and one defective semiconductor chip 2. In this case, the chip block CB1 integrally includes, for example, three good semiconductor chips 2.

After the second dicing step, as shown in FIGS. 13A and 13B, a non-defective chip block CB1 is placed in a state where the main surface thereof faces upward, as described above. Mounting on module substrate 6 (mounting step 103
b).

FIGS. 13A and 13B show a case where two non-defective chip blocks CB 1 integrally including two non-defective semiconductor chips 2 are mounted on the module substrate 6. .

The two non-defective chip blocks CB1
May be obtained from the same chip block CB (see FIG. 3 and the like) or may be obtained from one different chip block CB. Note that FIG.
FIGS. 8A and 8B correspond to FIGS. 8A and 8B, respectively.

Subsequently, after the non-defective chip block CB1 is mounted on the module substrate 6, as shown in FIG.
The bonding pads 3BP1 of each semiconductor chip 2 of each chip block CB1 are electrically connected to the bonding pads 6BP1 of the module substrate 6 by bonding wires 8a, and the other bonding pads 6BP2 of the module substrate 6 are bonded to the leads 7b. They are electrically connected by wires 8b. Thereby, the semiconductor chip 2 and the leads 7b are electrically connected.

Here, the first embodiment has a structure in which the bonding pads 3BP1 of the semiconductor chip 2 and the bonding pads 6BP1 of the module substrate 6 are connected by bonding wires 8a.

For this reason, the position of the bonding pad 3BP1 of the semiconductor chip 2 and the corresponding module substrate 6
Even if the position with respect to the bonding pad 6BP1 is slightly shifted due to the change to the mounting method for mounting the two chip blocks CB1, the positional shift can be flexibly handled by changing the wire length or the like. Therefore, 2
It is not necessary to recreate the module substrate 6 just because the method has been changed to the method of mounting the chip blocks CB1.

Thereafter, the mounted chip block CB1
15 (a) and (b), after sealing with a package 9 made of, for example, epoxy resin or the like (step 104), the leads 7b are cut from the lead frame 7,
Further, the portion of the lead 7b protruding from the package 9 is formed into, for example, a gull wing shape, and the manufacture of the DRAM module is completed. 15A and 15B are cross-sectional views taken along lines XVA-XVA and XVB-XVB in FIG. 14, respectively.

As described above, according to the first embodiment, the following effects can be obtained.

(1) A chip block CB integrally including four semiconductor chips 2 is cut out from the semiconductor wafer 1, and the chip block CB is housed in one carrier 4 and transported, whereby a plurality of chip blocks CB are transported. Semiconductor chip 2
Can be transported as one chip block CB, instead of being transported separately.

(2) According to the above (1), the handling of the semiconductor chip 2 in the manufacturing process of the DRAM module becomes easy, and the transport of the semiconductor chip 2 in the manufacturing process of the DRAM module becomes easy.

(3) The handling of the semiconductor chip 2 in the manufacturing process of the DRAM module is facilitated, and the manufacturing process of the DRAM module can be greatly simplified.

(4) According to the above (1), the manufacturing time of the DRAM module can be greatly reduced.

(5). After a chip block CB integrally including four semiconductor chips 2 is cut out from the semiconductor wafer 1, the chip block CB is accommodated in one carrier 4 and transported, thereby obtaining a DRAM module. Since the number of expensive carriers 4 used in the manufacturing process can be significantly reduced, the price of the DRAM module can be reduced.

(6). After a chip block CB integrally including four semiconductor chips 2 is cut out from the semiconductor wafer 1, the chip block CB is transported in a state accommodated in one carrier 4, and For each block,
When four semiconductor chips 2 in the chip block CB are simultaneously inspected, if all the semiconductor chips 2 in the chip block CB are determined to be non-defective, or if a plurality of semiconductor chips 2 in the chip block CB are When it is determined that the chip block is non-defective, the chip block CB, CB1 can be handled as one non-defective chip block CB, CB1 in a subsequent manufacturing process.
That is, a plurality of non-defective semiconductor chips 2 can be collectively handled as one non-defective chip block CB, CB1, so that non-defective semiconductor chips 2 can be easily handled and the price can be reduced.

(7) In the above (6), by using the non-defective chip blocks CB and CB1 at the time of manufacturing the DRAM module, the manufacturing process of the module can be simplified and the manufacturing time can be greatly reduced. Can be shortened.

(8) After a chip block CB integrally including four semiconductor chips 2 is cut out from the semiconductor wafer 1, each semiconductor chip 2 in the chip block CB is simultaneously inspected for each chip block CB. And further mounting the chip block CB on the mounting board as it is,
When manufacturing the DRAM module by packaging the mounted chip block CB,
The heat treatment may be performed by placing one good chip block CB on the module substrate 6 and the heat treatment may be facilitated. Therefore, when the individual semiconductor chips 2 are separately mounted on the module substrate 6 and the heat treatment is performed. Compared to the DRA
The manufacturing process of the M module can be facilitated, and the manufacturing process can be simplified.

(9) According to the above (8), the price of the DRAM module product can be reduced.

(10) According to the above (8), the manufacturing time of the DRAM module can be greatly reduced.

(11) Since the chip block CB integrally including the four semiconductor chips 2 is sealed in the package 9, compared with the case where the individual semiconductor chips 2 are separately mounted and sealed, It is possible to promote downsizing of the DRAM module.

(12) According to the above (11), it is possible to promote downsizing of an electronic device having a DRAM module.

(13) According to the above (11), the wiring length between the adjacent semiconductor chips 2 can be shortened, so that the high-speed performance of each semiconductor chip 2 can be brought out without impairing the whole DRAM module. So its DRAM
It is possible to promote the operation speed of the entire module.

(14) According to the above (11), the wiring length between the adjacent semiconductor chips 2 can be shortened, so that the influence of noise and the like can be reduced. Further, since the heat transfer path can be shortened, it is possible to suppress deterioration of element characteristics due to heat during operation of the DRAM module. Therefore, the operation reliability of the DRAM module can be improved.

(Embodiment 2) FIG. 16 is an explanatory view for explaining a second dicing step in a manufacturing process of a semiconductor device according to another embodiment of the present invention, and FIG. 17 is a plan view of a main part of the semiconductor device. FIG. 18 (a) shows the XVIIIA-XVII of FIG.
FIG. 18B is a cross-sectional view taken along line IA, and FIG.
It is sectional drawing of a line.

In the first embodiment described above, the case where one chip block is further divided into one or two chip blocks in the second dicing step of FIG. 1 has been described. In the second dicing step 103a of FIG. 1, as shown in FIG. 16, all four semiconductor chips 2 of one good chip block CB are divided into pieces.

The method of mounting the semiconductor chip 2 on the module substrate 6 is the same as that of the first embodiment, and the description is omitted. FIG. 17 shows a plan view of the DRAM module in this case. FIG. 17 does not show a package for easy viewing of the drawing. FIGS. 18A and 18B are cross-sectional views taken along lines XVIIIA-XVIIIA and XVIIIB-XVIIIB in FIG. 17, respectively.

On the module substrate 6, four non-defective semiconductor chips 2 are mounted in a separated state. The semiconductor chip 2 may be cut out from the same chip block CB, or may be cut out from a different chip block CB.

Also in the second embodiment, the bonding pads 3BP1 of the semiconductor chip 2 and the bonding pads 6BP1 of the module substrate 6 are connected to the bonding wires 8a.
It is structured to be connected by.

Therefore, even if the positions of the bonding pads 3BP1 of the semiconductor chip 2 and the corresponding positions of the bonding pads 6BP1 of the module substrate 6 are slightly shifted due to the change to the method of mounting the individual semiconductor chips 2, The displacement can be flexibly dealt with by changing the wire length or the like. Therefore, the module board 6 is newly added because the method has been changed to the method of mounting the four non-defective semiconductor chips 2 in a separated state. No need to rebuild.

In the second embodiment, it is possible to obtain the same effect as that obtained in the first embodiment.

(Embodiment 3) FIG. 19 is a plan view of a main part of a semiconductor device according to another embodiment of the present invention, and FIG.
FIG. 20 is a sectional view taken along line XXA-XXA in FIG. 19, and FIG.
20 is a sectional view taken along line XXB-XXB in FIG.

The DRAM module according to the third embodiment has
As shown in FIGS. 19 and 20, each semiconductor chip 2 of the non-defective chip block CB is bonded to the bonding pad of the module substrate 6 via the bump electrode 10 to electrically connect the semiconductor chip 2 and the lead 7b. It has a structure to connect to.

The leads 7b and the bonding pads 6BP2 of the module substrate 6 are electrically connected by bonding wires 8b. However, the bonding structure between the lead 7b and the bonding pad 6BP2 of the module substrate 6 is not limited to this, and may be a structure in which they are bonded by bump electrodes.

In the third embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained.

(1) By bonding each semiconductor chip 2 of the non-defective chip block CB to the bonding pad of the module substrate 6 via the bump electrode 10, the semiconductor chip 2 is bonded to the bonding pad of the semiconductor chip 2 on the module substrate 6. Since the bonding pads can be arranged in the chip mounting area, the module substrate 6 can be reduced in size.

(Embodiment 4) FIG. 21 is a plan view of a main part of a semiconductor device according to another embodiment of the present invention, and FIG.
FIG. 22 is a sectional view taken along the line XXIIA-XXIIA in FIG.
(B) is a sectional view taken along line XXIIB-XXIIB in FIG.

In the fourth embodiment, a case where the non-defective chip block CB1 (see FIG. 12 and the like) described in the first embodiment is hermetically sealed as shown in FIGS. 21 and 22 will be described. . Note that a cap is not shown in FIG. 21 to make the drawing easier to see.

The package base 11a is made of, for example, ceramic, and a module substrate 6 is mounted at the center thereof. The configuration of the module substrate 6 is the same as that of the first embodiment.
Is the same as However, here, a plurality of bonding pads 6BP2 are arranged in the vicinity of the four sides of the module substrate 6 along the outer periphery.

On the main surface of the module substrate 6, two sets of chip blocks CB1 are arranged side by side in the width direction. The bonding pad 3BP1 of each semiconductor chip 2 of each chip block CB1 is connected to a bonding wire 8a.
Pad 6BP1 of module substrate 6 through
Is electrically connected to

The bonding pads 6BP2 of the module substrate 6 are electrically connected to the lead terminals 11b arranged so as to surround the outer periphery of the module substrate 6 on the package base 11a through bonding wires 8b.

The lead terminals 11b are electrically connected to a plurality of lead pins 11c regularly arranged on the outer periphery of the back surface of the package base 11a through internal wiring formed in the package base 11a.

A frame 11d surrounding the outer periphery of the module substrate 6 is joined to the main surface of the package base 11a. A cap 11e is placed on the frame 11d.
Are joined. Thereby, the chip block CB1
Are hermetically sealed. Note that both the frame 11d and the cap 11e are made of, for example, ceramic.

In the fourth embodiment, the same effects as in the first embodiment can be obtained.

(Embodiment 5) FIGS. 23 and 24 are flowcharts showing a manufacturing process of a semiconductor device according to another embodiment of the present invention, FIG. 25 is a plan view of a semiconductor wafer before a dividing process, and FIGS. 27 is a plan view of the sub-wafer after the dividing step, FIG.
And FIG. 28 is a plan view of the sub-wafer after the dividing step and illustrating the marks written thereon,
29 and 30 are enlarged plan views of a main part of the sub-wafer after the dividing step and illustrating another example of the mark written thereon, and FIG. 31 is a plan view of the semiconductor wafer before the dividing step. 32 is a plan view of the sub-wafer after the dividing step, FIG. 33 is a plan view of a jig for transporting the sub-wafer, and FIG.
4 is a cross-sectional view taken along line AA in FIG. 33, FIGS. 35 to 38 are plan views for explaining a modification of the jig for transporting the sub-wafer,
39 is a plan view of the semiconductor wafer before the dividing step, FIG. 40 is a plan view of the sub-wafer after the dividing step, FIG. 41 is a plan view of a jig for transporting the sub-wafer of FIG. 40, and FIG.
FIG. 43 is a plan view of the semiconductor wafer before the dividing step, FIG. 44 is a plan view of the sub-wafer after the dividing step, FIG. 45 is a plan view of a jig for transporting the sub-wafer, and FIG.
It is sectional drawing of the AA of 5 of FIG.

The method of manufacturing a semiconductor device according to the fifth embodiment includes a step of dividing a semiconductor wafer into a plurality of sub-wafers (equivalent to chip blocks) and transporting the divided wafers.
That is, in the fifth embodiment, as shown in FIG.
A semiconductor device is manufactured through a pre-process 201, a probe inspection process 202, a sub-wafer cutting process 203, a first transfer process 204, a dicing process 205, a second transfer process 206, and an assembly process 207 in this order.

Since the pre-process 201 is the same as in the first to fourth embodiments, the description is omitted. Probe inspection process 202
Is a step in which a probe is applied to each of the plurality of semiconductor chips formed on the semiconductor wafer in the previous step 201 to perform an electrical test of each semiconductor chip. The sub-wafer cutting step 203 is a step of dividing a semiconductor wafer into a plurality of sub-wafers. A plurality of semiconductor chips are formed on the sub-wafer. That is, the sub-wafer is
It corresponds to the chip block of the first to fourth embodiments, and has a plurality of semiconductor chips integrally.

The first transfer step 204 is a step in which the semiconductor wafer is transferred while being divided into sub-wafers. That is, in the fifth embodiment, even if the semiconductor wafer has a large diameter of, for example, about 8 inches, the semiconductor wafer can be transported in a divided and small state. This makes it easier to handle the semiconductor wafer in the transfer process. In addition, it is possible to suppress the occurrence of defects such as cracks and defects in the semiconductor wafer transfer process. Furthermore, a large-diameter semiconductor wafer can be handled without a significant change in equipment and devices in a subsequent process.

The dicing step 205 corresponds to the second dicing step in the first to fourth embodiments. Here, the sub-wafer may be divided into a plurality of semiconductor chips, or may be divided into one or more semiconductor chips and one or more chip blocks having a plurality of semiconductor chips. Alternatively, it may be divided into a plurality of chip blocks having a plurality of semiconductor chips.

Prior to the dicing step 205, a sub-wafer back surface polishing step may be introduced. Normally, the thickness of the semiconductor chip is set by polishing the back surface of the semiconductor wafer at the stage of the semiconductor wafer. For this reason, only semiconductor chips of the same thickness can be obtained from one semiconductor wafer.
Even if a semiconductor chip having a different thickness is required for a product type or manufacturing reason, it cannot be responded to.
In the fifth embodiment, the back surface is polished at the stage of the sub-wafer. At this time, the polishing amount of the back surface is changed for each sub-wafer according to the required thickness of the semiconductor chip. This makes it possible to obtain semiconductor chips or chip blocks having different thicknesses from one semiconductor wafer.

The second transporting step 206 is a step of transporting the semiconductor chips or chip blocks divided from the sub-wafer through the dicing step. In this case, a plurality of semiconductor chips are transported in a single transport jig. In addition, the chip blocks may be individually conveyed, or a plurality of chip blocks may be conveyed in a single jig.

The assembling step 207 is a step of sealing a semiconductor chip or a chip block after mounting it on a mounting board. These steps are described in the first to third embodiments.
4, the description is omitted.

As shown in FIG. 24, the order of the sub-wafer cutting step 202a and the probe inspection step 203a may be reversed from that in FIG. Other steps are the same as those in FIG. The contents of the sub-wafer cutting step 202a and the probe inspection step 203a are shown in FIG.
This is the same as described in 3. However, in the probe inspection step 203a, a probe inspection is performed for each sub-wafer. As a result, even if the semiconductor wafer itself has a large diameter, the sub-wafer smaller than the semiconductor wafer is handled in the probe inspection, so that the probe inspection is easy. The semiconductor wafer can be prevented from cracking or losing during probe inspection. Probe inspection can be performed without significant changes in probe inspection equipment and devices. By inspecting a plurality of sub-wafers in the same step and a plurality of semiconductor chips in each sub-wafer in the same step, the inspection time can be reduced.

Next, a specific example of division of the semiconductor wafer according to the fifth embodiment will be described. FIG. 25 and FIG. 26 show an example thereof. The grid-like broken line in FIG. 25 indicates a dividing line. FIG. 26 shows the sub-cut steps 203 and 20.
The sub-wafer (corresponding to a chip block) SW after 3a is shown. The sub-wafer SW includes a plurality of semiconductor chips 2
have. FIG. 26 shows a state where the semiconductor wafer 1 is divided into nine sub-wafers, but the present invention is not limited to this.

Each sub-wafer SW is provided with a mark indicating information on the sub-wafer. This mark describes information such as a lot number, a serial number in the lot, a product type, and a position of a sub-wafer in a semiconductor wafer. By attaching such a mark,
An effect is obtained such that the defect can be easily tracked. An example of the mark is shown in FIGS. FIG. 27 shows an example in which a notch mark M1 is provided on the outer periphery of the sub-wafer SW. The mark M1 is provided, for example, during the sub-wafer cutting steps 203 and 203a. FIG.
Is an example in which a bar code mark M2 is provided near the outer periphery of the sub-wafer SW. The mark M2 may be formed by a laser after the previous process, or may be formed at the time of a photolithography process for forming a predetermined pattern in the previous process. FIG. 29 shows an example in which a bar code mark M3 is attached to the cutting area of the semiconductor wafer. FIG.
0 indicates that the sub-wafer is to be cut into chip blocks CB.
And a mark M5 for a chip block CB. The mark M4 for the sub-wafer SW is provided in a cutting area outside the area of the chip block CB. The mark M5 for the chip block CB is
It is provided in the cutting area in the area B. Both marks M4 and M5 are based on bar code display. However, the mark M5 for the chip block CB may be used as the mark M4 for the sub-wafer SW.

FIGS. 31 and 32 show another example of dividing the semiconductor wafer. 31 shows a dividing line, and FIG. 32 shows a sub-wafer cutting step 203,
The sub-wafer SW after 203a is shown. here,
The semiconductor wafer 1 is divided into two planar arc-shaped sub-wafers SW.
And three sub-wafers SW including one planar rectangular sub-wafer SW. Such a sub-wafer SW
FIGS. 33 and 34 show an example of a jig used for carrying the wafer. FIG. 34 is a sectional view taken along line AA of FIG.

The transfer jig 12 is made of, for example, a fluorine-based resin, and has a rectangular planar shape, for example. Pins 12a are fixed to the sub-wafer receiving surface of the transfer jig 12 so as to project perpendicularly to the surface. The pins 12a are made of, for example, a fluorine-based resin, and have a function of positioning the sub-wafer SW at a predetermined position on the sub-wafer receiving surface and holding the sub-wafer SW so as not to move during transfer. When the transport jigs 12 are stacked in the thickness direction, the height of the pins 12a is
Is slightly lower so that the bottom surface does not touch. When the transfer jigs 12 are provided in multiple stages, the overall shapes and sizes of the transfer jigs 12 are the same. This makes it possible to use common transport equipment. In this case, in order to hold the sub-wafers SW having different shapes, the way of arranging the pins 12a in a plane is changed.
A mark is attached to a predetermined position of the transfer jig 12 so that the production control of the sub-wafer SW accommodated in the transfer jig 12 can be performed. An accommodation state of the SW is shown.

Although the pins 12a are fixed in the above-described transport jig 12, they may be detachable. In this case, as shown in FIG. 35, a plurality of pin insertion holes 12d are provided on the sub-wafer receiving surface of the transfer jig 12. The pin insertion holes 12d are hatched to make the drawing easier to see. Then, the way of arranging the pins 12a in a plane is changed according to the plane shape of the sub-wafer SW. For example, FIG. 36 shows a case where a planar circular arc-shaped sub-wafer SW is housed. Also, for example, FIG.
In FIG. 32, a flat rectangular sub-wafer S at the center of FIG.
The case where W is stored is shown. Further, for example, FIG.
26 shows a case where a plurality of sub-wafers SW in FIG. 26 are accommodated. With such a structure, a single transfer jig 12 can cope with a plurality of types of planar wafers SW. That is, it is not necessary to manufacture the transfer jig 12 for each planar shape of the sub-wafer SW. Therefore, the ease of manufacturing the transport jig 12 can be improved, and mass production is possible.

FIGS. 39 and 40 show another example of dividing the semiconductor wafer. The broken line in FIG. 39 shows the dividing line, and FIG. 40 shows the sub-wafer cutting steps 203 and 20.
The sub-wafer SW and the semiconductor chip 2 after 3a are shown. Here, the sub-wafer cutting steps 203, 203
a, the semiconductor wafer 1 is divided into a plurality of sub-wafers S.
W and a plurality of semiconductor chips 2. Here, the sub-wafer SW may be exactly the same as the chip block CB described in the first to fourth embodiments and the like, and a detailed description thereof will be omitted. An example of a jig used for carrying such a sub-wafer SW is shown in FIGS. In addition,
FIG. 42 is a sectional view taken along line AA of FIG.

The constituent material and the planar shape of the transfer jig 12 are the same as those described above, and the description is omitted. Here, the sub-wafer receiving surface of the transfer jig 12 is divided for each sub-wafer SW. The sub-wafer SW is held in point contact so as not to be broken or damaged during the transfer of the sub-wafer SW. Also in this case, the transport jigs 12 have a structure that can be stacked in multiple layers in the thickness direction.

FIGS. 43 and 44 show another example of dividing the semiconductor wafer. The broken line in FIG. 43 shows the dividing line, and FIG.
The sub-wafer SW after 03a is shown. Here, all of the plurality of sub-wafers SW are formed in the same planar shape (for example, a square shape). Note that the sub-wafer SW here is not limited to a planar square shape, and can be variously changed. Further, among the plurality of sub-wafers SW,
The corners of the sub-wafer SW arranged at the four corners may be rounded except for the outer periphery of the semiconductor wafer 1.

FIGS. 45 and 46 show an example of a jig used for carrying such a sub-wafer SW. Note that FIG.
FIG. 46 is a sectional view taken along line AA of FIG. 45. The constituent material, planar shape and structure of the transport jig 12 are substantially the same as those described with reference to FIGS. The difference is that fine projections 12e are provided on the bottom surface in each accommodation region of each sub-wafer SW, and the sub-wafer SW is held on the projections 12e by point contact. Here, since the planar shape of the plurality of divided sub-wafers SW is the same or substantially the same, there is no need to prepare a plurality of types of transfer jigs 12 according to the planar shape of the sub-wafers SW. What is necessary is just to prepare the conveyance jig 12. In the above-described examples (FIGS. 33 to 38, FIG. 41, FIG. 42, FIG. 45, and FIG. 46), the case where all the planar shapes of the transport jigs 12 are square is described. It may be a round shape instead of a thing.

According to the fifth embodiment, in addition to the effects obtained in the first to fourth embodiments, the following effects can be obtained.

(1) The large-diameter semiconductor wafer 1 can be divided and transported in a small size.
Can be easily handled in the transfer step. Therefore, it is possible to cope with an increase in the diameter of the semiconductor wafer 1. Therefore, the diameter of the semiconductor wafer 1 can be increased.

(2) Since the large-diameter semiconductor wafer 1 can be divided and transported in a small size, it is possible to suppress the occurrence of defects such as cracks and defects during the transportation of the large-diameter semiconductor wafer 1. It becomes possible. Therefore, the yield and reliability of the semiconductor device can be improved, and the cost of the semiconductor device can be reduced.

(3) Since the large-diameter semiconductor wafer 1 can be divided and transported in a small size, large-sized semiconductor wafers 1 can be transported without significant changes in transport equipment and equipment (for example, dicing equipment) in a later process. The semiconductor wafer 1 having a diameter can be handled. For this reason, with the increase in the diameter of the semiconductor wafer 1, it is possible to cope with a small design change without introducing new equipment or dedicated equipment or the like, so that the cost of the semiconductor device can be reduced.

(4) The large-diameter semiconductor wafer 1 is divided and reduced in size, and then a probe inspection is performed, so that the large-diameter semiconductor wafer 1 can be handled without a significant change in a probe inspection device or the like. Becomes possible. For this reason, as the diameter of the semiconductor wafer 1 increases, it is possible to cope with a small design change or the like without introducing a new probe inspection device or the like, so that the cost of the semiconductor device can be reduced.

(5) By polishing the back surface for each sub-wafer SW, the thickness can be changed for each sub-wafer SW, so that semiconductor chips 2 having different thicknesses can be obtained from one semiconductor wafer 1. Becomes Therefore, even when the thickness of the semiconductor chip 2 needs to be changed, it is possible to cope with it.

(Embodiment 6) FIG. 47 is a plan view of a semiconductor wafer used in a method of manufacturing a semiconductor device according to another embodiment of the present invention.

In the sixth embodiment, as shown in FIG.
This is an example of a case where the semiconductor wafer 1a itself is provided in advance with a structure that allows for division into a plurality of sub-wafers. That is, the cutting area between the adjacent sub-wafers is formed wider than the cutting area between the semiconductor chips in the sub-wafer, and the structure is easily divided into the sub-wafers. The manner of division is the same as that shown in FIGS. 25 and 26 used in the description of the fifth embodiment, and a description thereof will be omitted.

In the sixth embodiment, in addition to the effects obtained in the first to fifth embodiments, the semiconductor wafer 1a is provided in advance with a structure that allows for division into sub-wafers. Wafer cutting process 203, 2
03a can be easily divided.

As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say,

For example, in the first to third embodiments,
The case where a package in which the lead shape is formed in a gull-wing shape is used has been described. However, the present invention is not limited to this. For example, a package in which outer leads are formed in a J-shape may be used.

Further, in the second embodiment, the case has been described where the module is configured by using individually separated semiconductor chips. However, the present invention is not limited to this, and one separated semiconductor chip may be used. May be applied to the manufacture of an ordinary semiconductor device in which the semiconductor device is stored in one package.

In the above description, the invention made mainly by the present inventor is described in terms of the DRA which is the application field in which the background was used.
The case of applying to the M module technology has been described,
The present invention is not limited to this. For example, SRAM (Stat
The present invention can be applied to other memory modules such as an IC (Random Access Memory) and other semiconductor devices such as a microprocessor.

[0140]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the method of manufacturing a semiconductor device of the present invention, after a chip block integrally having two or more semiconductor chips is cut out from a semiconductor wafer, the chip block is housed in one jig. By transporting
Since two or more semiconductor chips can be conveyed as one chip block instead of being individually conveyed, handling of the semiconductor chips during the conveyance is facilitated, and the semiconductor chip during the manufacturing process of the semiconductor device is manufactured. The chip can be easily transported.

(2) According to the method of manufacturing a semiconductor device of the present invention, after a chip block integrally having two or more semiconductor chips is cut out from a semiconductor wafer, the chip block is housed in one jig. By transporting
Since two or more semiconductor chips can be transported as one chip block instead of being individually transported, handling of the semiconductor chips at the time of transport becomes easy, and the manufacturing process of the semiconductor device is greatly reduced. This can be simplified.

(3) According to the method of manufacturing a semiconductor device of the present invention, after a chip block integrally having two or more semiconductor chips is cut out from a semiconductor wafer, the chip block is housed in one jig. By transporting
Since two or more semiconductor chips can be transported at once as one chip block instead of being transported separately, the manufacturing time of the semiconductor device can be significantly reduced.

(4) According to the method of manufacturing a semiconductor device of the present invention, after a chip block integrally having two or more semiconductor chips is cut out from a semiconductor wafer, the chip block is housed in one jig. By transporting
Since the number of expensive jigs used in the semiconductor device manufacturing process can be significantly reduced, the price of the semiconductor device can be reduced.

(5) According to the method of manufacturing a semiconductor device of the present invention, after a chip block integrally having two or more semiconductor chips is cut out from a semiconductor wafer, the chip block is housed in one jig. If all the semiconductor chips in the chip block are judged to be non-defective by inspecting two or more semiconductor chips in the chip block simultaneously for each chip block, or If a plurality of semiconductor chips in the block are determined to be non-defective, the chip block can be handled as one non-defective chip block in a subsequent manufacturing process. That is,
Since non-defective semiconductor chips can be collectively handled as one non-defective chip block, non-defective semiconductor chips can be easily handled and the price can be reduced.

(6) In the above (5), when manufacturing a module product constituting one semiconductor device by a plurality of semiconductor chips, by using the non-defective chip block, the manufacturing process of the module product is facilitated. And the manufacturing time can be greatly reduced.

(7) According to the method of manufacturing a semiconductor device of the present invention, after a chip block integrally having two or more semiconductor chips is cut out from a semiconductor wafer, each chip block is divided into chips in the chip block. By simultaneously inspecting two or more semiconductor chips, further mounting the chip block on a mounting board as it is, and packaging the mounted chip block,
When manufacturing a module product that constitutes one semiconductor device by a plurality of semiconductor chips, one chip block may be placed on a mounting substrate and heat-treated, and the handling is facilitated. , The manufacturing process of the semiconductor device can be simplified, and the manufacturing process can be simplified.

(8) According to the above (7), it is possible to reduce the price of a module product in which a plurality of semiconductor chips constitute one semiconductor device.

(9) According to the method of manufacturing a semiconductor device of the present invention, after a chip block integrally having two or more semiconductor chips is cut out from a semiconductor wafer, each of the chip blocks is cut in the chip block. By simultaneously inspecting two or more semiconductor chips, further mounting the chip block on a mounting board as it is, and packaging the mounted chip block,
When manufacturing a module product that constitutes one semiconductor device by a plurality of semiconductor chips, one chip block may be placed on a mounting substrate and heat-treated, and the handling is facilitated. Can be greatly reduced as compared with the case where the semiconductor devices are separately mounted and heat-treated.

(10) According to the method of manufacturing a semiconductor device of the present invention, a large-diameter semiconductor wafer can be divided and transported in a small size, which facilitates handling of the semiconductor wafer in the transporting step. It becomes possible. Therefore, it is possible to cope with an increase in the diameter of the semiconductor wafer. Therefore, it is possible to promote the increase in the diameter of the semiconductor wafer.

(11) According to the method of manufacturing a semiconductor device of the present invention, a large-diameter semiconductor wafer can be divided and transported in a small size. And the like can be suppressed from occurring. Therefore, the yield and reliability of the semiconductor device can be improved, and the cost of the semiconductor device can be reduced.

(12) According to the method of manufacturing a semiconductor device of the present invention, a large-diameter semiconductor wafer can be divided and transported in a small size, which requires a significant change in equipment and the like in a later process. And a semiconductor wafer having a large diameter can be handled. For this reason, with the increase in the diameter of the semiconductor wafer, it is possible to cope with a small design change without introducing a new facility or a dedicated facility or the like, so that the cost of the semiconductor device can be reduced.

(13) According to the semiconductor device of the present invention, a chip block integrally having two or more semiconductor chips is sealed in a package, so that individual semiconductor chips are separately mounted and sealed. It is possible to promote downsizing of the semiconductor device as compared with the case where the semiconductor device is used.

(14) According to the above (13), it is possible to promote downsizing of an electronic device having a module product in which a plurality of semiconductor chips constitute one semiconductor device.

(15) According to the above (13), the wiring length between adjacent semiconductor chips can be shortened, and the high-speed performance of each semiconductor chip can be brought out without impairing the entire semiconductor device. It is possible to promote the operation speed of the entire semiconductor device.

(16) According to the above (13), the wiring length between adjacent semiconductor chips can be shortened, so that the influence of noise and the like can be reduced. Further, since the heat transfer path can be shortened, deterioration of element characteristics due to heat during operation of the semiconductor device can be suppressed.
Therefore, the operation reliability of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor wafer after a pre-process of FIG. 1;

FIG. 3 is a plan view of the chip block after a first dicing step of FIG. 1;

FIG. 4 is a perspective view of a carrier used in the method for manufacturing the semiconductor device of FIG. 1;

5 is a cross-sectional view of the carrier of FIG. 4 taken along line VV.

FIG. 6 is a perspective view of a socket used in an inspection process which is a manufacturing process of the semiconductor device of FIG. 1;

7 is a plan view of a mounting board used in a manufacturing process of the semiconductor device of FIG. 1 and a lead frame on which the mounting board is mounted.

FIGS. 8A and 8B are cross-sectional views of main parts of the semiconductor device during a step of mounting a chip block on the mounting board of FIG. 7;

9 is a fragmentary plan view of the semiconductor device in a manufacturing step following that of FIG. 8 of the manufacturing step of the semiconductor device in FIG. 1;

10A is a sectional view taken along line XA-XA in FIG.
FIG. 10B is a sectional view taken along line XB-XB in FIG. 9.

11A and 11B are cross-sectional views of main parts of the semiconductor device in a manufacturing step following the step shown in FIG. 9 for manufacturing the semiconductor device in FIG. 1;

FIGS. 12A, 12B, and 12C are explanatory diagrams for explaining chip blocks after the second dicing step in FIG. 1;

13 (a) and 13 (b) are cross-sectional views of main parts of the semiconductor device during a step of mounting the chip block obtained in the step of FIG. 12 on the mounting board of FIG. 7;

14 is a fragmentary plan view of the semiconductor device in a manufacturing step following that of FIG. 13 of the manufacturing step of the semiconductor device in FIG. 1;

15A and 15B are cross-sectional views of main parts of the semiconductor device in a manufacturing step following the step shown in FIG. 14 for manufacturing the semiconductor device in FIG. 1;

FIG. 16 is an explanatory diagram for describing a second dicing step in a process of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 17 is a plan view of relevant parts of a semiconductor device according to another embodiment of the present invention;

18A is a cross-sectional view taken along line XVIIIA-XVIIIA in FIG. 17, and FIG. 18B is a cross-sectional view taken along line XVIIIB-XVIIIB in FIG.

FIG. 19 is a plan view of relevant parts of a semiconductor device according to another embodiment of the present invention;

20A is a sectional view taken along line XXA-XXA in FIG. 19, and FIG. 20B is a sectional view taken along line XXB-XXB in FIG.

FIG. 21 is a plan view of relevant parts of a semiconductor device according to another embodiment of the present invention;

22 (a) is a cross-sectional view taken along line XXIIA-XXIIA in FIG. 21, and FIG. 22 (b) is a cross-sectional view taken along line XXIIB-XXIIB in FIG.

FIG. 23 is a flowchart showing a process of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 24 is a flowchart showing a process of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 25 is a plan view of a semiconductor wafer before a dividing step.

FIG. 26 is a plan view of the sub-wafer after the dividing step.

FIG. 27 is a plan view of the sub-wafer after the dividing step and illustrating the marks written on the sub-wafer.

FIG. 28 is a plan view of the sub-wafer after the dividing step and illustrating another example of a mark written on the sub-wafer.

FIG. 29 is an enlarged plan view of a main part of the sub-wafer after the dividing step, for explaining another example of a mark written on the sub-wafer.

FIG. 30 is an enlarged plan view of a main part of the sub-wafer for explaining another example of a mark written on the sub-wafer after the dividing step.

FIG. 31 is a plan view of a semiconductor wafer before a dividing step.

FIG. 32 is a plan view of the sub-wafer after the dividing step.

FIG. 33 is a plan view of a jig for transporting a sub-wafer.

34 is a sectional view taken along line AA of FIG. 33.

FIG. 35 is a plan view for explaining a modification of the jig for transporting a sub-wafer.

FIG. 36 is a plan view for explaining a case where one sub-wafer of FIG. 26 is accommodated, which is a modification of the jig for transporting sub-wafers.

FIG. 37 is a plan view for explaining a modification of the jig for transporting a sub-wafer, in which another sub-wafer of FIG. 26 is accommodated.

FIG. 38 is a plan view for explaining a modification of the jig for transporting a sub-wafer and accommodating another sub-wafer.

FIG. 39 is a plan view of the semiconductor wafer before a dividing step.

FIG. 40 is a plan view of the sub-wafer after the division step.

FIG. 41 is a plan view of a jig for transferring the sub-wafer of FIG. 40.

42 is a sectional view taken along line AA of FIG. 41.

FIG. 43 is a plan view of a semiconductor wafer before a dividing step.

FIG. 44 is a plan view of the sub-wafer after the dividing step.

FIG. 45 is a plan view of a jig for transporting a sub-wafer.

46 is a sectional view taken along line AA of FIG. 45.

FIG. 47 is a plan view of a semiconductor wafer used in a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 1a Semiconductor wafer 2 Semiconductor chip 3BP1 Bonding pad 4 Carrier (jig) 4a Carrier base part 4a1 Chip block accommodation part 4a2 Opening 4b Carrier lid part 4c Pressing part 4d Press plate 5 Socket 5a Socket base part 5b Socket lid 5c Contact portion 5c1 Contact terminal 6 Module board (mounting board) 6a Chip mounting area 6BP1 bonding pad 6BP2 bonding pad 7 Lead frame 7a Board mounting section 7b Lead (external terminal) 8a, 8b Bonding wire 9 Package 10 Bump electrode 11a Package base 11b Lead terminal 11c Lead pin 11d Frame 11e Cap 12 Transport jig 12a Pin 12b Depression 12c Projection 12d Pin insertion hole 12e Projection CB Chip block CB1 chip Lock SW Sabuueha

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akihiko Ariga 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Hitoshi Nakano Gojokami-cho, Kodaira-shi, Tokyo 20-1 chome Semiconductor Division, Hitachi, Ltd.

Claims (20)

[Claims] 1. A semiconductor device, comprising: when a semiconductor chip is cut from a semiconductor wafer on which a plurality of semiconductor chips are formed, a step of cutting a chip block integrally having two or more semiconductor chips as one unit. Manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of cutting the chip block from a semiconductor wafer and then transporting the chip block in a state of being housed in one jig. Manufacturing method of a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the chip block is cut out from the semiconductor wafer, and then, for each of the chip blocks, two or more semiconductor chips in the chip block are simultaneously processed. A method for manufacturing a semiconductor device, comprising a step of inspecting. 4. The method for manufacturing a semiconductor device according to claim 3, further comprising a step of dividing the chip block into individual semiconductor chips after simultaneously inspecting two or more semiconductor chips in the chip block. A method for manufacturing a semiconductor device. 5. A method for cutting a semiconductor chip from a semiconductor wafer on which a plurality of semiconductor chips are formed, by cutting a chip block integrally having two or more semiconductor chips as one unit, A step of simultaneously inspecting two or more semiconductor chips in the chip block, a step of directly mounting the chip block on a mounting board, and a step of packaging the chip block mounted on the mounting board A method for manufacturing a semiconductor device, comprising: 6. A method for cutting a semiconductor chip from a semiconductor wafer on which a plurality of semiconductor chips are formed, by cutting a chip block integrally having two or more semiconductor chips as one unit, A step of simultaneously inspecting two or more semiconductor chips in a chip block; a step of cutting and removing a semiconductor chip in which a defect is found as a result of the inspection of the chip block; and a step of removing the defective semiconductor chip. And mounting the chip block on the mounting board as it is, and packaging the chip block mounted on the mounting board. 7. The method for manufacturing a semiconductor device according to claim 1, 5 or 6, wherein (a) accommodating a chip block cut out from the semiconductor wafer in one jig.
(B) a step of transporting the jig containing the chip block to an inspection device; (c) a step of mounting the jig containing the chip block on an inspection socket as it is; (d) A step of simultaneously inspecting electrical characteristics of two or more semiconductor chips in the chip block; and (e) a step of removing the chip block together with the jig from the inspection socket after the inspection step and transporting the chip block to a subsequent step. A method for manufacturing a semiconductor device, comprising: 8. A method for manufacturing a semiconductor device, comprising the step of dividing a semiconductor wafer into a plurality of sub-wafers having two or more semiconductor chips and transporting the divided sub-wafers. 9. A step of dividing a semiconductor wafer into a plurality of sub-wafers having two or more semiconductor chips, a step of transporting each of the plurality of sub-wafers, and a step of putting each of the plurality of sub-wafers into a subsequent step And a method of manufacturing a semiconductor device. 10. A step of dividing a semiconductor wafer into a plurality of sub-wafers having two or more semiconductor chips, and a step of forming a mark on each of the plurality of sub-wafers before or after the step of dividing the plurality of sub-wafers. And a step of transferring each of the plurality of sub-wafers; and a step of putting each of the plurality of sub-wafers into a post-process. 11. A method of dividing a semiconductor wafer into a plurality of sub-wafers having two or more semiconductor chips and transporting the plurality of sub-wafers, wherein the plurality of sub-wafers have the same or substantially the same planar shape. A method for manufacturing a semiconductor device. 12. A step of forming a plurality of semiconductor chips on a semiconductor wafer, a step of inspecting a plurality of semiconductor chips on the semiconductor wafer, and dividing the semiconductor wafer into a plurality of sub-wafers having two or more semiconductor chips. And a step of transferring each of the plurality of sub-wafers. 13. A step of forming a plurality of semiconductor chips on a semiconductor wafer, a step of inspecting a plurality of semiconductor chips on the semiconductor wafer, and dividing the semiconductor wafer into a plurality of sub-wafers having two or more semiconductor chips. Performing a step of transferring each of the plurality of sub-wafers, and introducing each of the plurality of sub-wafers to a subsequent step. 14. A step of forming a plurality of semiconductor chips on a semiconductor wafer, a step of inspecting a plurality of semiconductor chips on the semiconductor wafer, and dividing the semiconductor wafer into a plurality of sub-wafers having two or more semiconductor chips. Forming a mark on each of the plurality of sub-wafers before or after the dividing step of the plurality of sub-wafers, transferring each of the plurality of sub-wafers, and rearranging each of the plurality of sub-wafers A method of manufacturing a semiconductor device, comprising the steps of: 15. A step of forming a plurality of semiconductor chips on a semiconductor wafer, a step of dividing the semiconductor wafer into a plurality of sub-wafers having two or more semiconductor chips,
A method of manufacturing a semiconductor device, comprising: after dividing into a plurality of sub-wafers, inspecting each semiconductor chip in the sub-wafer; and transporting each of the plurality of sub-wafers. 16. A step of forming a plurality of semiconductor chips on a semiconductor wafer, dividing the semiconductor wafer into a plurality of sub-wafers having two or more semiconductor chips,
Forming a mark on each of the plurality of sub-wafers, dividing the plurality of sub-wafers, inspecting each semiconductor chip on the sub-wafer, and transporting each of the plurality of sub-wafers A method for manufacturing a semiconductor device, comprising: 17. A step of forming a plurality of semiconductor chips on a semiconductor wafer, a step of dividing the semiconductor wafer into a plurality of sub-wafers having two or more semiconductor chips,
After dividing into the plurality of sub-wafers, inspecting each semiconductor chip in the sub-wafers, transferring each of the plurality of sub-wafers, and putting each of the plurality of sub-wafers into a post-process A method for manufacturing a semiconductor device, comprising: 18. A semiconductor device, comprising: a step of manufacturing a semiconductor wafer having a structure anticipating division into a plurality of subwafers; and a step of dividing and transporting the semiconductor wafer into a plurality of subwafers. Manufacturing method. 19. A mounting board on which a chip block integrally including two or more semiconductor chips, a mounting board on which the chip block is mounted in a bare state, and a wiring for forming a predetermined circuit is formed; A semiconductor device, comprising: a package for sealing a chip block mounted on a mounting substrate; and an external terminal for extracting an electrode of a predetermined circuit formed on the mounting substrate to the outside of the package. 20. A jig used in the method for manufacturing a semiconductor device according to claim 1, wherein a circuit forming surface of the chip block is opposed to an electrode on the circuit forming surface. A base having an opening to be exposed,
A lid disposed on the back side of the chip block, disposed between the lid and the back of the chip block,
A jig for use in a method of manufacturing a semiconductor device, comprising: a pressing portion for pressing the chip block toward a base portion.