JPH11111987A - Manufacture of thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress fluctuations in the threshold of a thin-film transistor which is caused by unanticipated impurity ions diffusing into a channel section through ion doping. SOLUTION: A gate electrode 23, a silicon nitride film 24, a silicon oxide film 25, and a silicon film 26 are formed on a transparent substrate 21. Then, a resist mask 30 is formed on the silicon film 26, and a stopper insulating film 28 is formed by performing exposure from the rear surface side of the substrate 21. After the insulating film 28 has been formed, a low-concentration drain region 26a having an LDD structure is formed by implanting an N-type impurity by the ion-doping method, while the mask 30 is left on the insulating film 28. Finally, a source region 26s and a drain region 26d are formed by doping the silicon film with an N-type impurity by using a newly formed resist mask 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor (TFT) used as a pixel driving element of a liquid crystal display device or the like.

[0002]

2. Description of the Related Art FIGS. 4 and 5 are sectional views showing steps of a method of manufacturing a bottom gate type thin film transistor used as a switching element for display of a liquid crystal display panel. (A) First Step A high melting point metal film such as chromium or molybdenum is sputtered on the insulating transparent substrate 1 to form a high melting point metal film.
The refractory metal film is patterned into a predetermined pattern to form the gate electrode 2 (see FIG. 4A). (B) Second Step A silicon nitride film and a silicon oxide film 4 are formed on the transparent substrate 1 by covering the gate electrode 2 with silicon nitride and silicon oxide sequentially by a plasma CVD method. Similarly, silicon is stacked on the silicon oxide film 4 by a plasma CVD method to form an amorphous silicon film 5. Then, the silicon film 5 is irradiated with an excimer laser and heated until the amorphous silicon is melted. This allows
Silicon is crystallized to be in a polycrystalline state. This polycrystalline silicon film 5 becomes an active layer of the transistor (see FIG. 4B). (C) Third Step A silicon oxide is stacked on the silicon film 5 to form a silicon oxide film. Then, the silicon oxide film is patterned according to the gate electrode 2 to form a stopper insulating film 6 overlapping the gate electrode 2 (see FIG. 4C). (D) Fourth Step The silicon film 5 on which the stopper insulating film 6 is formed is ion-doped with phosphorus using the stopper insulating film 6 as a mask. In this doping, doping with a relatively low impurity concentration is performed, and the region covered with the stopper insulating film 6 becomes the channel region 5c of the thin film transistor (FIG. 4).
(D)). (D) Fifth Step A resist mask 7 covering the stopper insulating film 6 is formed, and phosphorus is ion-doped again. In this injection,
Except for the region covered with the resist mask 7, the silicon film 5
A region having N-type conductivity with a relatively high impurity concentration is formed in the region. These regions become a source region 5s and a drain region 5d on both sides of the gate electrode 2. Except for the area covered with the stopper 6, the area covered with the resist mask 7 becomes the lightly doped drain 5a having the LDD (Lightly Doped Drain) structure. (See FIG. 5A). (E) Sixth step Silicon film 5 into which impurity ions of a predetermined conductivity type have been implanted
Is irradiated with an excimer laser, and heated so that silicon does not melt. Thereby, impurity ions in the silicon film 5 are activated. Then, the silicon film 5 is patterned into an island shape leaving a predetermined width on both sides of the gate electrode 2,
Each transistor is separated and independent (see FIG. 5B). (F) Seventh Step A plasma C is formed by covering the silicon oxide film 4 with the silicon film 5.
Silicon oxide and silicon nitride are stacked again by the VD method, and a silicon oxide film 8 and a silicon nitride film 9 are sequentially formed. Then, a contact hole 10 penetrating the silicon oxide film 8 and the silicon nitride film 9 is formed on the silicon film 5 to be the source region 5s and the drain region 5d (see FIG. 5C). (G) Eighth Step An electrode 11 made of a metal such as aluminum connected to the silicon film 5 is formed in the contact hole 10 (see FIG. 6A). (H) Ninth Step An acrylic resin solution is applied on the silicon nitride film 9 on which the electrodes 11 are formed, and baked to form an acrylic resin layer 12. The acrylic resin layer 12 flattens the surface by filling irregularities due to the stopper insulating film 6 and the electrode 11. And
A contact hole 13 penetrating through the acrylic resin layer 12 is formed on the electrode 11 connected to the source region 5s.
A transparent electrode 14 made of TO or the like is formed. The transparent electrode 14 is formed, for example, by sputtering ITO on the acrylic resin film 11 in which the contact hole 13 is formed.
Is formed by patterning (see FIG. 6B).

[0003]

In the fourth step, phosphorus ion implantation is performed by an ion doping method. This ion doping method is an ion implantation method in which phosphine + hydrogen gas (PH3 + H2) is dissociated in a plasma atmosphere, and the dissociated ions (P−, H +, etc.) are doped into a shower by electrolytic acceleration. Whereas ion implantation, which is widely used in LSIs and the like, selects dissociated ions and dopes the workpiece, ion doping differs greatly in that it has no means for selecting ions. Is a processing method that is exposed to all kinds of dissociated ions.

For this reason, even if the stopper insulating film 6 is given a thickness enough to mask phosphorus ions in the fourth step,
Hydrogen ions (H +) and the like generated by the dissociation penetrate the stopper insulating film 6 and are implanted into a portion of the silicon film 5 to be the channel 5c, and this is injected into the transistor threshold voltage Vt
Had the disadvantage of fluctuating

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and a resist mask for forming a stopper insulating film is left on the stopper insulating film.
It is an object of the present invention to prevent the fluctuation of the threshold value of the transistor due to the entry of the hydrogen ions or the like by performing phosphorus ion doping in the state where the phosphorus ions are left.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. 1 to 3 are cross-sectional views showing steps of a method for manufacturing a bottom gate thin film transistor according to the present invention. (A) First Step On the surface (first main surface) of the insulating transparent substrate 21, a refractory metal such as chromium or molybdenum is sputtered to form a refractory metal film 22 having a thickness of 1000 to 2000 °. . The refractory metal film 22 is patterned into a predetermined pattern to form a gate electrode 23. In this patterning process, the gate electrode 23 is formed in a tapered shape (trapezoidal shape) in which both ends are widened on the transparent substrate 21 side by taper etching using a wet etchant. The gate electrode 23 'shows a contact portion of the electrode wiring when the high melting point metal film 22 is extended on the surface of the transparent substrate 21 to form an electrode wiring (FIG. 1A). reference). (B) Second step The gate electrode 23 is covered on the transparent substrate 21 and the thickness is 500
Silicon nitride of ~ 1500 ° and a thickness of 1000-20
A silicon oxide film of 00 ° is sequentially stacked by a plasma CVD method to form a silicon nitride film 24 and a silicon oxide film 25. Subsequently, silicon having a thickness of 300 to 800 ° is similarly stacked on the silicon oxide film 25 by the plasma CVD method to form an amorphous silicon film 26. 4 in total
By applying a heat treatment of 00 to 500 degrees, excess hydrogen ions contained in the silicon film 26 are removed. Then, the silicon film 26 is irradiated with an excimer laser 27 and heated until the amorphous silicon is melted. Thereby, silicon is crystallized to be in a polycrystalline state. This polycrystalline silicon film 26 becomes an active layer of the thin film transistor (see FIG. 1B). (C) Third Step A silicon oxide film 27 having a thickness of 800 to 1200 ° is laminated on the silicon film 26 to form a silicon oxide film 27. Then, the silicon oxide film 27 is patterned according to the gate electrode 23 to form a stopper insulating film 28 overlapping the gate electrode 23. In forming the stopper insulating film 28, a photoresist film covering the silicon oxide film 27 is formed, and the resist film is exposed from the back side (second main surface side) of the transparent substrate 21 using the gate electrode 23 as an exposure light 29. Irradiation is performed to form a resist mask 30 on the silicon oxide film 27 without a mask shift, and then the silicon oxide film 27 is patterned by an HF wet etchant (see FIG. 1C). (D) Fourth Step A resist mask 30 on which the stopper insulating film 28 is formed is formed on the silicon film 26 on which the stopper insulating film 28 is formed.
Is ion-implanted by an ion doping method while leaving. This is for forming a low-concentration drain portion of an N-channel thin film transistor having an LDD structure, and using phosphine (PH3) as a dopant,
The acceleration voltage is 3 to 10 KeV, and the dose of phosphorus is 1E12.
１1E13 cm−2. The portion covered with the stopper insulating film 28 becomes the channel region 26c of the transistor,
The phosphorus-doped region in this step becomes a low-concentration drain region 26a in a later step.

In this step, since the resist mask 30 has a thickness of 1 to 3 μm, it functions effectively as a selection mask during ion doping. Therefore, it is possible to solve the problem of the conventional problem that the plasma-dissociated hydrogen ions penetrate the stopper insulating film 28 and enter the channel region 26c (see FIG. 2A). (E) Fifth Step The resist mask 30 on the stopper insulating film 28 is removed,
A photoresist is applied again, and this time, exposure is performed from the surface side of the transparent substrate 21 to form a resist mask 31 covering the stopper insulating film 28 and the region to be the low-concentration drain region 26a.
-10 KeV, phosphorus dose is 1E14-1E15c
Ion implantation is performed at m-2. In this ion doping, regions exhibiting N-type conductivity are formed in the silicon film 26 except for the region covered by the resist mask 31, and these regions are formed on both sides of the gate electrode 23 by the source region 26s and the drain region. 26d. Also, the stopper insulating film 2
8 from the portion covered with the resist mask 31 to the portion covered with the resist mask 31.
6a (see FIG. 2B).

When a P-channel thin film transistor is formed on the same transparent substrate 21 for the peripheral circuit, the resist mask 31 is also formed on the silicon film 26 where the P-channel thin film transistor is to be formed in this step.
(Not shown). Then, after this step, the resist mask 31 is removed, a resist mask (not shown) for covering a portion where a new N-channel transistor is formed is formed, and boron ions are ion-doped by using the stopper insulating film 28 as a mask. For ion implantation. This ion implantation has an accelerating voltage of 3 to 10 Ke.
The dose of V and boron is 1E14 to 1E15 cm-2. Thus, P-type source and drain regions are formed in the silicon film 26 on both sides of the gate electrode 23 of the P-channel transistor (not shown). Therefore, the stopper insulating film 28 is required to have a minimum thickness enough to mask boron ions (B +). (F) Sixth step Silicon film 2 into which impurity ions of a predetermined conductivity type have been implanted
6 is irradiated with an excimer laser 32 and heated to such an extent that silicon does not melt. Thereby, impurity ions in the silicon film 26 are activated. Then, the gate electrode 23
The silicon film 26 is patterned into an island shape with a predetermined width left on both sides of the transistor to separate each transistor. The method is as follows. First, after forming a resist mask, the stopper insulating film 28 on the wiring gate electrode 23 'is selectively removed with an HF-based etchant, and then the portion covered with the resist mask by dry etching. This is performed by removing the silicon film 26 other than that shown in FIG. 2 (C).
reference). (G) Seventh Step A plasma C is formed by covering the silicon oxide film 5 with the silicon film 6.
Silicon oxide and silicon nitride are stacked again by the VD method, a silicon oxide film 33 and a silicon nitride film 34 are sequentially formed, and then the silicon oxide film 33 and the silicon nitride film 34 are annealed by heat treatment at 350 to 450 degrees. This heat treatment also serves to simultaneously diffuse hydrogen ions contained in the silicon nitride film 34 into the silicon film 26 through the silicon oxide film 33. The diffused hydrogen ions neutralize and terminate dangling bonds in the silicon film 26. At this time, the supply amount of hydrogen ions is determined by a diffusion equation consisting of the concentration of hydrogen ions contained in the silicon nitride film 34 and the diffusion distance from the silicon nitride film 34 to the stopper insulating film 28 and reaching the silicon film 26. It is determined. If the thickness of the stopper insulating film 28 can be set small, the diffusion distance can be shortened, so that a sufficient amount of hydrogen ions can be supplied to the silicon film 26 in a short time at a low temperature.

Then, a contact hole 35 penetrating the silicon oxide film 33 and the silicon nitride film 34 is formed on the silicon film 26 serving as the source region 26s and the drain region 26d and on the gate electrode 23 'for wiring (FIG. 3).
(A)). (H) Eighth Step In the contact hole 35, an electrode 36 made of a metal such as aluminum connected to the drain region 26d of the silicon film 26 and an electrode 36 connected to the gate electrode 23 'are formed. The electrode 36 is formed, for example, by patterning aluminum sputtered on the silicon nitride film 34 in which the contact hole 35 is formed. Here, the electrode 36 connected to the drain region 26d forms a drain wiring continuously along the transistor arrangement direction. The contact hole 34 on the source region 26s removes the aluminum (FIG. 3).
(B)). (I) Ninth Step An acrylic resin solution is applied on the silicon nitride film 34 on which the electrodes 36 are formed, and baked to form an acrylic resin layer 37. The acrylic resin layer 37 is formed of the stopper insulating film 28
The surface is flattened by filling irregularities due to the electrode 36 and the electrode 36. Then, a contact hole 38 penetrating the acrylic resin layer 37 is formed on the source region 26s, and a transparent electrode 39 made of ITO or the like connected to the source region 26s is formed in the contact hole 38. This transparent electrode 39 is formed, for example, by patterning ITO sputtered on the acrylic resin film 37 in which the contact hole 38 is formed (see FIG. 4).

According to the present embodiment, the following functions and effects can be obtained. (1) Since phosphorus is ion-doped while the resist mask 30 for forming the stopper insulating film 28 is left on the stopper insulating film 28, impurity ions (H +) or the like in the plasma atmosphere erroneously enter the channel region 26c. No more doping. Therefore, variation in the threshold value Vt of the transistor can be suppressed, and the manufacturing yield of the semiconductor device can be improved.

(2) Since the stopper insulating film 28 only needs to have a thickness enough to mask boron ions for forming a p-channel transistor, the stopper insulating film 28
Can be made thinner. This makes it possible to alleviate surface irregularities and shorten the diffusion distance of hydrogen ions in the seventh step, thereby enabling processing in a short time.

[0012]

As described above, according to the present invention, unexpected impurities are prevented from being diffused into the channel region 26c by ion implantation at the time of forming the low concentration drain region 26a in the fourth step. Accordingly, there is an advantage that the variation in the threshold value Vt of the transistor can be suppressed and the manufacturing yield of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a cross-sectional view for explaining a conventional example.

FIG. 5 is a sectional view for explaining a conventional example.

FIG. 6 is a cross-sectional view for explaining a conventional example.

[Explanation of symbols]

 21 ... Transparent substrate 23 ... Gate electrode 26 ... Silicon film 26c ... Channel region 26a ... Low concentration drain region 28 ... Stopper insulating film 29 ... Resist mask 35 ... Electrode 38 ... ..Transparent electrodes

Claims (4)

[Claims] A step of forming a gate electrode on a first main surface of an insulating substrate; a step of forming a gate insulating film covering the gate electrode on the insulating substrate; and a semiconductor film on the gate insulating film. Stacking an insulating film on the semiconductor film; forming a resist mask on the insulating film above the gate electrode; and selectively removing the insulating film with the resist mask. A step of forming a stopper insulating film by sputtering, and a step of doping the semiconductor layer with impurities while leaving the resist mask on the stopper insulating film. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the resist mask is formed by exposing the insulating substrate from the second main surface side using the gate electrode as a mask. A step of forming a gate electrode on the first main surface of the insulating substrate; a step of forming a gate insulating film covering the gate electrode on the insulating substrate; and a semiconductor film on the gate insulating film Stacking an insulating film on the semiconductor film; forming a first resist mask on the insulating film above the gate electrode; and forming the insulating film by the first resist mask. Forming a stopper insulating film by selectively removing, and forming a one-conductivity-type low-concentration region by doping impurities into the semiconductor layer while leaving the first resist mask; Forming a second resist mask covering the semiconductor layer in the vicinity of the stopper and the stopper, and doping impurities into the semiconductor layer to form one-concentration high-concentration source / drain regions. A method of manufacturing the thin film transistor characterized by Rukoto. 4. The method according to claim 3, wherein the formation of the resist mask is performed by exposing the insulating substrate from the second main surface side using the gate electrode as a mask.