JPH11112327A - Logic circuit including CMOS logic circuit - Google Patents

Abstract

(57) Abstract: To increase the speed of a multi-input selection circuit including a CMOS logic circuit and to suppress the through current of the CMOS logic circuit. When an H-level external input line is selected, a rise in the potential of an input line of a CMOS inverter is detected by a voltage level detection means to turn on a p-channel MOS transistor, and an input line is turned on. To the H level. The circuit operation is speeded up without being affected by the load connected to the output line 106a of the CMOS inverter 101, and the CMOS
The time required for the through current to flow through S inverter 101 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic circuit including a CMOS logic circuit, and more particularly to speeding up such a logic circuit and suppressing a through current of the CMOS logic circuit.

[0002]

2. Description of the Related Art As a conventional example of a logic circuit including a CMOS logic circuit, a multi-input selection circuit as shown in FIG. 9 is known. This multi-input selection circuit includes a large number of external input lines 806
Are selectively turned on by a control signal 805 as a MOS transistor 800 inserted in each of them, so that a signal of one external input line 806 can be changed to a CMOS inverter 801 which is a CMOS logic circuit.
, And the signal is shaped by a CMOS inverter 801 and output. A p-channel MOS transistor 802 for correcting a voltage level is connected to an input line 803 of the CMOS inverter 801, and a gate thereof is connected to an output line 804 of the CMOS inverter 801.

If a selected external input line 806 is at the H level, the potential of the input line 803 of the CMOS inverter 801 rises, resulting in the CMOS inverter 80
The potential of one output line 804 decreases. However, since the potential of the input line 803 becomes an intermediate level lower than the H level due to the voltage drop of the MOS transistor 800 inserted into the external input line 806, a so-called through current flows inside the CMOS inverter 801.

Generally, in a CMOS logic circuit including a CMOS inverter 801, a p-channel MOS transistor and an n-channel MOS transistor are connected in series between a power supply and a ground. When the input potential is at the H level or the L level, one of the MOS transistors connected in series is turned on and the other is turned off, so that no through current flows from the power supply to the ground through the series connection. However, when the input potential is at an intermediate level between the H level and the L level,
Both MOS transistors are simultaneously turned on, and a through current flows. In the case of a CMOS logic circuit having a large fan-out which is expected to be connected to a heavy load to some extent, or has a large fan-out used for the purpose of not specifying the type of the connected load in advance, the through current has a considerably large value. This can cause overheating and failure.

Now, when the CMOS inverter 801 operates and its output line 804 falls to a certain voltage level,
P-channel MO connected between input line 803 and power supply
The S transistor 802 turns on, and the input line 803 is pulled up from the intermediate level to the H level. Thus, CMO
Through current of S inverter 801 is suppressed.

[0006]

SUMMARY OF THE INVENTION CMOS inverter 8
The signal waveform becomes dull due to the influence of the ground capacitance C of the input line 803 of No. 01. As the number of external input lines 806 increases, the ground capacitance C increases, and the waveform of the signal becomes dull correspondingly. The delay time until a signal change on the output line 804 increases. Depending on the effect of the load connected to the output line 804,
The signal waveform becomes dull. The degree of the dulling varies depending on the load and is not uniquely determined. As a result, there is a problem that the time at which the p-channel MOS transistor 802 controlled by the output line 804 is turned on is delayed, the time for the through current to flow increases, and it is not uniquely determined.

From another point of view, p-channel MOS
The transistor 802 also has the function of accelerating the rise of the input waveform of the CMOS inverter 801 and reducing the delay time. Therefore, from the time when the external input line 806 is selected or the signal change of the selected external input line 806, p
The shorter the time until the channel MOS transistor 802 is turned on, the shorter the delay time and the higher the speed of the circuit.

For that purpose, a CMOS inverter 80 is used.
It is conceivable to lower the logical threshold of 1. In this case,
When the load is light, the output of the CMOS inverter 801 falls earlier, so that the on-time of the p-channel MOS transistor 802 also becomes earlier. However, when the load is heavy, the fall of the output of the CMOS inverter 801 is delayed, so that the intended high speed cannot be achieved as a result.

SUMMARY OF THE INVENTION It is an object of the present invention to realize a more reliable suppression of a through current and a faster circuit operation in a logic circuit including a CMOS logic circuit.

[0010]

In order to achieve the above object, the present invention relates to a logic circuit including a CMOS logic circuit having a first logic level and a second logic level with respect to input and output. A voltage level detecting means connected to the input line and detecting a voltage level of the input line; and a voltage level detecting means connected to the voltage level detecting means and the input line and detecting the input level according to a voltage level detection result by the voltage level detecting means. Voltage level correction means for correcting the potential of the line from an intermediate level between the first logic level and the second logic level to the second logic level is provided. Further, it is connected to the voltage level correcting means and the input line or the output line of the CMOS logic circuit, and the voltage is applied during a period when the potential of the input line changes from the second logic level to the first logic level. Voltage level correction inhibiting means for inhibiting voltage level correction by the level correcting means.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a multi-input selection circuit according to a first embodiment of the present invention, and FIG. 2 shows operation waveforms thereof.

In FIG. 1, reference numeral 101 denotes a CMOS inverter which is a kind of a CMOS logic circuit. This CMOS
The inverter 101 has first and second logic levels as input and output logic levels. Here, the L (low) level is the first logic level, and the H (high) level is the second logic level. Many external input lines 108 are connected to the input lines 104a of the CMOS inverter 101 via MOS transistors 100 as switching elements. MOS transistor 100 inserted in each external input line 108
Are turned on and off by respective control signals 107.

In order to suppress the through current of the CMOS inverter 101 and speed up the circuit operation, a voltage level detecting means 102 and a p-channel MO as a voltage level correcting means are provided.
An S transistor 103 is provided. The voltage level detecting means 102 sets the output line 105a to the H level until the potential of the input line 104a exceeds a certain voltage level, but sets the output line 105a to the L level when the potential exceeds the voltage level. A specific example of the voltage level detecting means 102 will be described later with reference to FIG. The p-channel MOS transistor 103 as a voltage level correction means
It is connected between the input line 104a of the CMOS inverter 101 and the power supply, and its gate is connected to the voltage level detecting means 102.
Output line 105a.

The circuit operation when the MOS transistor 100 of an external input line 108 is selected and turned on and the external input destination 108 is at H level will be described with reference to FIG. From this selection time t0, the CMOS inverter 1
01 starts rising from the L level, but because of the presence of the relatively large ground capacitance C and the voltage drop of the selected MOS transistor 100, the potential of the input line 104a rises slowly like the waveform 104b. Become. From time t1 when the potential of the input line 104a reaches the detection voltage level of the voltage level detection means 102, the output line 105a
Starts to fall as shown by the waveform 105b. Time point t2
As a result, the p-channel MOS transistor 103 as a voltage level correcting means is turned on, and a charging current flows to the ground capacitance C through the p-channel MOS transistor 103, and the input line 104a is pulled up to the H level side.
04a rises to the H level as early as the waveform 104b. Then, at time t3, the CMOS inverter 101
Operates, and the potential of the output line 106a falls toward the L level as shown by the waveform 106b.

By detecting the rising of the input line 104a of the CMOS inverter 101 as described above, C
At time t2, which is earlier than the start of the operation of the MOS inverter 101, the p-channel MOS transistor 103 is turned on to perform voltage level correction. Therefore, the CMOS inverter 1
01 from the selection of the external input line 108 (or the start of the rise of the signal) to the start of the fall of the output signal of the CMOS inverter 101, as compared to the conventional example in which the fall of the output signal of the CMOS inverter 101 is detected by detecting the fall of the output signal of the CMOS inverter 101. The delay time is greatly reduced. In addition, the CMOS inverter 10
Since the time when the input potential of 1 is at the intermediate level becomes short,
The time required for the through current to flow through the CMOS inverter 101 is also greatly reduced. Since the load connected to the output line 106a of the CMOS inverter 101 has no effect on the operation of the p-channel MOS transistor 103 as the voltage level correcting means, the delay time and the time during which the through current flows are uniquely determined. In addition, since the logical threshold value and the like of the CMOS inverter 101 can be determined so as to be optimized exclusively for driving the load, the speed of the CMOS inverter 101 itself can be easily increased. Thus, according to this embodiment, it is possible to realize a multi-input selection circuit that is faster than the conventional one.

FIG. 3 shows an example of the voltage level detecting means 102. The example shown here is a p-channel MOS transistor 2
This is a CMOS inverter composed of a P. 00 and an n-channel MOS transistor 201. In order to make the time point t1 in FIG. 2 earlier, it is preferable to set the logical threshold value of this CMOS inverter low.
This is possible by appropriately adjusting the size of the 0,201 channel.

Although this CMOS inverter transiently flows through current, it is known that the load is only the p-channel MOS transistor 103. Therefore, each MOS transistor 200 is controlled so that the through current is suppressed to a sufficiently small value. , 201 are easy to design.

FIG. 4 shows another example of the voltage level detecting means 102.
Shown in In the example shown here, a p-channel MOS transistor 103 is
This is a current mirror circuit including a transistor 300 and an n-channel MOS transistor 301. C
When the potential of the input line 104a of the MOS inverter 101 exceeds the threshold value of the n-channel MOS transistor 301, M
A current flows from the power supply to the ground through the OS transistors 300 and 301, and at the same time, the p-channel MOS transistor 3
A current having a value determined by 00 and the channel size ratio of the p-channel MOS transistor 103 flows from the power supply to the input line 104a through the p-channel MOS transistor 103. This current charges the ground capacitance C of the input line 104a, and raises its potential to the H level. For the MOS transistors 103 and 300, for example, the drains of both MOS transistors are made common,
The gate and source of p-channel MOS transistor 103 are arranged on one side, and the p-channel MOS transistor 103 is arranged on the other side.
A structure in which the gate and the source of the transistor 300 are provided can be employed. During the voltage level correction period of the input line 104a, it is easy to suppress the through current flowing from the power supply to the ground through the MOS transistors 300 and 301 to a minimum necessary value.

Incidentally, in the first embodiment described with reference to FIG.
It is assumed that the selected external input line changes to L level after a has risen to H level. During this transition period, until the output line 105a of the voltage level detecting means 102 is inverted to the H level, the p-channel MOS transistor 103 for voltage level correction is in the ON state, so that the potential drop of the input line 104a is prevented. That is, it acts in the direction of decreasing the circuit speed. This effect is preferably weak. However, in order to reduce this effect, in the configuration of the first embodiment, the value of the current flowing through the p-channel MOS transistor 103 at the time of rising of the input line 104a must be suppressed, and the voltage level correction effect is weakened. . Therefore, in the first embodiment, the strength of the voltage level correction at the time of rising must be limited in consideration of the adverse effect at the time of falling.

In order to eliminate such restrictions and achieve more reliable suppression of the through current and further higher speed of the circuit operation, the following second and third embodiments will be described below. While the input line 104a changes from the H level to the L level, the p-channel MOS transistor 1
03 is configured to suppress the voltage level correction operation.

FIG. 5 shows a multi-input selection circuit according to a second embodiment of the present invention, and FIG. 6 shows operation waveforms thereof. The multi-input selection circuit shown in FIG. 5 has a configuration obtained by adding a voltage level correction suppression unit 501 for suppressing the voltage level correction by the p-channel MOS transistor 103 to the multi-input selection circuit shown in FIG. In this embodiment, the voltage level correction suppressing means 501 includes a p-channel MOS transistor 505 inserted in series with the p-channel MOS transistor 103 serving as a voltage level correcting means, and a gate and a CMOS.
A delay element 504 is connected between the output line 106a of the inverter 101 and the output line 106a. This delay element 504 has a CMOS inverter output line 106a connected to its output line 509a.
And outputs a signal obtained by delaying the inverted signal of the above signal for a predetermined time. Other circuit configurations are the same as those of the multi-input selection circuit shown in FIG.

Next, when the input line 104a of the CMOS inverter 101 is at the L level, an external input line 108 of a certain H level is selected, and after the output line 106a of the CMOS inverter 101 changes to the L level, the same external input The operation when the line 108 changes to the L level or another external input line 108 at the L level is selected will be described with reference to the operation waveforms in FIG.

At time t0 when the H-level external input line 108 is selected, the potential of the input line 104a starts rising as shown by a waveform 104b, and from time t1 the potential of the output line 105a of the voltage level detecting means 102 changes to the waveform 105b. Start to fall. At this stage, since the potential of the output line 509a of the delay element 504, that is, the gate potential of the p-channel MOS transistor 505 is at the L level as shown by the waveform 509b, the p-channel MOS transistor 505 is on. Therefore, at time t2, the p-channel MOS
When the transistor 103 is turned on, the potential of the input line 104a is raised to the H level as shown by a waveform 104b.
At time t3, the CMOS inverter 101 operates, and the potential of the output line 106a starts to decrease as shown by the waveform 106b. The operation at the rising stage of the input line 104a is substantially the same as that of the multi-input selection circuit of FIG. However, at a time point t4 when a certain time has elapsed from the fall of the CMOS inverter output line 106a, the potential of the output line 509a of the delay element 504 rises as shown by a waveform 509b, so that the p-channel MOS transistor 505 is turned off (at this time). In this case, the input line 104a is at the H level), and the voltage level correction by the p-channel MOS transistor 103 is suppressed.

Thereafter, at time t5, when the selected external input line 108 changes to the L level or another external input line 108 at the L level is selected, the potential of the CMOS inverter input line 104a changes to the waveform 104b. Fall. The output line 105a of the voltage level detecting means 102 is at the L level as shown by the waveform 105b.
Since the transistor 505 is off, the p-channel M
Since the voltage level correction effect by the OS transistor 103 is suppressed, the input line 104a falls more quickly than in the case where it is not suppressed, the CMOS inverter 101 operates at time t6, and the output line 106a changes to the waveform 106b.
Stand up like. Then, at time t7, the output line 105a of the voltage level detecting means 102 rises as shown by a waveform 105b, and the p-channel MOS transistor 103 is turned off.
09 falls like a waveform 509b, the p-channel MOS transistor 505 turns on (the input line 104a is at the L level at this time), and the suppression of the voltage level correction by the p-channel MOS transistor 103 is released.

FIG. 7 shows a multi-input selection circuit according to a third embodiment of the present invention. This multi-input selection circuit has a configuration in which a voltage level correction suppression means 600 is added to the multi-input circuit shown in FIG. The voltage level correction suppressing means 600 includes a p-channel MOS transistor 601 connected in series with the p-channel MOS transistor 103 serving as a voltage level correcting means.
To the input line 104a of the CMOS inverter 101.
A signal delayed for a predetermined time without inverting the signal
02 is applied to the gate of the p-channel MOS transistor 601 through the gate. When the input line 104a rises from the L level to the H level, the gate potential of the p-channel MOS transistor 601 becomes L level and the p-channel MOS transistor 601 is turned on. However, after the input line 104a goes high, the high level is applied to the gate of the p-channel MOS transistor 601 by the delay element 602, so that the p-channel MOS transistor 601 is turned off and the voltage level correction by the p-channel MOS transistor 103 is performed. Deter. When the input line 104a falls from the H level to the L level, the p-channel MOS transistor 601 remains off until the transition period has elapsed, so that the voltage level correction by the p-channel MOS transistor 103 is suppressed. After the input line 104a goes low, the p-channel MOS transistor 601 turns on, and the voltage level correction by the p-channel MOS transistor 103 operates.

In this embodiment, since the gate of the p-channel MOS transistor 601 is controlled by a signal obtained by delaying the signal on the input line 104a, the p-channel MOS transistor 601 is turned on or off, unlike the second embodiment. This timing is uniquely determined without being affected by the blunting of the output waveform due to the load of the CMOS inverter 101.

According to the second and third embodiments, since the falling of the input line 104a is not hindered by the p-channel MOS transistor 103, the circuit operation speed at that time can be made higher than that of the circuit of FIG. The time during which a through current flows during the transition can also be reduced. On the other hand, regarding the rising of the input line 104a, without considering the falling,
Since the p-channel MOS transistor 103 can be designed to obtain a sufficient voltage level correction effect, the circuit operation at that time can be made faster than the circuit of FIG. Can also be further reduced.

Although the three embodiments have been described above, the present invention is not limited to these embodiments, but can be similarly applied to various logic circuits using CMOS logic circuits.
For example, as shown in FIG. 8, the CMOS inverter 101 of the multi-input selection circuit shown in FIG. 1 is replaced with a CMOS NAND gate 700, and a switch element 100 inserted into some (or all) external input lines 108. The present invention includes a logic circuit having a more complicated logic function, such as a configuration in which is changed to a switch element 702 controlled by two (or three or more) control signals 701. A logic circuit in which the multiple input selection circuit shown in FIG. 5 or 7 is similarly modified is also included in the present invention. Further, the voltage level detecting means, the voltage level correcting means and the voltage level correction inhibiting means are not limited to those described above.

[0030]

As is apparent from the above description, according to the present invention, in a logic circuit including a CMOS logic circuit, C
The voltage level of the input line of the MOS logic circuit is directly detected, and the potential of the input line is changed from the intermediate level when the input line of the CMOS logic circuit changes from the first logic level to the second logic level according to the detection result. By correcting to the second logic level, the through current of the CMOS logic circuit is effectively suppressed and the operation of the logic circuit is speeded up without being affected by the load connected to the output line of the CMOS logic circuit. be able to. The effect is particularly great in a logic circuit such as a multi-input selection circuit in which the ground capacitance of the input line of the CMOS logic circuit increases. Further, by suppressing the voltage level correction action during the period when the input line of the CMOS logic circuit changes from the second logic level to the first logic level, the circuit operation is further speeded up and the through current is more effectively suppressed. realizable.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the first embodiment.

FIG. 3 is a circuit diagram illustrating an example of a voltage level detecting unit.

FIG. 4 is a circuit diagram showing another example of the voltage level detecting means.

FIG. 5 is a schematic circuit diagram showing a second embodiment of the present invention.

FIG. 6 is an operation waveform diagram of the second embodiment.

FIG. 7 is a schematic circuit diagram showing a third embodiment of the present invention.

FIG. 8 is a schematic circuit diagram showing a modification of the present invention.

FIG. 9 is a schematic circuit diagram showing a conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 MOS transistor (switch element) 101 CMOS inverter 102 voltage level detecting means 103 p-channel MOS transistor (voltage level correcting means) 104 a input line of CMOS inverter 106 a output line of CMOS inverter 108 external input line 200 p-channel MOS transistor 201 n-channel MOS transistor 300 p-channel MOS transistor 301 n-channel MOS transistor 504 delay element 505 p-channel MOS transistor 600 voltage level correction suppression means 601 p-channel MOS transistor 602 delay element 700 CMOS NAND gate 702 switch element

Claims (2)

[Claims] 1. A CMOS logic circuit having a first logic level and a second logic level with respect to input and output, and voltage level detection means connected to an input line of the CMOS logic circuit and detecting a voltage level of the input line And the potential of the input line is connected to the voltage level detection means and the input line, and the potential of the input line is set to an intermediate level between the first logic level and the second logic level in accordance with a voltage level detection result by the voltage level detection means. A voltage level correcting means for correcting the level from the second logical level to the second logical level. 2. A CMOS logic circuit having a first logic level and a second logic level with respect to input and output, and voltage level detection means connected to an input line of the CMOS logic circuit and detecting a voltage level of the input line. And the potential of the input line is connected to the voltage level detection means and the input line, and the potential of the input line is set to an intermediate level between the first logic level and the second logic level in accordance with a voltage level detection result by the voltage level detection means. Voltage level correcting means for correcting the level from the second logical level to the second logical level; and a voltage level correcting means connected to the input line or the output line of the CMOS logic circuit, wherein the potential of the input line is the second logical level. A logic circuit including a CMOS logic circuit, comprising: a voltage level correction inhibiting unit that inhibits the voltage level correction by the voltage level correcting unit during a period in which the voltage level changes to the first logical level.