JPH11112347A - A / D converter, driving method of A / D converter, comparator, and driving method of comparator - Google Patents

Abstract

(57) [Abstract] [Problem] A capable of increasing digital conversion speed
To provide a / D converter. SOLUTION: Second to fourth comparator circuit sections 12b-1.
2d are three first to first circuits each having the same circuit configuration.
The third chopper type comparators 21, 22, 23 are provided. The first chopper type comparator 21 sequentially performs each operation of the sampling operation, the comparison operation, and the output operation, and repeats the operations. The second chopper type comparator 22 is configured as shown in FIG.
As shown in (1), each operation of the sampling operation, the comparison operation, and the output operation is performed in order and repeated. The third chopper type comparator 23 sequentially performs each operation of the sampling operation, the comparison operation, and the output operation, and repeats the operations. Also, first to first
The sampling operation, comparison operation, and output operation of the third chopper type comparators 21 to 23 operate so that the first to third chopper type comparators 21 to 23 do not overlap each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter,
The present invention relates to a method for driving a / D converter, a comparator, and a method for driving a comparator.

2. Description of the Related Art In recent years, digitalization of electronic devices has been progressing even in analog devices, and therefore A / D converters have been widely spread. In addition, high-speed processing is required for electronic devices, and these A
Similarly, it is desired that the / D converter operate at a higher speed. Along with this, the comparator used in the A / D converter is also required to have higher speed.

[0003]

2. Description of the Related Art A flash A / D converter has been generally known as a high-speed A / D converter. The flash A / D converter uses a chopper comparator.

FIG. 10 shows an N-bit flash type A / D converter using a chopper type comparator. The converter comprises a reference voltage generation circuit 51, (2 ^N -1) chopper type comparators 52, and an encoder 53.

[0005] The reference voltage generating circuit 51 is composed of resistance R of the 2 ^N equal resistance value at a voltage dividing circuit connected in series, dividing the reference voltage VR at the 2 ^N resistors R, correspondingly The compressed voltages are applied to the corresponding comparators 52 as comparison voltages V1 to VN-1. Each chopper comparator 52 receives the analog input voltage VAX. Each chopper type comparator 52 compares the corresponding comparison voltage V1 to VN-1 with the analog input voltage VAX, and outputs the comparison result to the encoder 53. The encoder 53 outputs an N-bit digital output signal for the analog input voltage VAX based on the comparison result of each comparator 52.

Each of the chopper type comparators 52 includes three first to third switches SW1 to SW3, a capacitor C, and a CMOS inverter IV. The first switch SW1 opens and closes based on the first control signal φ1 and supplies the analog input voltage VAX to one end of the capacitor C. The second switch SW2 opens and closes based on the second control signal φ2 and supplies the comparison voltage from the reference voltage generation circuit 51 to one end of the capacitor C. The other end of the capacitor C is connected to an encoder 53 via an inverter IV. A third switch SW3 is connected between the output terminal and the input terminal of the CMOS inverter IV. The third switch SW3 opens and closes based on the third control signal φ3.

The first to third control signals φ1 to φ3 are output at a predetermined timing from the control signal generation circuit 54 to control the switches SW1 to SW3. More specifically, the second switch SW2 is open (OFF state) by the second control signal φ2, and the first and third switches SW1 and SW3 are closed by the first and third control signals φ1 and φ3. When in the ON state, a sampling operation, that is, an analog input voltage VAX is input. At this time, the inverter IV
Is the threshold voltage VTH of the inverter IV, and the terminal voltage Vc of the capacitor C is Vc = VAX-V
TH, becomes.

Then, after the first to third switches SW1 to SW3 are turned off by the first to third control signals φ1 to φ3 to complete the sampling operation, the operation proceeds to the comparison operation.
In the comparison operation, the first and third switches SW1 and SW3 are turned off by the first and third control signals φ1 and φ3, and the second switch SW2 is turned on by the second control signal φ2. The first switch SW1 is off, the second switch
When the switch SW2 is turned on, the comparison voltage is applied to one end of the capacitor C.

At this time, when the comparison voltage is higher than the analog input voltage VAX input during the previous sampling operation, the voltage at the input terminal of the inverter IV becomes higher than the threshold voltage VTH of the inverter IV. I
V outputs an L-level output signal to the encoder 53.
Conversely, when the comparison voltage is smaller than the analog input voltage VAX input during the previous sampling operation, the inverter IV
Of the input terminal of the inverter IV is the threshold voltage V
Since the value is smaller than TH, the inverter IV outputs an H-level output signal to the encoder 53. That is, each chopper type comparator 52 sequentially executes a sampling operation and a comparison operation based on the control signals φ1 to φ3, and outputs a comparison result between the corresponding comparison voltages V1 to VN-1 and the analog input voltage VAX to the encoder 53. Output.

[0010]

The N-bit flash A / D converter using the above-mentioned chopper type comparator is excellent in increasing the speed. However, as described above, in the chopper type comparator, Since the two operations of the sampling operation and the comparison operation are performed and the comparison operation requires time, there is a limit in further increasing the speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an A / D converter and a method of driving the A / D converter, which can further increase the speed. It is in. A second object of the present invention is to provide a comparator and a method for driving the comparator, which can contribute to speeding up the A / D converter.

[0012]

According to the first aspect of the present invention, a plurality of comparison voltages having mutually different potentials are compared with each other by a comparator provided for each comparison voltage. A plurality of A / D converters for comparison are provided for each of the comparison voltages, for comparing the comparison voltage with an analog voltage.

According to a second aspect of the present invention, in the A / D converter according to the first aspect, the outputs of the plurality of comparators provided for the comparison voltage and the comparison voltages adjacent thereto are provided. A new comparator is provided for comparing the outputs of the plurality of comparators.

According to a third aspect of the present invention, there is provided the first or second aspect.
Wherein the comparator is a chopper type comparator. According to a fourth aspect of the present invention, in the A / D converter according to any one of the first to third aspects, the A / D converter is a flash type A / D converter.

[0015] The invention according to claim 5 provides the invention according to claims 1 to 3.
In the A / D converter according to any one of the above, the A / D converter is a half flash type A / D converter. According to a sixth aspect of the present invention, there is provided the driving method of the A / D converter according to the first aspect, wherein the comparator provided for each comparison voltage performs a sampling operation for inputting an analog voltage, which is performed by each comparator. In a comparison operation of inputting a comparison voltage and comparing with the analog voltage, and an output operation of outputting a comparison result by the comparison operation, at least the sampling operation and the output operation are operated at timings so as not to overlap each other.

According to a seventh aspect of the present invention, there is provided a comparator comprising a plurality of comparators which receive an analog voltage and a comparison voltage, compare the two voltages, and output the comparison result.

The invention according to claim 8 is provided with a plurality of comparators for inputting an analog voltage and a comparison voltage, comparing the two voltages and outputting the comparison result, and inputting the analog voltage to each comparator at different timings. This is a method of driving a comparator in which the output of the comparison result of each comparator is output at mutually different timings.

(Operation) According to the first aspect of the present invention, by operating each comparator at a shifted timing, analog voltages can be compared at short intervals and the comparison result can be obtained. As a result, the digital conversion speed can be increased.

According to the second aspect of the present invention, in addition to the operation of the A / D converter according to the first aspect, the outputs of the plurality of comparators provided for the comparison voltage by the new comparator and the outputs adjacent thereto are provided. The comparison of the comparison voltage with the outputs of the plurality of comparators provided means comparison between the comparison voltage and an intermediate voltage between adjacent comparison voltages and the analog input voltage. Therefore, the digital conversion speed can be increased and high-resolution digital conversion can be performed.

According to the third aspect of the present invention, the A / D converter including the chopper type comparator can perform digital conversion at a higher speed. According to the invention of claim 4, the flash A / D converter can be digitally converted at a higher speed.

According to the fifth aspect of the present invention, the half-flash A / D converter can perform digital conversion at a higher speed. According to the sixth aspect of the present invention, the sampling operation and the output operation of each comparator are operated at timing such that they do not overlap each other, so that analog voltages can be compared at short intervals and the comparison result can be obtained. As a result, the digital conversion speed can be increased.

According to the seventh aspect of the present invention, the analog voltages can be compared at short intervals by operating the comparators at different timings, and the comparison result can be obtained.

According to the eighth aspect of the present invention, the analog voltages are input to the respective comparators at different timings, and the output of the comparison result of each comparator is output at the different timings. And a comparison result can be obtained.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) An embodiment of a 3-bit flash A / D converter using a chopper type comparator embodying the present invention will be described below with reference to the drawings. FIG. 1 is an electric circuit diagram for explaining an electric configuration of a 3-bit flash A / D converter. FIG. 2 is an electric circuit diagram for explaining an electric configuration of the chopper type comparator constituting the A / D converter.

In FIG. 1, the comparison voltage generation circuit 11
A voltage dividing circuit in which a plurality of resistors R having the same resistance value are connected in series. One end of the voltage dividing circuit is connected to a DC power supply line to which a reference voltage VR is applied, and the other end is connected to ground. I have. The comparison voltage generation circuit 11 divides the reference voltage VR by eight resistors R, and applies the divided voltages to the corresponding first to seventh comparator circuit sections 12a to 12g as comparison voltages VR1 to VR7, respectively. Each of the comparator circuits 12a to 12g receives the analog input voltage VAX. The first to seventh comparator circuits 12a to 12g compare the corresponding comparison voltages VR1 to VR7 with the analog input voltage VAX and compare the comparison results with the encoder 13
Output to The encoder 13 outputs a 3-bit digital output signal S corresponding to the analog input voltage VAX based on the comparison results of the first to seventh comparator circuit sections 12a to 12g.
0, S1, and S2 are output.

First to seventh comparator circuit sections 12a-1
Since 2g is formed by the same circuit,
For convenience of description, the second to fourth comparator circuit units 12b to 12b
12d will be described, and detailed description of other comparator circuit units will be omitted. FIG. 2 shows an electric circuit of the second to fourth comparator circuit units 12b to 12d. 2nd to 4th
Each of the comparator circuit units 12b to 12d includes three first to third chopper type comparators 21, 22, and 23 having the same circuit configuration.

The first chopper type comparator 21 of each of the comparator circuit sections 12b to 12d has first to fourth switches SW1a to SW4a, each of which comprises four analog switches.
It comprises a capacitor C1 and a CMOS inverter IV1. The first switch SW1a opens and closes based on the first control signal φ1a to supply the analog input voltage VAX to one end of the capacitor C1. Second switch SW2
a opens and closes based on the second control signal φ2a and supplies the comparison voltages VR2, VR3, VR4 from the comparison voltage generation circuit 11 to one end of each capacitor C1. Capacitor C1
Is connected to the inverter IV1, and the output terminal of the inverter IV1 is connected to the encoder 13 via the fourth switch SW4a. The fourth switch SW4a opens and closes based on the fourth control signal φ4a. A third switch SW3a is connected between the output terminal and the input terminal of the CMOS inverter IV1. Third switch SW3a
Opens and closes based on the third control signal φ3a.

The second chopper type comparator 22 of each of the comparator circuit sections 12b to 12d has first to fourth switches SW1b to SW4b, each of which comprises four analog switches.
It comprises a capacitor C2 and a CMOS inverter IV2. The first switch SW1b opens and closes based on the first control signal φ1b, and supplies the analog input voltage VAX to one end of the capacitor C2. Second switch SW2
b opens and closes based on the second control signal φ2b and supplies the comparison voltages VR2, VR3, VR4 from the comparison voltage generation circuit 11 to one end of each capacitor C2. Capacitor C2
Is connected to the inverter IV2, and the output terminal of the inverter IV2 is connected to the encoder 13 via the fourth switch SW4b. The fourth switch SW4b opens and closes based on the fourth control signal φ4b. A third switch SW3b is connected between the output terminal and the input terminal of the CMOS inverter IV2. Third switch SW3b
Opens and closes based on the third control signal φ3b.

The third chopper type comparator 23 of each of the comparator circuit sections 12b to 12d has first to fourth switches SW1c to SW4c, each of which comprises four analog switches.
It comprises a capacitor C3 and a CMOS inverter IV3. The first switch SW1c opens and closes based on the first control signal φ1c to supply the analog input voltage VAX to one end of the capacitor C3. Second switch SW2
c opens and closes based on the second control signal φ2c and supplies the comparison voltages VR2, VR3, VR4 from the comparison voltage generation circuit 11 to one end of each capacitor C3. Capacitor C3
Is connected to the inverter IV3, and the output terminal of the inverter IV3 is connected to the encoder 13 via the fourth switch SW4c. The fourth switch SW4c opens and closes based on the fourth control signal φ4c. A third switch SW3c is connected between the output terminal and the input terminal of the CMOS inverter IV3. Third switch SW3c
Opens and closes based on the third control signal φ3c.

Each of the first to fourth control signals φ1a to φ4a, φ
1b to φ4b, φ1c to φ4c are control signal generation circuits 14
At a predetermined timing. First to fourth control signals φ1a to φ4a supplied to the first chopper type comparator 21 of each of the comparator circuit units 12b to 12d
Is output from the control signal generation circuit 14 at the following timing. Then, the first chopper type comparator 21
As shown in FIG. 3, each operation of a sampling operation, a comparison operation, and an output operation is sequentially performed, and the operations are repeated.

In the sampling operation, the first and third switches SW1a and SW3a are turned on, and the second and fourth switches S1a and SW3a are turned on.
W2a and SW4a are turned off. The comparison operation is the second
The switch SW2a is turned on, and the first, third, and fourth switches SW1a, SW3a, and SW4a are turned off. In the output operation, the second and fourth switches SW2a and SW4a are turned on, and the first and third switches SW1a and SW3a are turned off.

That is, during the sampling operation, the first and third control signals φ1a, φ3a are changed to the first and third switches SW1a,
The H-level signal for turning on the SW3a and the second and fourth control signals φ2a and φ4a are L-level signals for turning off the second and fourth switches SW2a and SW4a.

In the comparison operation, the second control signal φ2a is an H level signal for turning on the second switch SW2a, and the first, third and fourth control signals φ1a, φ3a, φ4a.
Are the first, third, and fourth switches SW1a, SW3a, SW
This is an L-level signal for turning 4a off.

During the output operation, the second and fourth control signals φ2
a, φ4a are the second and fourth switches SW2a, SW4a
Signal at the H level for turning ON the first and third signals
The control signals φ1a and φ4a correspond to the first and third switches SW1
a, an L level signal for turning off the SW3a.

The first to fourth signals supplied to the second chopper type comparators 22 of the respective comparator circuits 12b to 12d.
The control signals φ1b to φ4b are output from the control signal generation circuit 14 at the following timing. Then, like the first chopper type comparator 21, the second chopper type comparator 22 performs each operation of the sampling operation, the comparison operation, and the output operation in order as shown in FIG. 3, and repeats them.

That is, during the sampling operation, the first and third control signals φ1b, φ3b are changed to the first and third switches SW1b,
The H-level signal for turning on SW3b and the second and fourth control signals φ2b and φ4b are L-level signals for turning off the second and fourth switches SW2b and SW4b.

During the comparison operation, the second control signal φ2b is an H level signal for turning on the second switch SW2b, and the first, third, and fourth control signals φ1b, φ3b, φ4b.
Are the first, third, and fourth switches SW1b, SW3b, SW
4b is an L level signal for turning off 4b.

During the output operation, the second and fourth control signals φ2
b, φ4b are second and fourth switches SW2b, SW4b
Signal at the H level for turning ON the first and third signals
The control signals φ1b and φ4b correspond to the first and third switches SW1
b, an L level signal for turning off the SW3b.

The first to fourth signals supplied to the third chopper type comparator 23 of each of the comparator circuits 12b to 12d.
The control signals φ1c to φ4c are output from the control signal generation circuit 14 at the following timing. Then, the third chopper type comparator 23 performs each operation of the sampling operation, the comparison operation, and the output operation in order as shown in FIG. 3, and repeats them.

During the sampling operation, the first and third control signals φ1c and φ3c are applied to the first and third switches SW1c and SW3.
H-level signal for turning c on, second and fourth signals
The control signals φ2c and φ4c are the second and fourth switches SW2
c, an L level signal for turning off the SW4c.

At the time of the comparison operation, the second control signal φ2c is an H level signal for turning on the second switch SW2c, and the first, third and fourth control signals φ1c, φ3c, φ4c.
Are the first, third, and fourth switches SW1c, SW3c, SW
This is an L-level signal for turning off 4c.

During the output operation, the second and fourth control signals φ2
c and φ4c are second and fourth switches SW2c and SW4c.
Signal at the H level for turning ON the first and third signals
The control signals φ1c and φ4c correspond to the first and third switches SW1
c, an L level signal for turning off the SW3c.

As shown in FIG. 3, the control signal generation circuit 14 controls the sampling operation, comparison operation and output operation of the first to third chopper type comparators 21 to 23, respectively.
The first to fourth control signals φ1a to φ4 are set so that the first to third chopper type comparators 21 to 23 do not overlap each other.
a, φ1b to φ4b and φ1c to φ4c. That is, when the first chopper type comparator 21 performs the sampling operation, the second chopper type comparator 22 performs the comparison operation,
The third chopper type comparator 23 performs an output operation. When the first chopper type comparator 21 performs the comparison operation, the second chopper type comparator 22 performs the output operation,
The chopper type comparator 23 performs a sampling operation. When the first chopper type comparator 21 performs an output operation,
The second chopper type comparator 22 performs a sampling operation,
The third chopper type comparator 23 performs a comparison operation.

Next, the operation of the 3-bit flash A / D converter configured as described above will be described. Now, when the first chopper type comparator 21 starts the sampling operation, the second chopper type comparator 22 starts the comparison operation between the analog input voltage VAX input in the previous sampling operation and the comparison voltages VR1 to VR7. Further, the third chopper type comparator 23 starts an output operation of outputting the comparison result obtained in the previous comparison operation to the encoder 13. Therefore,
At this point, the first to seventh comparator circuit units 12a to 12a
A comparison result with respect to the analog input voltage VAX sampled by each of the 12g third chopper type comparators 23 in the sampling operation is output to the encoder 13 and converted into 3-bit digital signals S0 to S2.

Next, when the first chopper type comparator 21 completes the sampling operation and starts the comparison operation,
The chopper type comparator 22 starts an output operation of outputting the comparison result obtained in the previous comparison operation to the encoder 13.
Further, the third chopper type comparator 23 starts a new sampling operation. Therefore, at this time,
The comparison result with respect to the analog input voltage VAX sampled by the second chopper type comparator 22 of each of the seventh comparator circuit sections 12a to 12g in the sampling operation is output to the encoder 13, and the 3-bit digital signals S0 to S are output.
Converted to 2.

Next, when the first chopper type comparator 21 starts the output operation, the second chopper type comparator 2
2 starts a new sampling operation and the third
The chopper comparator 23 starts a comparison operation between the analog input voltage VAX input in the previous sampling operation and the comparison voltages VR1 to VR7. Accordingly, at this time, the comparison result with respect to the analog input voltage VAX sampled by the first chopper type comparator 21 of each of the first to seventh comparator circuit sections 12a to 12g in the sampling operation is output to the encoder 13, and the 3-bit digital signal is output. S0-S2
Is converted to

Thereafter, the same operation is repeated, and the A / D converter digitally converts the analog input voltage VAX at that time. Next, features of the above embodiment will be described below.

(1) In the above embodiment, the first to seventh comparator circuit sections 12a to 12g are provided with three first to third chopper type comparators 21, 22, and 23, each having the same circuit configuration. . Then, in the first to third chopper type comparators 21, 22, and 23 provided in the respective comparator circuit sections 12a to 12g, the respective operations of the sampling operation, the comparison operation, and the output operation do not overlap each other. Therefore, while one chopper-type comparator, for example, the first chopper-type comparator 21 performs the sampling operation, the comparison operation, and the output operation, sampling is first performed from the other second and third chopper-type comparators 22 and 23. The comparison result of the analog input voltage VAX is output to the encoder 13 and is converted into a digital signal, so that the analog input voltage VAX can be A / D-converted at a high speed. That is, the flash type A /
The D converter is 3 times smaller than the conventional flash A / D converter.
Digital conversion can be performed twice as fast.

(2) Each of the comparator circuits 12a to 12a
First to third chopper type comparators 2 provided in 12g
In steps 1, 22, and 23, the sampling operation, the comparison operation, and the output operation are performed so as not to overlap with each other. Therefore, the comparison operation that requires time can perform the comparison operation with a margin and has high accuracy. High comparisons can be made.

In the above embodiment, the sampling operation, the comparison operation, and the output operation do not overlap each other. However, the comparison operation may be performed so as to overlap.

In the above embodiment, three first to third chopper type comparators 21, 22, and 23 are provided in the first to seventh comparator circuit sections 12a to 12g. However, as shown in FIG. First and second chopper type comparators 2
The configuration may be implemented by using one or two or four or more components. Also in this case, at least each operation of the sampling operation and the output operation of each chopper type comparator is
As described above, it is necessary to control so as not to overlap each other.

In the above embodiment, the present invention is embodied as a 3-bit flash A / D converter, but may be applied to a 2-bit or 4-bit or more flash A / D converter. (Second Embodiment) Next, a second embodiment of the present invention will be described. This embodiment is embodied in a half flash A / D converter. The half flash A / D converter according to the present embodiment is characterized by a comparator provided in the A / D converter. Since the other parts can be easily understood from a general half-flash type A / D converter, in the present embodiment, for convenience of explanation, features having features will be described in detail, and other parts will be described. Is omitted.

FIG. 5 shows the electrical configuration of the 4-bit half flash A / D converter 30. The half flash A / D converter 30 includes three comparator circuits 31 for upper bits and three comparator circuits 32 for lower bits. The respective outputs of the three upper-bit comparator circuits 31 are output to the upper-bit encoder 33 for the upper two bits. Each output of the three lower-bit comparator circuit units 32 is output to the lower-bit encoder 34 of the lower two bits.
Upper and lower bit comparator circuit sections 31, 32
Have the same circuit configuration. FIGS. 6 and 7 show electric circuits for explaining the circuit configuration in each of the comparator circuit sections 31 and 32. FIG. The comparator circuit sections 31 and 32 are provided with two first and second chopper type comparators 35, 36, 37 and 38 having the same circuit configuration.

Each comparator circuit section 31 on the upper bit side
The first chopper type comparator 35 provided in the first to fourth switches SW1 including four analog switches
1a to SW14a, capacitor C11, and CMOS
And an inverter IV11. The first switch SW11a opens and closes to supply the analog input voltage VAX to one end of the capacitor C11. Second switch SW12
a opens and closes, a comparison voltage VRA generated by a plurality of resistors R,
VRB and VRC are supplied to one end of each capacitor C11. The other end of the capacitor C11 is connected to the inverter IV11, and the output terminal of the inverter IV11 is connected to the encoder 33 via the fourth switch SW14a. A third switch SW13a is connected between the output terminal and the input terminal of the CMOS inverter IV11.

Then, the first chopper type comparator 35
As shown in FIG. 8, each of a sampling operation, a comparison operation, an output operation, and a non-operation is sequentially performed, and the operations are repeated. In the sampling operation, the first and third switches SW11a and SW13a are turned on, and the second and fourth switches SW12a and SW14a are turned off. In the comparison operation, the second switch SW12a is turned on, and the first, third, and fourth switches SW11a, SW13a, and SW14a are turned on.
Is turned off. In the output operation, the second and fourth switches SW11a and SW14a are turned on, and the first and third switches SW11a and SW13a are turned off. In addition, when not operating, the switches SW11a to SW14a are turned off.

Each comparator circuit section 31 on the upper bit side
The second chopper type comparator 37 provided in the first to fourth switches SW1 to SW4 each including four analog switches
1b to SW14b, capacitor C12, and CMOS
And an inverter IV12. The first switch SW11b opens and closes and supplies the analog input voltage VAX to one end of the capacitor C12. Second switch SW12
b opens and closes and supplies comparison voltages VRA, VRB, VRC to one end of each capacitor C12. The other end of the capacitor C12 is connected to the inverter IV12,
The output terminal of V12 is connected to the encoder 33 via the fourth switch SW14b. CMOS inverter I
A third switch S is provided between the output terminal and the input terminal of V12.
W13b is connected.

Then, the second chopper type comparator 37
As in the first chopper type comparator 35, the switches SW11b to SW14b are controlled to open and close to perform a sampling operation, a comparison operation, an output operation, and a non-operation.

Also, the comparator circuit section 3 on the upper bit side
A sampling operation between the first chopper type comparator 35 and the second chopper type comparator 37;
Each of the switches SW11a to SW14a, SW1 is controlled so that the comparison operation, the output operation, and the non-operation do not overlap each other.
Opening and closing control of 1b-SW14b is performed. That is, as shown in FIG. 8, when the first chopper type comparator 35 performs the sampling operation, the second chopper type comparator 3
Reference numeral 7 performs a comparison operation, an output operation, and a non-operation. Further, while the first chopper type comparator 35 performs the comparison operation, the output operation and the non-operation in order, the second chopper type comparator 37 performs the sampling operation.

On the other hand, the first chopper type comparator 36 provided in each comparator circuit section 32 on the lower bit side
Are first to fourth switches SW21a to SW24a, each of which includes four analog switches, and capacitors C21 and C21.
And a MOS inverter IV21. First
The switch SW21a opens and closes to open the analog input voltage VAX.
Is supplied to one end of the capacitor C21. Second switch S
W22a opens and closes and supplies comparison voltages VRa, VRb, VRc to one end of each capacitor C21. Capacitor C2
The other end of 1 is connected to the inverter IV21, and the output terminal of the inverter IV21 is connected to the encoder 34 via the fourth switch SW24a. A third switch SW23a is connected between the output terminal and the input terminal of the CMOS inverter IV21.

Then, the first chopper type comparator 36
As shown in FIG. 8, each operation of a sampling operation, a non-operation, a comparison operation, and an output operation is sequentially performed, and the operations are repeated. In the sampling operation, the first and third switches SW21a and SW23a are turned on, and the second and fourth switches SW21a and SW23a are turned on.
The switches SW22a and SW24a are turned off. In the non-operation, the switches SW21a to SW24a are turned off. In the comparison operation, the second switch SW22a is turned on, and the first, first, third, and fourth switches SW21a, SW21
23a and SW24a are turned off. In the output operation, the second and fourth switches SW21a and SW14a are turned on, and the first and third switches SW21a and SW23a are turned off.

Each comparator circuit section 32 on the lower bit side
The second chopper type comparator 38 provided in the first to fourth switches SW2 including four analog switches
1b to SW24b, capacitor C22, and CMOS
And an inverter IV22. The first switch SW21b opens and closes and supplies the analog input voltage VAX to one end of the capacitor C22. Second switch SW22
b opens and closes and supplies comparison voltages VRa, VRb, VRc to one end of each capacitor C22. The other end of the capacitor C22 is connected to the inverter IV22, and the inverter I22
The output terminal of V22 is connected to the lower bit encoder 34 via the fourth switch SW24b. CMOS
A third switch SW23b is connected between the output terminal and the input terminal of the inverter IV22.

Then, the second chopper type comparator 38
As in the first chopper comparator 36, the switches SW21b to SW24b are controlled to open and close to perform a sampling operation, a non-operation, a comparison operation, and an output operation.

Further, the comparator circuit section 3 on the lower bit side
8, between the first chopper type comparator 36 and the second chopper type comparator 38, as shown in FIG. 8, the respective switches SW21a to SW21a.about. S
W24a and SW21b to SW24b are opened and closed.
That is, when the first chopper type comparator 36 is performing the sampling operation, the second chopper type comparator 3
8 performs non-operation, comparison operation and output operation. Further, while the first chopper type comparator 36 performs the non-operation, the comparison operation, and the output operation in order, the second chopper type comparator 38 performs the sampling operation.

Further, the switches SW11a to SW14 are connected between the first chopper type comparator 35 on the upper bit side and the first chopper type comparator 36 on the lower bit side so that the comparison operation and the output operation do not overlap each other.
a, SW21a to SW24a are opened and closed. That is, when the upper-bit first chopper comparator 35 performs the comparison operation and the output operation, the lower-bit first chopper comparator 36 performs the output operation. When the upper-bit first chopper comparator 36 is not operating, the lower-bit first chopper comparator 36 performs a comparison operation and an output operation.

Further, the switches SW11b to SW14 are connected between the second chopper type comparator 37 on the upper bit side and the second chopper type comparator 38 on the lower bit side so that the comparison operation and the output operation do not overlap each other.
b, SW21b to SW24b are opened and closed. In other words, when the upper-bit second chopper comparator 37 performs the comparison operation and the output operation, the lower-bit first chopper comparator 38 performs the output operation. When the upper-bit second chopper-type comparator 37 is not operating, the lower-bit second chopper-type comparator 38 performs a comparison operation and an output operation.

While the non-operation of the first and second chopper type comparators 35 and 37 on the upper bit side is performed between the output operation and the sample operation, the first and second chopper type comparators on the lower bit side are not performed. The non-operation of the chopper type comparators 37 and 38 is executed between the sampling operation and the output operation. This is because the comparison voltage VRa, which the half flash A / D converter supplies to the lower bit-side comparator circuit unit 32 based on the comparison result of the upper bit-side comparator circuit unit 31,
This is because VRb and VRc are determined.

Next, the operation of the 4-bit half flash A / D converter 30 configured as described above will be described. Each first chopper type comparator 3 for upper bits
5 starts the sampling operation, each of the second chopper type comparators 37 for the upper bits receives the analog input voltage VAX input in the previous sampling operation and the comparison voltages VRA and VRA.
The comparison operation with RB and VRC is started. On the other hand, each of the first chopper comparators 36 for the lower bits starts the sampling operation similarly to the first chopper comparator 35 for the upper bits. Further, each second chopper type comparator 38 for the lower bits is in a non-operation state.

When the first chopper type comparators 35 and 36 for the upper and lower bits are in the sampling operation,
The second chopper type comparator 37 for the upper bit shifts from the comparison operation / output operation to the non-operation state. Therefore, the encoder 33 for the upper bits generates digital signals S2 and S3 of the upper 2 bits.

On the other hand, the second chopper type comparator 38 for the lower bit is selected based on the determination result of the encoder 33 based on the comparison result by the comparison operation / output operation of the second chopper type comparator 37 for the upper bit. The comparison voltages VRa, VRb, and VRc are input, a comparison operation with the previously input analog voltage VAX is started, and then an output operation is performed.
Then, the encoder 34 for lower bits generates digital signals S0 and S1 of lower 2 bits.

Therefore, at this time, the analog input voltage VAX sampled by the second chopper type comparators 37 and 38 for the upper and lower bits is converted into the digital signals S0 to S0.
Converted to S3.

When each first chopper type comparator 35 for the upper bits starts the comparison operation, each second chopper type comparator 37 for the upper bits starts the sampling operation. On the other hand, each of the first chopper type comparators 36 for lower bits starts non-operation. Further, each second chopper type comparator 38 for the lower bit enters a sampling operation state.

Each of the first chopper type comparators 35 for the upper bits starts the output operation when the comparison operation is completed.
Therefore, the encoder 33 for the upper bits generates digital signals S2 and S3 of the upper 2 bits. Then, when the output operation of each first chopper type comparator 35 for the upper bits is completed, each of the first chopper type comparators 35 becomes inactive. When each of the first chopper type comparators 35 for the upper bits becomes inactive,
Each of the first chopper type comparators 36 for the lower bits is an encoder 33 based on the comparison result by the comparison operation / output operation of the first chopper type comparator 35 for the upper bits.
Of the comparison voltages VRa, VRb,
VRc is input, a comparison operation with the previously input analog voltage VAX is started, and then an output operation is performed. The lower bit encoder 34 outputs the lower two bits of the digital signal S.
0 and S1 are generated.

Therefore, at this time, the analog input voltage VAX sampled by the first chopper type comparators 35 and 36 for the upper and lower bits is converted into the digital signals S0 to S0.
Converted to S3.

Thereafter, the same operation is repeated, and the A / D converter 30 digitally converts the analog input voltage VAX at that time. Next, the features of the half flash A / D converter 30 configured as described above will be described below.

(1) In the above embodiment, the comparator circuits 31 and 32 for the upper and lower bits respectively include the two first and second chopper type comparators 35, 36, 37 and 38 having the same circuit configuration. Provided. The first chopper-type comparators 35 and 37 of the comparator circuits 31 and 32 for the upper and lower bits and the second chopper-type comparators 36 and 38 of the comparator circuit units 31 and 32 for the upper and lower bits respectively. Moved so that they do not overlap each other.

Therefore, the first chopper type comparator 3 of the comparator circuits 31 and 32 for the upper and lower bits
The second chopper type comparators 37 and 38 of the comparator circuit units 31 and 32 for the upper and lower bits perform digital conversion of the analog input voltage VAX obtained by sampling first while the respective units 5 and 36 perform each operation. A, fast
/ D conversion. That is, digital conversion can be performed at twice the speed of a conventional half-flash type A / D converter.

(2) Moreover, when the same high-speed conversion as the conventional flash A / D converter known at high speed is realized by the half flash A / D converter of the above embodiment, the chopper comparator It can be realized with a small number. By the way, in the case of 8 bits, the flash type A / D converter has 255 chopper type comparators, whereas the half flash type A / D converter of the present invention.
The converter has 60 chopper comparators.
In the case of 10 bits, the flash A / D converter has 1023 chopper comparators, whereas the half flash A / D converter of the present invention has 124 chopper comparators.

In the above embodiment, the first and second chopper type comparators 35, 36, 37 and 38 are provided in the comparator circuits 31 and 32 for the upper and lower bits. You may comprise. In the above embodiment, the 4-bit half flash A / D converter 3
Although it is embodied as 0, it may be embodied in other multi-bit half flash type A / D converters.

The embodiments of the present invention are not limited to the above embodiments, but may be implemented as follows. The comparator circuit of the above embodiment is configured by a chopper type comparator, but may be implemented instead of a differential type comparator.

The comparator circuit of the above embodiment is
It may be used alone, that is, for a comparator used only to compare the magnitude of the analog input voltage with one comparison voltage.

Although the comparator circuit of each of the above embodiments includes the fourth switch, the fourth switch may be included in the encoder, for example. The flash A / D converter shown in FIG. 4 has the comparator circuits 12a to 12 as shown in FIG.
New comparator circuit sections 40 are provided between g (in FIG. 8, between the second comparator 12b and the third comparator 12c). This new comparator circuit section 40 is provided with two first and second chopper type comparators 41 and 42 having the same circuit configuration.

The first chopper type comparator 41 is a first and second switch SW41 comprising two analog switches.
a, SW41b, two capacitors C41a, C41
b and a CMOS inverter IV41.

The first switch SW41a closes (turns on) when the first chopper comparator 21 of the second and third comparator circuit sections 12b and 12c performs a sampling operation, and connects the input terminal and the output terminal of the CMOS inverter IV41. In other cases, the input terminal and the output terminal of the inverter IV41 are cut off by being opened (turned off).

The second switch SW41b closes (turns on) when the first chopper type comparator 21 of the second and third comparator circuits 12b and 12c performs an output operation, and outputs the output (comparison result) of the CMOS inverter IV41 to the encoder. And at other times, open (off) and C
The output (comparison result) of the MOS inverter IV41 is not output to the encoder.

The input terminal of the CMOS inverter IV41 is connected to the first chopper type comparator 21 provided in the third comparator circuit section 12c via the first capacitor C41a.
Connected to the output terminal of the inverter IV1. or,
The input terminal of the CMOS inverter IV41 is connected to the inverter I of the first chopper type comparator 21 provided in the second comparator circuit section 12b via the second capacitor C41b.
It is connected to the output terminal of V1.

The second chopper type comparator 42 has a first and second switch SW42 comprising two analog switches.
a, SW42b, two capacitors C42a, C42
b and a CMOS inverter IV42.

The first switch SW42a closes (turns on) when the second chopper comparator 22 of the second and third comparator circuit sections 12b and 12c performs a sampling operation, and connects the input terminal and the output terminal of the CMOS inverter IV42. In other cases, the input terminal and the output terminal of the inverter IV42 are cut off (open).

The second switch SW42b closes (turns on) when the second chopper type comparator 22 of the second and third comparator circuits 12b and 12c performs an output operation, and outputs the output (comparison result) of the CMOS inverter IV42 to the encoder. And at other times, open (off) and C
The output (comparison result) of the MOS inverter IV42 is not output to the encoder.

The input terminal of the CMOS inverter IV42 is connected to the second chopper type comparator 22 provided in the third comparator circuit section 12c via the first capacitor C42a.
Is connected to the output terminal of the inverter IV2. or,
The input terminal of the CMOS inverter IV42 is connected to the inverter I of the second chopper type comparator 22 provided in the second comparator circuit section 12b via the second capacitor C42b.
It is connected to the output terminal of V2.

Therefore, when the first chopper type comparator 21 of the second and third comparator circuit sections 12b and 12c is performing a sampling operation, the first chopper type comparator 41 of the new comparator circuit section 40 has the first chopper type comparator.
The switch SW41a is turned on. At the time of this sampling operation, the output voltage of the inverter IV1 of the first chopper type comparator 21 of each of the second and third comparator circuit sections 12b and 12c is the same as that of the inverter IV1.
The threshold voltage VTH is 1. Therefore, the input voltage of the inverter IV41 of the first chopper type comparator 41 in the new comparator circuit section 40 is the threshold voltage VTH of the inverter IV41.

Subsequently, when the first chopper type comparator 21 of the second and third comparator circuit sections 12b and 12c performs a comparison operation, the first switch SW41a of the first chopper type comparator 41 in the new comparator circuit section 40. Is turned off.

At the time of this comparison, if there is a difference between the output voltage of the inverter IV1 of each of the first chopper type comparators 21 of the second and third comparator circuit sections 12b and 12c, the difference becomes the first and the second. Second capacitor C41
a and C41b appear in the divided voltage of the voltage dividing circuit. Note that the difference between the output voltage of the inverter IV1 of each first chopper type comparator 21 and the output voltage of the inverter IV1
41, the threshold voltage V
The center of the inverter IV41 is set so as to fall within the range of the unsaturated region (the region between the saturated region and the cutoff region) of the inverter IV41 (the second and third comparator circuit portions 12b and 12c).
In each of the first chopper type comparators 21).

Accordingly, the inverter I of the first chopper type comparator 41 in the new comparator circuit section 40
V41 operates as an inverting amplifier. As a result, the inverter IV41 inverts and amplifies the divided voltage of the voltage dividing circuit and outputs the result. The output values inverted and amplified by the inverter IV41 are compared with the comparison voltages VR2, VR3, which are compared by the second and third comparator circuits 12b, 12c, respectively.
Of the analog input voltage VAX with respect to the intermediate potential (= (VR2 + VR3) / 2).

Subsequently, when the first chopper type comparator 21 of the second and third comparator circuit sections 12b and 12c performs an output operation, the second switch SW41b of the first chopper type comparator 41 in the new comparator circuit section 40. Is turned on and output to the next encoder.

On the other hand, the second chopper-type comparator 42 in the new comparator circuit section 40 similarly outputs the comparison voltage VR2, in synchronization with each of the second chopper-type comparators 22 in the second and third comparator circuit sections 12b and 12c. V
A comparison result of the analog input voltage VAX with respect to the intermediate potential of R3 (= (VR2 + VR3) / 2) is output.

As described above in detail, the new comparator circuit section 40 compares the intermediate potential of each of the comparison voltages VR1 to VR7 with the analog input voltage VAX. Therefore, A / D conversion can be performed at high speed, and high-resolution digital conversion can be performed. In addition, since the input voltages of the CMOS inverters 41 and 42 are not near the threshold voltages of the CMOS inverters 41 and 42 in the comparison operation, a large current does not flow through the CMOS inverters 41 and 42. As a result, power consumption can be reduced.

The first chopper type comparators 41 and 42 of the new comparator circuit section 40 have the first
And second capacitors C41a, C41b, C42a, C
The same effect can be obtained by replacing the resistor 42b with a resistor.

[0098]

According to the first aspect of the invention, the digital conversion speed of the A / D converter can be increased.

According to the second and third aspects of the present invention, the digital conversion speed of the A / D converter can be increased, and high-resolution digital conversion can be performed. According to the invention of claim 4, the flash A / D converter can be digitally converted at a higher speed.

According to the fifth aspect of the invention, the half-flash type A / D converter can perform digital conversion at a higher speed. According to the invention of claim 6, the digital conversion speed of the A / D converter can be increased.

According to the seventh and eighth aspects of the present invention, the analog input voltages can be compared at short intervals, and the comparison result can be obtained.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram for explaining a flash type A / D converter.

FIG. 2 is an electric circuit diagram for explaining a circuit configuration in a comparator circuit section of the flash A / D converter.

FIG. 3 is a timing chart for explaining the operation of the flash A / D converter.

FIG. 4 is an electric circuit diagram for explaining another example of the flash A / D converter.

FIG. 5 is an electric circuit diagram for explaining a half flash type A / D converter.

FIG. 6 is an electric circuit diagram in the upper bit comparator circuit unit.

FIG. 7 is an electric circuit diagram in a lower bit comparator circuit unit;

FIG. 8 is a timing chart for explaining the operation of the half flash type A / D converter.

FIG. 9 is an electric circuit diagram for explaining another example of the flash A / D converter.

FIG. 10 is an electric circuit diagram of a conventional flash A / D converter.

[Explanation of symbols]

 12a to 12g First to seventh comparator circuit units 13, 33, 34 Encoder 14 control signal generation circuit 21 to 23 First to fourth chopper type comparator 31 Upper bit side comparator circuit unit 32 Lower bit side comparator circuit unit 33 Upper bit Side encoder 34 Lower bit side encoder 35, 36 First chopper type comparator 37, 38 Second chopper type comparator VR1 to VR7 Comparison voltage VAX Analog input voltage SW1a, SW1b, SW1c First switch SW2a, SW2b, SW2c Second switch SW3a, SW3b, SW3c Third switch SW4a, SW4b, SW4c Fourth switch C1-C3 Capacitors IV1-IV3 CMOS inverter

Claims (8)

[Claims] An A / D for comparing a plurality of comparison voltages having different potentials with each other and a comparison voltage and an analog voltage by a comparator provided for each comparison voltage.
An A / D converter, comprising: a plurality of comparators for comparing each of the comparison voltages with an analog voltage. 2. The A / D converter according to claim 1, wherein outputs of a plurality of comparators provided for a comparison voltage and outputs of a plurality of comparators provided for an adjacent comparison voltage. A / D converter provided with a new comparator for comparing. 3. The A / D converter according to claim 1, wherein said comparator is a chopper type comparator. 4. A according to claim 1, wherein
In the / D converter, the A / D converter is a flash type A
A / D converter, which is a / D converter. 5. A according to any one of claims 1 to 3, wherein
In the / D converter, the A / D converter is an A / D converter which is a half flash type A / D converter. 6. The method of driving an A / D converter according to claim 1, wherein the comparator provided for each comparison voltage performs a sampling operation for inputting an analog voltage and a comparison operation performed by each comparator. An A / D converter configured to operate at a timing such that at least a sampling operation and an output operation of a comparison operation of inputting and comparing the analog voltage and outputting a comparison result by the comparison operation do not overlap each other. Drive method. 7. A comparator comprising a plurality of comparators that receive an analog voltage and a comparison voltage, compare the two voltages, and output the comparison result. 8. A plurality of comparators for inputting an analog voltage and a comparison voltage, comparing the two voltages and outputting the comparison result, inputting the analog voltage to each comparator at different timings, and comparing each comparator. A method of driving a comparator that outputs results at different timings.