JPH11112830A - Television camera equipment - Google Patents

Abstract

(57) [Problem] To provide a circuit for automatically discriminating a plurality of video signal systems inputted from the outside. SOLUTION: A means for judging whether a synchronization signal inputted from the outside is a binary signal (NTSC synchronization signal, pseudo NTSC synchronization signal) or a ternary signal (HDTV synchronization signal, pseudo HDTV synchronization signal), and Vertical cycle frequency is 60
Hz (HDTV sync signal, pseudo NTSC sync signal) or 5
9.94 Hz (NTSC synchronizing signal, pseudo HDTV synchronizing signal) determination means, a reference clock oscillator for synchronizing with each of these synchronizing signals,
For SC sync signal, for pseudo HDTV sync signal, pseudo NTS
A function of automatically determining a reference clock oscillator for synchronizing with the synchronizing signal and an H-periodic signal generator based on the type of the synchronizing signal, and synchronizing with the synchronizing signal. It is intended to have.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television camera apparatus for automatically discriminating a high definition television (hereinafter, referred to as HDTV) signal from an NTSC signal and processing the signal.

[0002]

2. Description of the Related Art At present, a television camera of the HDTV system and NTS which is a current broadcasting system separately from the HDTV system.
At present, television cameras adopting the C system are used.
A television camera having both the DTV system and the NTSC system has been developed. However, in such a television camera supporting a plurality of systems, in order to perform synchronous coupling with an external input, an external input terminal corresponding to each system and a separate synchronization circuit are installed, or the external input terminal is One method is to manually perform switch switching in accordance with the type of input signal, and to connect to a desired synchronous circuit.

[0003]

Therefore, in the former,
It is necessary to provide an external input terminal corresponding to each system and an individual synchronous circuit, and the circuit scale required for synchronous coupling increases. In the latter case, every time the external input is switched, the switch must be manually switched, and the trouble of switching, the setting error, or the forgetting of the switching operation may occur. The present invention eliminates these drawbacks, and minimizes the number of external input terminals while supporting multiple video signal systems in synchronous coupling. The purpose is to prevent it.

[0004]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a television camera apparatus for processing signals of a plurality of television signal systems such as an HDTV system and an NTSC system. Means for separating and extracting the horizontal period synchronizing signal and the vertical period synchronizing signal from the external input signal, and extracting the extracted synchronizing signal into a binary signal (NTSC)
Sync signal, pseudo NTSC sync signal) or ternary signal (HDT
V synchronizing signal, pseudo HDTV synchronizing signal) and a vertical cycle frequency of 60 Hz (HD
TV sync signal, pseudo NTSC sync signal) or 59.94H
z (NTSC synchronizing signal, pseudo HDTV synchronizing signal), reference clock oscillating means for generating a reference clock corresponding to each of the above synchronizing signals, Means for generating a horizontal period synchronizing signal and a vertical period synchronizing signal, means for judging the binary signal or ternary signal from the outputs of the respective synchronizing signal generating units, and the frequency of the vertical period of the synchronizing signal is 60 Hz Switching means for selecting and outputting a synchronizing signal corresponding to the synchronizing signal extracted from the external input signal based on the judgment result of the means for judging whether the signal is 59.94 Hz or not, and automatically discriminating the external synchronizing signal. Things. As a result, a function of determining whether the externally input synchronization signal is a binary signal (NTSC synchronization signal, pseudo NTSC synchronization signal) or a ternary signal (HDTV synchronization signal, pseudo HDTV synchronization signal), If the frequency of the cycle is 6
A function of discriminating between 0 Hz (HDTV synchronizing signal, pseudo NTSC synchronizing signal) and 59.94 Hz (NTSC synchronizing signal, pseudo HDTV synchronizing signal) automatically discriminates a reference clock oscillator and an H cycle signal generator synchronized with the synchronizing signal. Therefore, it is possible to automatically synchronize with the synchronization signal.

[0005]

FIG. 1 shows a block diagram of an embodiment of the present invention, and the operation will be described below. As a synchronization signal input from the outside, an HDTV synchronization signal (vertical cycle:
60Hz), NTSC sync signal (vertical cycle: 59.94Hz),
There are four types of pseudo HDTV synchronization signal (vertical cycle: 59.94 Hz) and pseudo NTSC synchronization signal (vertical cycle: 60 Hz).
First, the external input signal 1 is input to a horizontal (H) cycle synchronization signal separation circuit 2, a binary / ternary signal discrimination circuit 3, and a vertical (V) cycle synchronization signal separation circuit 4. H cycle synchronization signal separation circuit 2
Then, the H-cycle synchronization signal is separated from the external input signal 1, and the V-cycle synchronization signal separation circuit 4 separates the V-cycle synchronization signal from the external input signal 1.

In the binary / ternary signal discriminating circuit 3, NTSC
Synchronous signal (or pseudo NTSC signal) is binary signal, HDT
Since the V synchronization signal (or the pseudo HDTV signal) is a ternary signal, the NTSC / HDTV signal is determined. Here, the binary / ternary signal discriminating circuit 3 in FIG. 1 outputs “L” level when the external input signal 1 is a binary signal,
H level. The H-period synchronization signal separated by the H-period synchronization signal separation circuit 2 is input to the PLL circuit 5. The output of the switching circuit 26 is also input to the PLL circuit 5. The PLL circuit The PLL circuit 5 compares the phases of the two signals, detects and outputs the phase difference, and outputs the output of the PLL circuit 5 via a LPF (low-pass filter) circuit 6 to the VCO.
9 (reference oscillation frequency: 18.5625 MHz-for HDTV),
The input terminal 2 side of the switching circuit 7 and the input terminal 1 of the switching circuit 8
Side, VCO12 (reference oscillation frequency: 14.325 MHz-
(For pseudo NTSC) 12. Where VCO
Represents a crystal oscillator.

On the other hand, the V-period synchronization signal separated by the V-period synchronization signal separation circuit 4 is input to a PLL circuit 28. The output of the switching circuit 25 is also input to the PLL circuit 28. The PLL circuit 28 compares the phases of the two signals, detects and outputs a phase difference. The output of the PLL circuit 28 is input to the input terminal 1 of the switching circuit 7, the input terminal 2 of the switching circuit 8, and the window comparator circuit 30 via the LPF circuit 29. Switching circuits 7 and 8 are binary / 3
The output of the value signal discriminating circuit 3 is used as a switching signal and the input terminal 1
Side or input terminal 2 side is selected. Here, the switching circuits 7 and 8 in FIG. 1 select the input terminal 1 side when the output of the binary / ternary signal discriminating circuit 3 is "H" level, and select the input terminal 2 side when the output is "L" level. The output of the switching circuit 7 is input to a VCO (oscillation frequency: 14.318 MHz-for NTSC) 10 to control the VCO 10. The output of the switching circuit 8 is VC
O (Oscillation frequency: 18.5439 MHz-For pseudo HDTV)
11 to control the VCO 11.

The output of the VCO 9 is supplied to an H counter circuit (HDT).
V) 13 to generate an H cycle synchronizing signal of the HDTV signal, which is input to the input terminal 1 side of the switching circuit 21.
The output of the VCO 9 is supplied to a V counter circuit (for HDTV) 1
7 to generate a V cycle synchronizing signal of the HDTV signal, which is input to the input terminal 1 side of the switching circuit 23. VCO
The output of 12 is input to an H counter circuit (for pseudo NTSC) 16, which generates an H cycle synchronization signal of the pseudo NTSC signal, and is input to the input terminal 2 side of the switching circuit 21. Also,
The output of VCO12 is a V counter circuit (for pseudo NTSC)
The switching circuit 23 generates a V cycle synchronizing signal of the pseudo NTSC signal. The switching circuits 21 and 23 select the input terminal 1 side or the input terminal 2 side using the output of the binary / ternary signal discriminating circuit 3 as a switching signal. Here, the switching circuits 21 and 23 in FIG.
If the output of the value / ternary signal discriminating circuit 3 is at "H" level, the input terminal 1 side is selected.

The output of the VCO 10 is supplied to an H counter circuit (N
The signal is input to the input terminal 2 of the switching circuit 22. The output of the VCO 10 is supplied to a V counter circuit (NTSC
, A V-cycle synchronization signal of the NTSC signal is generated, and is input to the input terminal 2 of the switching circuit 24 and the input terminal 1 of the switching circuit 25. The output of the VCO 11 is input to an H counter circuit (for pseudo HDTV) 16 and
An H-cycle synchronization signal of the TV signal is generated and input to the input terminal 1 of the switching circuit 22. The output of the VCO 11 is
A V counter circuit (for a pseudo HDTV) 19 is inputted to generate a V cycle synchronization signal of a pseudo HDTV signal, and a switching circuit 24
, And the input terminal 2 of the switching circuit 25. The switching circuits 22, 24, and 25 select the input terminal 1 or the input terminal 2 using the output of the binary / ternary signal discriminating circuit 3 as a switching signal. Here, the switching circuit 2 of FIG.
2, 24 and 25 select the input terminal 1 side when the output of the binary / ternary signal discriminating circuit 3 is "H" level, and select the input terminal 2 side when the output is "L" level.

The output of the switching circuit 25 is input to the PLL circuit 28 as a signal for phase comparison with the V-period synchronization signal separated by the V-period synchronization signal separation circuit 4.
The output of the switching circuit 21 is connected to the input terminal 1 of the switching circuit 26, and the output of the switching circuit 22 is connected to the input terminal 2 of the switching circuit 26.
Input to the side. The selection of the input terminals 1 and 2 in the switching circuit 26 is performed by the output of the window comparator 30. The output of the switching circuit 23 is connected to the input terminal 1 of the switching circuit 27, and the output of the switching circuit 24 is connected to the switching circuit 27.
Is input to the input terminal 2 side. The selection of the input terminals 1 and 2 in the switching circuit 27 is performed by the window comparator 3
This is performed by outputting 0. Here, window comparator 3
The output of 0 is "L" when the input level of the window comparator 30 is within the frequency control voltage of the VCOs 10 and 11.
If the voltage is other than the level and the cycle number control voltage, the level is "H" level.
The switching circuit 26 of FIG.
If the output of 0 is "H" level, the input terminal 1 side is selected, and if the output is "L" level, the input terminal 2 side is selected. The switching circuit 2
An output 6 is an HD (horizontal drive) pulse of the camera system, and is input as a signal for phase comparison with the H-cycle synchronization signal separated by the H-cycle synchronization signal separation circuit 2 in the PLL circuit 5. . The output of the switching circuit 27 is a VD (vertical drive) pulse of the camera system.

Next, a circuit operation when the external input signal is an HDTV signal will be described. Externally input HD
The TV signal is input to an H cycle synchronization signal separation circuit 2, a binary / ternary signal determination circuit 3, and a V cycle synchronization signal separation circuit 4. HDT separated by the H cycle synchronization signal separation circuit 2
The H-period synchronization signal for V is input to the PLL circuit 5.
At this time, the output of the switching circuit 26 is also input to the PLL circuit 5. Here, in the PLL circuit 5, the input 2
The phase difference between the two signals is detected. The output of the switching circuit 26 is
This is an HD cycle H cycle synchronization signal generated by the H counter circuit (for HDTV) 13 based on the output of the VCO (for HDTV) 9. Then, the H cycle synchronization signal becomes an HD pulse for HDTV of the camera system. Note that VC
O9 is controlled by the output of the LPF circuit 6. Also,
The output of the VCO 9 is input to a V counter circuit (for HDTV) 17 and generates a V cycle synchronization signal. This signal passes through the switching circuits 23 and 27 and becomes a VD pulse of the system. In addition, H separated by the V cycle synchronization signal separation circuit 4
The V cycle synchronization signal for DTV is input to the PLL circuit 28. The output of the switching circuit 25 is also input to the PLL circuit 28. Here, the PLL circuit 28 detects the phase difference between the two input signals. The output of the switching circuit 25 is a V counter circuit (NTS
(For C) 18 is a V-period synchronization signal. Note that V
The CO 10 is controlled by the output of the LPF circuit 29. That is, this circuit includes a VCO 10 and a V counter circuit separately from the HD and VD pulse generation circuits of the camera system.
According to (NTSC) 18, V cycle is 60Hz or 59.
This is to determine whether the frequency is 94 Hz.

Next, the circuit operation when the external input signal is an NTSC signal will be described. NT input from outside
The SC signal is input to an H-period synchronization signal separation circuit 2, a binary / ternary signal discrimination circuit 3, and a V-period synchronization signal separation circuit 4. NTS separated by H cycle synchronization signal separation circuit 2
The H-period synchronization signal for C is input to the PLL circuit 5.
At this time, the output of the switching circuit 26 is also input to the PLL circuit 5. Here, in the PLL circuit 5, the input 2
The phase difference between the two signals is detected. The output of the switching circuit 26 is
This is an NTSC H cycle synchronization signal generated by the H counter circuit (for NTSC) 14 based on the output of the VCO (for NTSC) 10. Then, this H cycle synchronization signal becomes an HD pulse for NTSC of the camera system. Note that VC
O10 is controlled by the output of the LPF circuit 6. The output of the VCO 10 is a V counter circuit (for NTSC) 1
8 to generate a V-period synchronization signal. This signal passes through the switching circuits 24 and 27 and becomes a VD pulse of the system. Further, the V-cycle synchronization signal for NTSC separated by the V-cycle synchronization signal separation circuit 4 is input to the PLL circuit 28. The output of the switching circuit 25 is also input to the PLL circuit 28. Here, in the PLL circuit 28,
A phase difference between two input signals is detected. Switching circuit 2
The output of 5 is a V counter circuit based on VCO11.
(For pseudo HDTV) 19 is a V-period synchronization signal. The VCO 11 is controlled by the output of the LPF circuit 29. That is, this circuit is the H of the camera system.
Apart from the D and VD pulse generation circuits, the V cycle is set by the VCO 11 and the V counter circuit (for pseudo HDTV) 19.
This is to determine whether the frequency is 60 Hz or 59.94 Hz.

Next, the operation when the external input signal is a pseudo HDTV signal will be described. The pseudo HDTV signal input from the outside is supplied to an H-period synchronization signal separation circuit 2, binary / 3
It is input to the value signal discriminating circuit 3 and the V-period synchronizing signal separating circuit 4. The H cycle synchronization signal for pseudo HDTV separated by the H cycle synchronization signal separation circuit 2 is input to the PLL circuit 5. At this time, the output of the switching circuit 26 is also input to the PLL circuit 5. Here, the PLL circuit 5 detects a phase difference between two input signals. Switching circuit 26
Is an H cycle synchronization signal for the pseudo HDTV generated by the H counter circuit (for the pseudo HDTV) 15 based on the output of the VCO (for the pseudo HDTV) 11. Then, the H cycle synchronization signal is the H signal for the pseudo HDTV of the camera system.
It becomes a D pulse. The VCO 11 is controlled by the output of the LPF circuit 6. The output of the VCO 11 is input to a V counter circuit (for pseudo HDTV) 19, and generates a V cycle synchronization signal. This signal is transmitted to the switching circuits 24 and 27
, And becomes the VD pulse of the system. Further, the V cycle synchronization signal for pseudo HDTV separated by the V cycle synchronization signal separation circuit 4 is input to the PLL circuit 28. Also,
The output of the switching circuit 25 is also input to the PLL circuit 28. Here, the PLL circuit 28 detects the phase difference between the two input signals. The output of the switching circuit 25 is VC
This is a V cycle synchronization signal generated by a V counter circuit (for NTSC) 18 based on O10. The VCO 10 is
It is controlled by the output of the LPF circuit 29. That is, this circuit includes a VCO 10 and a V counter circuit (for NTSC) 1 separately from the HD and VD pulse generation circuit of the camera system.
According to 8, it is determined whether the V cycle is 60 Hz or 59.94 Hz.

Next, the operation when the external input signal is a pseudo NTSC signal will be described. The pseudo NTSC signal input from the outside is divided into an H-period synchronization signal separation circuit 2, binary / 3
It is input to the value signal discriminating circuit 3 and the V-period synchronizing signal separating circuit 4. The H cycle synchronization signal for pseudo NTSC separated by the H cycle synchronization signal separation circuit 2 is input to the PLL circuit 5. At this time, the output of the switching circuit 26 is also input to the PLL circuit 5. Here, the PLL circuit 5 detects a phase difference between two input signals. Switching circuit 26
Is an H cycle synchronization signal for the pseudo NTSC generated by the H counter circuit (for the pseudo NTSC) 16 based on the output of the VCO (for the pseudo NTSC) 12. Then, the H cycle synchronization signal is used as the H signal for the pseudo NTSC of the camera system.
It becomes a D pulse. The VCO 12 is controlled by the output of the LPF circuit 6. The VCO 12 output is input to a V counter circuit (for pseudo NTSC) 20,
Generate a V cycle synchronization signal for SC. This signal passes through the switching circuits 23 and 27 and becomes a VD pulse for pseudo NTSC of the system. Also, the V-period synchronization signal separation circuit 4
The V cycle synchronization signal for pseudo NTSC separated by
Input to the circuit 28. The output of the switching circuit 25 is also input to the PLL circuit 28. Here, the PLL circuit 28 detects the phase difference between the two input signals. The output of the switching circuit 25 is V
This is a V cycle synchronization signal generated in the counter circuit (for pseudo HDTV) 19. The VCO 11 is controlled by the output of the LPF circuit 29. In other words, this circuit is different from the HD / VD pulse generation circuit of the camera system in that the VCO
11. V counter circuit (for pseudo HDTV) 19
It is to determine whether the V cycle is 60 Hz or 59.94 Hz. That is, whether the signal is an HDTV signal or an NTSC signal is determined by the binary / ternary signal determination circuit 3, and whether the signal is an HDTV signal or a pseudo HDTV signal is determined.
Alternatively, whether the signal is an NTSC signal or a pseudo NTSC signal is determined by the window comparator 30.
It is possible to automatically determine the above four signals input from the outside.

[0015]

As described above, according to the present invention, an externally input synchronization signal is a binary signal (NTSC synchronization signal,
A pseudo NTSC synchronization signal) or a ternary signal (HDTV
And a function for determining whether the signal is a synchronization signal for synchronization or a pseudo HDTV synchronization signal) and the frequency of the vertical cycle of the synchronization signal is 60 Hz.
(HDTV synchronization signal, pseudo NTSC synchronization signal) or 59.94 Hz (NTSC synchronization signal, pseudo HDT synchronization signal).
The reference clock oscillator and the H-period signal generator for synchronizing with these external synchronizing signals can be automatically discriminated and selected by the function of judging whether or not the external synchronizing signal is used. It is possible to manufacture a television camera device having the above configuration.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.

[Explanation of symbols]

1: external input signal, 2: H cycle synchronization signal separation circuit, 3:
Binary / ternary signal discrimination circuit, 4: V-period synchronization signal separation circuit, 5, 28: PLL circuit, 6, 29: LPF circuit,
7, 8, 21 to 27: switching circuit, 9: VCO (HDTV
10: VCO (for NTSC), 11: VCO (for pseudo HDTV), 12: VCO (for pseudo NTSC), 13:
H counter circuit (for HDTV), 14: H counter circuit
(For NTSC), 15: H counter circuit (pseudo HDTV)
16) H counter circuit (for pseudo NTSC), 17:
V counter circuit (for HDTV), 18: V counter circuit
(For NTSC), 19: V counter circuit (pseudo HDTV)
20) V counter circuit (for pseudo NTSC), 30:
Window comparator circuit.

Claims (1)

[Claims] 1. A television camera device for processing signals of a plurality of television signal systems such as a high-definition television (hereinafter, referred to as HDTV) system and an NTSC system. Means for separating and extracting the period synchronization signal and the vertical period synchronization signal, and that the extracted synchronization signal is a binary signal (NTSC synchronization signal, pseudo NTSC synchronization signal) or ternary signal (HDTV synchronization signal, pseudo HDTV synchronization signal) Means for determining whether the frequency of the vertical cycle of the synchronization signal is 60 Hz (HDTV synchronization signal, pseudo NTSC synchronization signal) or 59.94 Hz (NTSC synchronization signal, pseudo HDTV synchronization signal). A reference clock oscillating means for generating a reference clock corresponding to each synchronization signal; Means for generating a horizontal period synchronizing signal and a vertical period synchronizing signal, means for judging the binary signal or ternary signal from the output of the respective synchronizing signal generating means, and the frequency of the vertical period of the synchronizing signal is 60H
switching means for selecting and outputting a synchronization signal corresponding to the synchronization signal extracted from the external input signal based on the determination result of the means for determining whether the signal is z or 59.94 Hz, and automatically determining the external synchronization signal. A television camera device.