JPH11119746A - Drive circuit, display device and electronic equipment - Google Patents

Abstract

(57) Abstract: In a liquid crystal display driving circuit, various clock signals (dot clock DC, clock signal C) are used.
LX1 to CLX4) are automatically adjusted. SOLUTION: A dummy circuit 27 is formed on the same IC chip as a data drive circuit (not shown) of a liquid crystal display, and simulates a circuit per one stage of the data drive circuit. The counter 26 receives the clock signal OS
The delay time (time during which the signal passes through the dummy circuit 27) is measured by counting the CI, and the measurement result is stored in the register 25 for each frame period. The counter 22 counts the clock signal OSCI using the value stored in the register 25 as an initial value, and the decoder 23 decodes this to generate various clock signals. When the delay time of the data side driving circuit and the dummy circuit 27 changes due to a temperature change or the like, the value is reflected on the initial value of the counter 22, and the generation timing of various clock signals is adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit suitable for a liquid crystal display, a display device controlled by the driving circuit, and an electronic apparatus.

[0002]

2. Description of the Related Art The general structure of a conventional liquid crystal display device will be described with reference to FIG. The liquid crystal display device is a liquid crystal panel used as a light valve of an electronic device, for example, a liquid crystal projector, and includes a liquid crystal panel block 10, a timing circuit block 20, and a data processing block 30. The blocks 20 and 30 are formed on the same IC chip.

The timing circuit block 20 outputs a timing signal (to be described in detail later) used in each section. In the data processing block 30, reference numeral 32 denotes a phase expansion circuit which, when one system of image signal Data is input, expands it into N-phase (N = 6 in the illustrated example) image data Data1 to 6. Output. The image signal Da
The reason why ta is expanded to the N phase is that the time for applying the image data signal to the source electrode of each TFT 114 via the sample and hold switches 106a to 106f described later is extended, so that the sample and hold time and the charging time of the liquid crystal cell 116 are increased. This is to ensure.

Reference numeral 34 denotes an amplifying / inverting circuit for inverting image data Data1 to Data6 which need to be inverted, and then appropriately inverting the inverted image data Data1 to Data6.
6 is amplified and output. Note that the inversion cycle is determined by one horizontal scanning period or dot clock depending on whether the method of applying the data signal to the entire panel is polarity inversion in scanning line units, polarity inversion in data signal lines, or polarity inversion in pixel units. Set to the cycle.

In the liquid crystal panel block 10, FIG.
Scanning signal lines 1 arranged in parallel along the row direction of
, 10a, b, c,..., And a plurality of data signal lines 112a, b,
The pixel portion 100 having c,... is formed.

In the figure, a scanning signal line 110 and a data signal line 1
Pixels are formed in a matrix at the intersections of 12a, b, c,.... Each pixel has a scanning signal line 11
, A gate electrode is connected to the data signal lines 112a, b, c,..., And a pixel electrode (not shown) connected to the drain electrode of the TFT 114 ) And a storage capacitor (not shown) connected to the pixel electrode. And a pixel electrode,
A liquid crystal cell 116 is constituted by the corresponding common electrode and the liquid crystal layer sandwiched between both electrodes.

The liquid crystal panel has a glass substrate (element substrate) on which the above-described data signal lines, scanning signal lines, TFTs, pixel electrodes, and storage capacitors are formed, and a glass substrate (a counter substrate) on which a common electrode is formed. ) Are opposed to each other with a gap, and the liquid crystal is sandwiched between the gaps and sealed.

Are sample-and-hold switches formed of TFTs formed on the element substrate, and are provided corresponding to the respective data signal lines 112. When a predetermined hold signal is supplied, the sample-and-hold switches 106a, b, c,. The voltage levels of the image data Data1 to 6 at that time are output to the corresponding data signal lines 112.

Reference numeral 104 denotes a sample hold switch 106
a, b, c,... are data-side drive circuits for driving and controlling the image data Data1 to
6, each sample and hold switch 106a,
The hold signal is supplied to b, c,... (the details will be described later). 103 denotes a data line driving circuit. Reference numeral 105 denotes a scanning-side driving circuit, and each of the scanning signal lines 110a, 110b,
Scan signals are sequentially supplied to c,.

Here, the TFT 114 whose gate electrode is connected to the scanning signal line 110a, b, c,... To which the scanning signal is supplied is turned on. When the image data is supplied to the data signal lines 112a, b, c,..., The TFs whose source electrodes are connected to the data signal lines
The storage capacitor is charged via T114. That is, the liquid crystal cell 11 corresponding to the intersection of the vertical scanning by the scanning side driving circuit 105 and the horizontal scanning by the data side driving circuit 104
6 will be charged. Reference numeral 170 denotes a precharge circuit, and each of the data signal lines 112a, b, c,...
Immediately before image data is supplied to each data signal line, that is, before the selection of the previous scanning line is completed and a new scanning line is selected and the data signal is supplied to the pixel. A precharge voltage is applied through TFTs 170a, b, c,....

The precharge circuit 170 is formed on an element substrate, receives a precharge timing signal PR supplied from the timing circuit block 20, and
70a, b, c,..., Each data signal line 112a,
A precharge voltage VP supplied from outside the panel is applied to b, c,... The example of the precharge circuit shown in FIG. 4 is a case where the panel is driven by the polarity inversion of the scanning line unit, and the voltage VP is set to a voltage having the same polarity as the polarity of the data signal immediately applied to the data signal line. The polarity is inverted for each scanning line.

Next, details of the data side driving circuit 104 will be described with reference to FIG. In the figure, 120, 130, 14
Reference numerals 0 and 150 are shift registers to which a common input signal DX shown in FIG. 6 is supplied. Here, as shown in FIG. 6, the input signal DX is a signal that goes to the “H” level over “8” cycles of the dot clock DC. Each of the clock signals CLX1 to CLX4 has a cycle of “8” times the dot clock DC, and each of the clock signals CLX2 to CLX4 has a cycle of “1” of the dot clock DC and “2” with respect to the clock signal CLX1. "And" 3 "periods.

Returning to FIG. 5, in the shift register 120, a clocked inverter 121a is supplied with an input signal DX and a clock signal CLX1 to its signal input terminal and control input terminal, respectively. Therefore, the output signal of the clocked inverter 121a is at the "L" level for a half cycle in which both the input signal DX and the clock signal CLX1 are at the "H" level, and is high for the half cycle in which the clock signal CLX1 is at the "L" level. It becomes an impedance state.

Next, an inverter 121b inverts an output signal of the clocked inverter 121a. Therefore, during a half cycle in which both the input signal DX and the clock signal CLX1 are at the “H” level, the output signal of the inverter 121b is at the “H” level. Next, a clocked inverter 121c is supplied with an output signal of the inverter 121b at its signal input terminal and a clock signal -CLX1 (an inverted signal of CLX1) at its control input terminal.

Therefore, during a half cycle in which both the clock signal CLX1 and the input signal DX are at the “H” level, the output of the clocked inverter 121c is in a high impedance state. Here, when the clock signal CLX1 becomes “L” level, the output signal of the inverter 121b at that time is inverted by the clocked inverter 121c,
An “L” level output signal is supplied to inverter 121b. As a result, even in a half cycle in which clock signal CLX1 is at the “L” level, a signal at the “H” level is output from inverter 121b.

Next, the clock signal CLX1 becomes "H" again.
When the level becomes the level, the input signal DX becomes 'L' level, so that the output signal of the clocked inverter 121a becomes 'H' level and the output signal of the inverter 121b becomes 'L' level. Therefore, the output signal of the inverter 121b (indicated by SR1-OUT1 in FIG. 6) becomes equal to the input signal DX.

A clocked inverter 122a has a signal input terminal and a control input terminal connected to a signal SR.
1-OUT1 and a clock signal -CLX1 are supplied. Accordingly, in a half cycle in which signal SR1-OUT1 is at the “H” level and clock signal CLX1 is at the “L” level, the output signal of clocked inverter 122a is at the “H” level, and the other period is high impedance. become. In other words, the clocked inverter 12
From 2a, a signal obtained by delaying the output signal of clocked inverter 121a by a half cycle is output.

Next, 122b is an inverter, 122c is a clocked inverter, and 123a is a clocked inverter, which are connected similarly to the inverter 121b and the clocked inverter 121c, respectively. However, the clocked inverter 121c and the clocked inverter 1
The clock signal CLX1 that is not inverted is supplied to 23a. As a result, the output signal of inverter 122b (represented by SR1-OUT2 in FIG. 6) is a signal delayed from signal SR1-OUT1 by a half cycle of clock signal CLX1.

As described above, the clocked inverter 121
a, inverter 121b and clocked inverter 1
Reference numeral 21c forms the first stage of the shift register 120, and the clocked inverters 122a, 122b and 122c form the second stage. Then, a signal obtained by sequentially delaying the input signal DX by a half cycle of the clock signal CLX1 is output from each stage of the shift register 120.

The shift registers 130, 140, 1
Reference numeral 50 is configured in the same manner as the shift register 120, and is driven by clock signals CLX2 to CLX4 whose phases are advanced by "1" period, "2" period and "3" period of the dot clock DC with respect to the clock signal CLX1, respectively. . As a result, the shift registers 130, 140, 150
Output signal of each stage of the shift register 120 is "1" period of the dot clock DC,
The phase is advanced by "2" periods and "3" periods. Therefore, the remarkable output signals of these shift registers become equal to the signals obtained by delaying the input signal DX by one period of the dot clock DC as shown by the signals SR1-OUT1 to SR3-OUT2 in FIG.

Next, 160a, b, c,...
The circuit performs a NAND operation on an output signal of each stage of each shift register and an output signal (for example, the signal SR1-OUT1 and the signal SR1-OUT2) delayed by "4" cycles of the dot clock DC. 162a, b, c,...
Is an inverter, and NAND circuits 160a, b, c,
.. Are inverted and the signals SL1-Data1, S
L2-Data2, SL3-Data3,... Are output.

As a result, as shown in FIG.
-Data1, SL2-Data2, SL3-Data
.. Represent the output signals SR1-OUT1, SR2-O
, UT1, SR3-OUT1,..., And the output signal delayed by “4” cycles with respect to each other, and has a pulse width of “4” cycle width of the dot clock DC. Are sequentially delayed by "1" period. These signals are used as hold signals as sample hold switches 106a, 106b, 106c,.
, The image data Data1 to 6 are held by the sample and hold switches 106a, b, c,....

Next, the configuration of the timing circuit block 20 will be described with reference to FIG. In the figure, reference numeral 21 denotes an oscillation circuit, which outputs a clock signal OSCI having a frequency several times that of the dot clock DC. 22 is a counter,
The reset is performed in synchronization with the rise of the horizontal synchronization signal HSYNC. After the reset, the number of pulses of the clock signal OSCI is counted. An initial value input terminal INI for inputting an initial value of the count value at the time of reset is input to the counter 22.
T is provided. Reference numeral 24 denotes a rotary encoder which is operated by a manufacturer or a user to set the initial value. A decoder 23 decodes the output value of the counter 22 and outputs various timing signals in addition to the dot clock DC, the input signal DX and the clock signals CLX1 to CLX4.

[0024]

By the way, in the circuit shown in FIG. 5, although the image signal Data is expanded to the "6" phase, the sample hold switch 106a,
The sample hold time in b, c,... is only “4” times the dot clock DC, and the switching element 106 cannot perform sufficient sampling of the data signal, and is supplied to the pixel with an insufficient voltage. Therefore, a sufficient contrast ratio cannot be obtained. This means that it is easy to simply extend the sample hold time (for example, for each of the NAND circuits 160a, b, c,..., The output signal with the shift register and the "3" cycle or "3" period of the dot clock DC). If an output signal delayed by 2 cycles is supplied, the sample hold time becomes "5" times or "6" times the dot clock DC.) With this configuration, the frequency of timing adjustment becomes high. is there.

The reason will be described below. In FIG. 6, signals SL1-Data1, SL2-Data2,
The rising or falling timing of SL3-Data3,... Matches the rising or falling timing of clock signals CLX1 to CLX4. However, these timings do not match because each gate circuit has a delay time.

For example, if the circuit shown in FIG. 5 is constituted by a TFT (thin film transistor), the signal SL1-Data
The delay time of 1, SL2-Data2, SL3-Data3,... Is about “50 to 200” nsec. The delay time varies depending on the environment in the semiconductor manufacturing process, and varies greatly with temperature and aging. Therefore, if the sample hold time is extended to "5" times or "6" times the dot clock DC, the signal SL1
-Data1, SL2-Data2, SL3-Data
Due to the timing error of 3,..., Unintended image data may be held.

For example, in the configuration as shown in FIG. 4, the image data to be held by the sample and hold switch 106a is stored in the sample and hold switch 1a.
It is conceivable that it is held by 06 g. When such a problem occurs, a ghost occurs in the image displayed on the liquid crystal panel block 10. Therefore, in order to avoid such a situation, the manufacturer and the user need to adjust the timing of the data-side drive circuit 104 as necessary. That is, it is necessary to operate the rotary encoder 24 while looking at the screen to find an optimum point, which is complicated.

As described above, in the conventional liquid crystal display drive circuit, the frequency of the timing adjustment increases when trying to secure a long sample hold time, and the sample hold time must be shortened when trying to reduce the frequency of adjustment. , The contrast ratio decreases, and the image quality deteriorates.

The present invention has been made in view of the above circumstances, and has as its object to provide a driving circuit, a display device, and an electronic device which can simplify the adjustment work while having high image quality.

[0030]

According to a first aspect of the present invention, a plurality of data signal lines to which data signals are supplied and a scanning signal line intersecting the data signal lines are provided. A pixel is provided in a matrix corresponding to the intersection of the data signal line and the scanning signal line, and a data signal of the corresponding data signal line is supplied when a predetermined scanning signal is supplied to the corresponding scanning signal line And a data line driving circuit for supplying the data signal to the data signal line in synchronization with a predetermined clock signal, and at least a part of the data line driving circuit. A dummy circuit that simulates a circuit; and a timing adjustment circuit that measures a delay time of the dummy circuit and adjusts a timing of the clock signal based on the measured delay time. And wherein the Rukoto.

Further, in the configuration according to the second aspect,
2. The driving circuit according to claim 1, wherein the data line driving circuit and the dummy circuit are formed on the same substrate.

Further, in the configuration according to the third aspect,
3. The driving circuit according to claim 2, wherein the data line driving circuit includes a shift register that sequentially transmits an input signal, and a switching element that is controlled based on a timing of an output signal of each stage of the shift register. The dummy circuit includes a circuit for at least one stage of the shift register and a switching element controlled based on the timing of the output signal.

Further, in the configuration according to the fourth aspect, a plurality of data signal lines to which a data signal is supplied, a scanning signal line intersecting the data signal line, the data signal line and the scanning signal line , Which are provided in a matrix corresponding to the intersection of the pixels, and which are provided with a pixel to which a data signal of a corresponding data signal line is supplied when a predetermined scanning signal is supplied to the corresponding scanning signal line. A circuit,
A data line driving circuit that supplies the data signal to a corresponding data signal line in synchronization with a predetermined clock signal; a delay time measuring circuit that measures a delay time of the data line driving circuit; And a timing adjustment circuit for adjusting the timing of the clock signal.

Further, in the configuration according to claim 5,
5. The drive circuit according to claim 4, further comprising a precharge circuit for applying a precharge voltage to said data signal line, wherein said data line drive circuit sequentially shifts an input signal, and each of said shift register A switching element controlled by the timing of the output signal of the stage, wherein the delay time measuring circuit applies an input signal to the shift register, and then applies the input signal to the input terminal of the switching element to the data line. The time until the precharge voltage appears is measured as the delay time.

Further, in the configuration according to claim 6,
6. The driving circuit according to claim 5, wherein the data line driving circuit and the precharge circuit are formed on the same substrate.

According to a seventh aspect of the present invention, there is provided a driving circuit according to any one of the first to sixth aspects.

[0037] According to an eighth aspect of the present invention, there is provided a display device according to the seventh aspect.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION

1. First Embodiment Next, a liquid crystal panel according to a first embodiment of the present invention will be described. The overall configuration of the first embodiment is similar to that of FIG. The configuration of the data-side drive circuit 104 is the same as that shown in FIG. 5, but in order to obtain a high contrast ratio, the sample and hold time in the sample and hold switches 106a, b, c,. "6"
(For example, the signal SL1-- in FIG. 6).
Instead of Data1, signal SR1-OUT1 and signal SR
3-A product obtained by ANDing with OUT1 is used).

As the timing circuit block 20, the one shown in FIG. 1 is used instead of the one shown in FIG.
In the figure, parts corresponding to the respective parts in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

In the figure, reference numeral 26 denotes a counter, the S of which is
When the signal at the TART input terminal rises to the “H” level, the counting of the clock signal OSCI starts, and when the signal at the STOP input terminal rises to the “H” level, the counting ends. Reference numeral 25 denotes storage means such as a register, which latches the count result of the counter 26 in synchronization with the vertical synchronization signal VSYNC.

Reference numeral 27 denotes a dummy formed on the element substrate of the liquid crystal panel block 10 in the same process as each element of the data line driving circuit 103, and for simulating the data line driving circuit 103 and detecting a delay time of the circuit there. And the data side drive circuit 104 and the sample hold switch 10
6a, b, c,... Are configured in the same manner as the configuration per "1" stage. That is, the dummy circuit 27 includes a clocked inverter 271 corresponding to the clocked inverter 121a and the like, an inverter 272 corresponding to the inverter 121b and the like, and a NAN corresponding to the NAND circuit 160a and the like.
It comprises a D circuit 273, an inverter 274 corresponding to the inverter 162a, and a sample hold switch 275 corresponding to the sample hold switch 106a and the like.

A power supply voltage VDD is applied to the input terminal of the sample hold switch 275, and the output terminal is connected to the STOP input terminal of the counter 26. The input signal DX is supplied to the START input terminal of the counter 26 and the input terminal of the clocked inverter 271. Elements such as TFTs constituting the dummy circuit 27 have the same size (TFT) as the corresponding circuit elements of the data line driving circuit 103.
Have the same channel length and channel width)
It is configured so that That is, it is desirable that both have the same process and the same configuration and have substantially the same characteristics.

The dummy circuit 27 is provided on an element substrate near the data line driving circuit 103 in order to obtain a delay time equivalent to that of the data line driving circuit 103 regardless of variations in element characteristics on the substrate. Good.

Next, the operation of this embodiment will be described.

First, when the horizontal synchronizing signal HSYNC rises, the counter 22 is reset, and the initial value of the count value is set based on the contents of the register 25. Thereafter, each time the clock signal OSCI rises, the count result is supplied to the decoder 23 while being incremented. In the decoder 23, the dot clock DC, the input signal DX, and the clock signal CL shown in FIG.
X1 to CLX4 are generated and are supplied to the data side driving circuit 104. As a result, the sample hold switch 106a is driven.

The image signal Data is supplied to the phase expansion circuit 32.
Are developed into image data Data 1 to 6 of the “6” phase, and supplied to the input terminals of the sample-and-hold switches 106 a, 106 b, 106 c,.
As a result, the image data Data1 to 6 are latched by the sample and hold switches 106a, b, c,..., And an image is displayed on the pixel unit 100.

On the other hand, when input signal DX rises to 'H' level, counter 26 starts counting clock signal OSCI. This input signal DX is supplied to a clocked inverter 271, an inverter 272, and a NAND circuit 27.
3, and is delayed while being inverted “4” times via the inverter 274 and supplied to the control input terminal of the sample and hold switch 275. Then, after the operation time of the sample hold switch 275 elapses, the power supply voltage VDD
Is applied to the STOP input terminal of the counter 26, and the counting operation in the counter 26 ends. here,
FIGS. 10B to 10D show the relationship between the input signal DX, the output signal of the dummy circuit 27, and the count value of the counter 26.

The above operation is repeated for each horizontal scanning cycle. When the horizontal scanning for "1" field (or one frame) is completed and the vertical synchronization signal VSYNC is supplied to the register 25, the counting result of the counter 26 (that is, the last horizontal scanning in the previous field (frame)) is performed. The count result during the period is latched in the register 25. As a result, the horizontal synchronizing signal HSYN
When C is supplied to the counter 22, the count result is preset as an initial value of the count in the counter 22.

Since the dummy circuit 27 is formed by the same process on the same substrate as the data side drive circuit 104, each stage of the data side drive circuit 104 and the sample and hold switches 106a, b, c,. They have almost the same delay time. The count result in the counter 26 indicates this delay time, and the initial value in the counter 22 is preset based on the count result. Therefore, the dot clock DC, the input signal DX, and the clock signal CLX1 output from the decoder 23 are output.
Timing signals such as .about.CLX4 are output at a timing earlier by a time corresponding to the count result.

In other words, assuming that the initial value of the counter 22 is "0", the waveform of the signal DX is shown in FIG.
If it is as shown in FIG. 2F, the waveform of the signal DX when the initial value of the counter 22 is set according to the count result of the counter 26 is as shown in FIG.

As a result, the delay time in the data side driving circuit 104 and the sample and hold switches 106a, b, c,... Is compensated. First of all, image data Dat
Since a1 to a6 are transmitted at the dot clock frequency synchronized with the clock signal OSCI, the delay time is
Although the sampling timing of the image data Data 1 to 6 has been shifted, this is compensated for.
The timing of the sample hold in the sample hold switches 106a, b, c,...
It almost exactly coincides with the transmission timings of ta1 to ta6. Also, even if the delay time of the data side drive circuit 104 or the sample and hold switches 106a, b, c,... Changes due to a temperature change or the like, the delay time of the dummy circuit 27 on the same substrate should also change. Is immediately reflected in the count result of the counter 26.

It should be noted that the count result of the counter 26 is not used for each horizontal synchronization signal HSYNC, but for the vertical synchronization signal VSYNC.
The reason that the count is reflected on the counter 22 every time is that when the delay time of the dummy circuit 27 is near the threshold value at which the count value changes, the count result varies every horizontal scan, so the DX timing is changed every horizontal scan. This is because a change in scanning timing may cause flicker on the screen.

The oscillation circuit 21 is configured as a phase-locked loop (PLL), and outputs a horizontal synchronizing signal HSY.
NC and the vertical synchronizing signal VSYNC are also clock signals OSCI.
Is preferably counted and formed.

In FIG. 1, the dummy circuit 27 for one stage of the data line drive circuit 103 is provided to measure the delay time for one stage. However, the present invention is not limited to this, and the present invention is not limited to this. The delay can be measured. For example, when measuring the delay of two stages of the shift register, the delay time up to the sample and hold switch 106e is measured. In this case, the clocked inverter 121
a, inverter 121b, clocked inverter 122
a, which simulates these in correspondence with the inverter 122b 4
The inverter of the stage is provided by replacing the inverter 271 of FIG.

In this case, it is preferable that the dummy clocked inverter be configured as a clocked inverter to which the clock CLX1 is input, similarly to the data side drive circuit. Further, since the calculation result of the counter 26 measures the delay caused by the output of the second stage of the shift register that inputs the clock CLX1, the calculation result obtained by subtracting the half cycle of the clock CLX1 is set to one half. 22 will be preset.

2. Second Embodiment Next, an example in which the liquid crystal panel of the first embodiment is applied to a liquid crystal projector will be described with reference to FIG.

In the figure, reference numeral 1100 denotes a liquid crystal projector, in which a lamp unit 1102 for a white light source is provided. The projection light emitted from the lamp unit 1102 is supplied to the plurality of mirrors 11 in the light guide 1104.
, And three dichroic mirrors 1108, the three primary colors of RGB are separated, and three liquid crystal panels 1110 associated with the respective primary colors
R, 1110G and 1110B are illuminated, and each liquid crystal panel modulates the incident color light as a light valve according to an image signal.

The structures of the liquid crystal panels 1110R, 1110G and 1110B are as described in the first embodiment. The timing circuit block 20 described in the first embodiment includes three liquid crystal panels 1110R, 1110G,
It is preferable that the delay time from the dummy circuit 27 of one of the three liquid crystal panels is provided in common with the 1110B.
This is because the three liquid crystal panels are manufactured in the same process, and the shift in the delay time due to manufacturing variations is small, so that the timing circuit block 20 can be used in common.

However, if the three liquid crystal panels are used in different environments (different ambient temperatures) and the characteristics of the liquid crystal panels are different from each other, a timing circuit block 27 may be provided for each of the liquid crystal panels to separately adjust the timing. .
Now, the light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions.
In the dichroic prism 1112, red (R) and blue (B) light are bent by “90 °”, and green (G) light goes straight. Therefore, the images of the respective colors are combined, and a color image is projected on a screen or the like via the projection lens 1114.

3. Third Embodiment Next, an example in which the liquid crystal panel of the first embodiment is applied to a personal computer will be described with reference to FIG.

In the figure, personal computer 120
0 is a main body 1204 having a keyboard 1202;
And a liquid crystal display 1206. The liquid crystal display 1206 is configured by adding a color filter and a backlight to the liquid crystal panel of the first embodiment.

4. Modifications The present invention is not limited to the embodiments described above,
For example, various modifications are possible as follows.

4.1. In each of the above embodiments, the count result of the counter 26 is latched in the register 25 in synchronization with the vertical synchronization signal VSYNC, but various latch timings other than the vertical synchronization signal VSYNC may be employed. For example, latching may be performed at 10-second intervals and 1-minute intervals.

4.2. In the above embodiments, the data side drive circuit 104 and the sample hold switch 1
The dummy circuit 27 was used to determine the delay times of 06a, b, c,.... However, for example, the data side driving circuit 104 and the sample hold switch 10
6a, b, c,... Themselves may be measured, and the contents of the register 25 may be set based on the result.

FIG. 8 shows a modification of this embodiment. FIG.
In, the potential of the first-stage data line 112a is extracted and input to the count stop STOP of the counter 26 in the middle. Input signal DX generated during vertical blanking
Are transmitted by the clock signal CLX through the shift register of the data side drive circuit 104. As a result, NAND1
60a, the sampling timing signal SL1-Data1 is output via the inverter 162a, the sample hold switch 106a is turned on, and the image signal Data1 is output.
Is output to the data line 112a.

On the other hand, the counter 26 starts counting by DX, and stops counting by Data1, which is taken out of the panel from the data line 112a. The count result of the counter 26 is latched in the register 25,
The counter 22 is preset as an initial value to be used for compensating for a delay time in the next field (or frame). Note that the latch timing of the register 25 is determined by the counter 26 from the generation of the vertical synchronization signal VSYNC.
Latches the result of the counter 26 after the elapse of the period until the count stops.

According to such a configuration, the dummy circuit 27
, The delay time can be measured during the vertical period. Normally, several pixels close to the periphery (upper, lower, left, and right) of the pixel area of the liquid crystal panel are not made to contribute to display as dummy pixels. Therefore, the data line 102a
Is a dummy data line connected to the dummy pixel. Even if a leader line is added to the data line 102a for measuring the delay time, the display has no effect.

The input signal DX is the clock signal OSC
Since the pulse is output by counting the output of I, it is generated even during the vertical retrace period. However, since the input signal DY for starting scanning is not output to the scanning side driving circuit, no scanning signal is output. Therefore, the data line driving circuit operates during the vertical scanning period, but the display is not rewritten.

The output of another data line can be taken out and the delay time can be measured. That is, as in the first embodiment, when taking out the output of the sample hold switch 106e and measuring the delay, the counter 26 takes out the output from the data line 112e and stops counting. Similarly, the count result is subtracted from the half cycle of the clock signal CLX1, and the counter value is preset to the counter 22. 4.3. Further, the data side driving circuit 104 and the sample hold switch 106a,
An embodiment in which the delay times of b, c,... itself are measured, and the contents of the register 25 are set based on the result will be described.

FIG. 9 shows a modification of this embodiment. FIG.
In the case where the counter 26 stops counting STOP, the data line 112a
The timing at which the precharge voltage applied to the image signal Data1 that has undergone phase development appears via the sample-and-hold switch 106a is extracted and input. The input signal DX generated during the vertical return line period is transmitted to the shift register of the data side driving circuit 104 by the clock signal CLX.

As a result, the sampling timing signal SL 1-1 is supplied via the NAND 160 a and the inverter 162 a.
Data1 is output. On the other hand, before the occurrence of DX, the TFT 1 turned ON by the precharge timing signal PR
The precharge voltage VP is applied to the data line 112 via the line 70a.
a is applied. Therefore, during the vertical retrace period, Da
Since the image signal is not output at ta1, when the switch 106a is turned on, the precharge voltage is output in reverse to Data1.

Further, the counter 26 starts counting by DX, and the data taken out of the panel is read out.
1 stops counting. The count result of the counter 26 is latched in the register 25 and used for compensating the delay time in the next field (or frame).
The counter 22 is preset as an initial value. In addition,
The latch timing in the register 25 is determined by the vertical synchronization signal V
After a period from the occurrence of SYNC to the time when the counter 26 stops counting, the result of the counter 26 is latched.

According to such a configuration, the dummy circuit 27
, The delay time can be measured during the vertical flyback period. Normally, several pixels near the periphery of the pixel area of the liquid crystal panel (up, down, left, and right) are set as dummy pixels so as not to contribute to display. Therefore, the data line 102
a is a dummy data line connected to the dummy pixel.
Use of the data line 102a for delay time measurement does not affect display.

4.4. In the configuration of FIG. 4, the data side driving circuit 104 and the sample hold switch 106
a, b, c,..., cause delays, in which the sample and hold switches 106a, b, c,.
The delay time in the data-side driving circuit 104 is larger than the delay time in. Therefore, the data side driving circuit 1
If the delay time of 04 is sufficient, the dummy circuit 27 is connected to the clocked inverter 271, the inverter 2
It is also conceivable to configure only with 72, NAND circuit 273, and inverter 274.

4.5. In the above embodiments and modifications, the description has been made on the assumption that the timing circuit block 20 is configured on a separate substrate from the liquid crystal panel block 10. However, the timing circuit block 20 is also configured on the element substrate of the liquid crystal panel block 10. May be formed.

4.6. In the second and third embodiments, the liquid crystal projector 1100 and the personal computer 1200 have been described as examples of the electronic devices. However, it is needless to say that a liquid crystal panel may be applied to various electronic devices other than these.

[0077]

As described above, according to the present invention,
Since the timing of the clock signal is automatically adjusted based on the delay time of the data-side drive circuit or the dummy circuit, the adjustment operation can be simplified while maintaining high image quality.

[Brief description of the drawings]

FIG. 1 is a timing circuit block 20 according to a first embodiment.
It is a block diagram of.

FIG. 2 is a plan view of a liquid crystal projector 1100 according to a second embodiment.

FIG. 3 is a personal computer 12 according to a third embodiment.
00 is a front view of FIG.

FIG. 4 is an overall block diagram of a conventional liquid crystal display device and the liquid crystal display device of the first embodiment.

FIG. 5 is a circuit diagram of a data-side driving circuit 104 of the conventional liquid crystal display device and the liquid crystal display device of the first embodiment.

FIG. 6 is a timing chart of FIG.

FIG. 7 is a block diagram of a conventional timing circuit block 20.

FIG. 8 is a block diagram of a modification of the first embodiment.

FIG. 9 is a block diagram of another modification of the first embodiment.

FIG. 10 is a timing chart of each unit of the first embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Liquid crystal panel block 20 Timing circuit block 21 Oscillation circuit 22 Counter 23 Decoder 25 Register 26 Counter 27 Dummy circuit 30 Data processing block 32 Phase expansion circuit 34 Amplification / inversion circuit 100 Pixel part 104 Data side drive circuit 105 Scan side drive circuit 106a, b, c,... Sample hold switch (switching element) 110a, b, c,... Scan signal line 112a, b, c,... Data signal line 114 TFT 116 Liquid crystal cell 120, 130, 140, 150 Shift register 121a Clocked inverter 121b Inverter 121c Clocked inverter 122a Clocked inverter 122b Inverter 122c Clocked inverter 123a Clocked inverter 130, 140, 150 Shift register 160a, b, c,... NAND circuit 162a, b, c,... Inverter 170 Precharge circuit 271 Clocked inverter 272 Inverter 273 NAND circuit 274 Inverter 275 Sample hold switch (switching element)

Claims (8)

[Claims] 1. A plurality of data signal lines to which data signals are supplied, a plurality of scanning signal lines intersecting the data signal lines, and a matrix corresponding to the intersection of the data signal lines and the scanning signal lines. And a pixel provided with a data signal of a corresponding data signal line when a predetermined scanning signal is supplied to the corresponding scanning signal line. A data line driving circuit for supplying the data signal to the data signal line in synchronization with a dummy circuit simulating at least a part of the data line driving circuit; and measuring a delay time of the dummy circuit. A timing adjustment circuit that adjusts the timing of the clock signal based on the measured delay time. 2. The drive circuit according to claim 1, wherein said data line drive circuit and said dummy circuit are formed on the same substrate. 3. The data line driving circuit includes: a shift register that sequentially transmits an input signal; and a switching element that is controlled based on a timing of an output signal of each stage of the shift register. At least one of the shift registers
3. The driving circuit according to claim 2, wherein the driving circuit comprises a circuit corresponding to stages and a switching element controlled based on the timing of the output signal. 4. A plurality of data signal lines to which data signals are supplied, a plurality of scanning signal lines intersecting the data signal lines, and a matrix corresponding to the intersection of the data signal lines and the scanning signal lines. And a pixel provided with a data signal of a corresponding data signal line when a predetermined scanning signal is supplied to a corresponding scanning signal line. A data line driving circuit for supplying the data signal to a corresponding data signal line in synchronization with the data line driving circuit; a delay time measuring circuit for measuring a delay time of the data line driving circuit; and a clock signal based on the measured delay time. And a timing adjusting circuit for adjusting the timing of the driving. 5. A precharge circuit for applying a precharge voltage to the data signal line, wherein the data line drive circuit sequentially shifts an input signal, and an output signal of each stage of the shift register. A switching element controlled by the timing of the above, wherein the delay time measurement circuit, after an input signal is supplied to the shift register, a precharge voltage applied to the data line at an input terminal of the switching element 5. The driving circuit according to claim 4, wherein a time until it appears is measured as the delay time. 6. The drive circuit according to claim 5, wherein said data line drive circuit and said precharge circuit are formed on the same substrate. 7. A display device comprising the drive circuit according to claim 1. 8. An electronic apparatus comprising the display device according to claim 7.