JPH11119979A - Parallel addition / subtraction circuit - Google Patents

Abstract

[PROBLEMS] To provide a high-speed parallel addition / subtraction circuit. SOLUTION: A carry select type addition / subtraction circuit capable of performing parallel addition / subtraction is provided with all 0s as carry from the lower side to a higher-order arithmetic circuit, thereby providing 1
The pair of operation circuits perform the same operation, the operation results of the plurality of operation circuits are separated, and the operation result for each of the divided bit strings is independently obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an addition / subtraction circuit, and more particularly to an addition / subtraction circuit used for a processor supporting a multimedia function.

[0002]

2. Description of the Related Art As a conventional addition / subtraction circuit, there is a carry select type addition / subtraction circuit. What is the carry select method?
In order to increase the operation speed, an upper-bit operation is performed without waiting for the carry of the lower-bit adder circuit. Are prepared, and two types of the same addition result are selected by carry from the lower bit addition circuit. The basic structure of such a carry-select type addition / subtraction circuit is, for example, a "high-speed computer system" (translator: Yasushi Kogoshi, publishing office: Modern Science Company, publication date: September 1, 1980) Date).

As a conventional carry select type addition / subtraction circuit, there is one as shown in FIG. This carry-select type addition / subtraction circuit comprises an addition circuit 111 of lower 16 bits.
And two adder circuits 11 for performing the operation of the upper 16 bits
3 and 115, each of which can independently perform 16-bit addition. The outputs of the upper 16-bit addition circuits 113 and 115 include a selector 119 for selecting the outputs of the two upper addition circuits.
One of the lower 16 bits is selected according to the carry from the adder circuit 111 via the carry control circuit 111 for inputting the carry to the bit adder circuits 13 and 15.

There is also a technique for adding a parallel processing function by using such a carry select type addition / subtraction circuit. In this case, since the upper bit addition circuit and the lower bit addition circuit are divided, a plurality of parallel operations can be performed by controlling the carry to the upper bit addition circuit. For example, when used as one adder circuit, the carry of the lower bit adder circuit is directly input to the upper bit adder circuit. In addition, when adding in parallel, if the carry from the lower bit addition circuit is ignored and 0 is input to the upper bit addition circuit, an addition result of only the upper bits can be obtained.

[0005]

However, in the case of this conventional circuit, by adding a control circuit to the upper bit addition circuit and the lower bit addition circuit, the added circuit can be used when one addition circuit is used. Minute delay, which becomes more pronounced as the number of divisions increases. For this reason, when high-speed processing is required, it is a serious problem.

An object of the present invention is to provide a high-speed addition / subtraction circuit.

An object of the present invention is to provide an efficient carry select type addition / subtraction circuit.

[0008]

In order to achieve the above object, a parallel addition circuit according to the present invention divides one adder into a plurality of parts and performs addition in parallel. It is characterized in that the division unit is controlled by controlling the addition content of the addition result selected by the carry from the lower order by the input control signal.

Preferably, by adjusting the control signal,
It is characterized in that it is possible to execute division addition in which division units are unequal.

According to another aspect of the present invention, a single subtracter is divided into two or more plural units, and a parallel subtraction circuit capable of performing subtraction in parallel enters a divided minimum unit subtractor. The division unit is controlled by controlling the content of the subtraction of the subtraction result selected by the carry from the lower order with a control signal.

Preferably, by adjusting the control signal,
It is characterized in that it is possible to execute division subtraction in which the division unit is not uniform.

[0012] Further, preferably, by adjusting the control signal, simultaneous and parallel operations in which addition and subtraction are confused are enabled.

According to still another aspect of the present invention, a parallel addition / subtraction circuit according to the present invention comprises a plurality of operations for independently performing operations on respective divided bit strings of two operands each divided into a plurality of bit strings. And a processing circuit for combining and outputting the operation results of the plurality of operation circuits to obtain the operation results of the two operands, wherein each of the plurality of operation circuits other than the lowest operation circuit has a pair. The parallel subtraction circuit, which performs a calculation when the carry from the lower order is 0 and 1 and selects one according to the carry from the lower order in the processing circuit, A pair of arithmetic circuits is provided for the arithmetic circuits other than the arithmetic circuit.
In the case of division addition, both carry out the operation when the carry from the lower order is φ, and in the case of the division subtraction, both carry out the operation when the carry is 1, and either of them is selected by the actual carry from the lower order. In this case, the same value is output even when the operation is performed, whereby the operation results of the plurality of operation circuits are separated to obtain the operation result for each of the divided bit strings.

Therefore, in the addition / subtraction circuit according to the present invention, the upper arithmetic circuit is provided with all 0s as carry from the lower order in the case of addition, and all 1s in the case of subtraction, whereby a pair of arithmetic circuits is formed. The same operation will be performed. In this case, the operation results of the plurality of operation circuits are separated, and the operation results for each of the divided bit strings are independently obtained. Further, even by performing such parallel addition and subtraction, time loss does not increase.

[0015]

FIG. 1 is a circuit diagram of a parallel addition / subtraction circuit according to a first embodiment of the present invention. This parallel addition / subtraction circuit has a structure in which a 16-bit parallel addition function is added to a 32-bit addition circuit in which the upper bit addition circuit uses the carry select method.

The carry select type addition / subtraction circuit of this embodiment comprises an addition circuit 11 of lower 16 bits and two addition circuits 13 and 15 for performing an operation of upper 16 bits.
16-bit addition can be performed independently of each other. The outputs of the upper 16-bit addition circuits 13 and 15 include a selector 119 for selecting the outputs of the two upper 16-bit addition circuits.
15 is also provided with a carry control circuit for inputting carry. Next, a specific operation will be described.

In the case of 32-bit addition, two addition circuits 1
A and B data are input to 3 and 15, respectively. As for the carry input at that time, "1" is input to one side and "0" is input to the other side. Thus, an addition result is prepared when the carry from the lower order is "1" or "0". At the same time, the lower 16-bit adder circuit
The inputs A and B are added, and a 16-bit addition result and a carry are output. The carry of the lower adder circuit is the upper 16
From the addition results prepared by the bit addition circuit, the result of the higher-order addition circuit having the same carry input as the carry of the lower-order addition circuit is selected, and the addition result and the carry of the upper 16 bits are output.

On the other hand, A and B data are also input to the lower 16-bit addition circuit 11. As the carry input at that time, in the case of addition, "0" is input. The carry of the adder circuit 11 is input to the selector 19, and one of the upper 16-bit adder circuits 13 and 15 is selected.
A 32-bit addition result and carry are obtained.

In the case of parallel 16-bit addition, data of A and B are input to the upper / lower-order addition circuit as in the case of 32-bit addition, but both carry "0" to the carry of the two upper 16-bit addition circuits. ". As a result, the top 1
The same result is output for both of the 6-bit addition results.
That is, no matter which result is selected by the selector 19, since the addition result of the upper 16 bits is the same, the addition result and the carry for the upper 16 bits are obtained without being affected by the carry of the lower 16 bit addition circuit. Can be In addition,
In the addition of the lower 16 bits, the result of addition and the carry of the lower 16 bits are obtained by the same processing as that of the 32-bit addition.

In addition, since subtraction is performed using a complement representation, it can be realized by inverting the data to be subtracted and adding "1" to the least significant bit. In the case of 32-bit subtraction, the data on the subtraction side is inverted, "1" is input to the carry input of the lower adder circuit, and then the carry inputs of the upper adder circuit are set to "0" and "1", respectively. 32
The result is similar to the addition of bits. In the case of the parallel 16-bit subtraction, similarly to the 32-bit subtraction, "1" is input to the carry input of the lower 16-bit adder circuit after the data to be drawn is inverted, and the carry input of the upper 16-bit adder circuit is performed. By inputting "1" to both of them, the upper and lower subtraction results can be obtained.

FIG. 2 is a circuit diagram of a parallel addition / subtraction circuit according to a second embodiment of the present invention. This embodiment uses 32bi
This is an example of a parallel adder / subtracter capable of performing t arithmetic processing, 16-bit arithmetic 2-parallel processing, and 8-bit arithmetic 4-parallel processing. The component is an 8-bit adder / subtracter 25, 26- which is a minimum unit of the parallel operation processing.
1, 26-2, 26-3, an operation control signal generation circuit 23 that generates an operation control signal to the adder / subtracter, a carry generation circuit 24 that generates a carry when performing an operation with a size larger than 8 bits, Selecting circuits 29-1, 29-2, 29 for selecting the operation result generated by the adder / subtractor from
-3. It is assumed that the adder / subtractor according to the present embodiment also performs the operation by the carry selection method. That is,
The calculation is performed by generating two types of calculation results in the case where there is a carry from the lower order in advance, and in the case where there is no carry, and selecting from the same two types of arithmetic results by the actual carry from the lower order.

In this embodiment, 32-bit operation processing, 16-bit operation 2-parallel processing, and 8-bit operation 4-parallel processing can be performed. For this purpose, the operation control signal generation circuit generates two control signals for each 8-bit operation unit, which is the minimum unit of operation, except for the lowest-order 8-bit operation unit, in addition, subtraction, and division modes. One control signal is input to the lowest 8-bit arithmetic unit.

The control signals output from the operation control signal generation circuit are shown below.

Signal z3 p3 z2 p2 zl pl z0 32bit addition 0 1 0 1 0 1 0 32bit subtraction 0 1 0 1 0 1 1 16bit addition 0 1 0 0 0 1 0 16bit subtraction 0 1 1 1 0 1 1 8bit addition 0 0 0 0 0 0 0 8-bit subtraction 1 1 1 1 1 1 1 Here, z3 and p3 are control signals input to the most significant 8-bit arithmetic unit, z2 and p2 are control signals input to the next 8-bit arithmetic unit, z
1, p1 is the control signal to enter the next arithmetic unit, z0 is the lowest 8
This is a control signal that enters the bit calculator.

The subtraction process is performed with AB = A + (B's two's complement representation) = A + (B bit inversion) +1. Therefore, in each of the arithmetic units, an inverting circuit for inverting the input B in the case of subtraction and a circuit for processing the control signal coming from the control signal generating circuit as 1 to be added to the end of the above equation, at the stage preceding the 8-bit adder. Consists of

When the signal is "0", the 8-bit operation unit outputs the operation result when there is no carry from the lower bit and the carry output to the upper bit when the signal is "0".
The calculation result when there is a carry from the lower order and the carry to the upper order are output. Except for the least significant 8-bit arithmetic unit, each high-order 8-bit arithmetic unit corresponds to each two control signals,
Output two operation results. For example, in the most significant 8-bit operation unit, sumz3 = A [31:24] + (B [31:24] ＾ sub) + z3 sump3 = A [31:24] + (B [31:24] ＾ sub) + p3 Coutz3 is an overflow carry signal in the operation of sumz0, and coutz3 is an overflow carry signal in the operation of sump0.

Here, sumz3 is an operation result corresponding to the control signal z3, and sump3 is an operation result corresponding to the control signal p3.
A [31:24] indicates the most significant 8 bits of the input operand data. sub
Indicates that the operation is a subtraction. “＾” is sub
Indicates that B [31:24] is bit inverted.

The carry generation circuit performs the carry signal coutz3, coutp3, coutz2, co
utp2, coutz1, coutp1, coutz0 are input, and the actual carry input signal to each 8-bit arithmetic unit is generated from the carry. One example of such a circuit is shown in FIG. Here, three multiplexers are used. Also, FIG.
If a circuit as shown in FIG. 1A is used, a higher-speed operation can be performed. In this case, as shown in FIG.
A multiplexer with two inputs and two outputs is equivalent to two multiplexers, and is therefore composed of seven multiplexers.

Next, an example of a specific calculation will be described. For example 32
Consider the case of adding bit data, A = 0xFFFFFFFF, B = 0x00000001 (hexadecimal notation). In the 32-bit addition mode, each control signal from the control signal generation circuit is a signal z3 p3 z2 p2 zl pl z0 32-bit addition 0 1 0 1 0 1 0, and data input to each 8-bit arithmetic unit is A3 = 0xFF B3 = 0x00 A2 = 0xFF B2 = 0x00 A1 = 0xFF B1 = 0x00 A0 = 0xFF B0 = 0x01, and the output of each arithmetic unit is sumz3 = 0xFF coutz3 = 0 sump3 = 0x00 coutp3 = 1 sumz2 = 0xFF coutz2 = 0 sump2 = 0x00 coutp2 = 1 sumz1 = 0xFF coutz1 = 0 sump1 = 0x00 coutp1 = 1 sumz0 = 0x00 coutz0 = 1. Therefore, the actual carry input to each 8-bit arithmetic unit is

[Equation 1] tcinl = coutz0 = 1 tcin2 = coutzl or (coutpl and coutz0) = 0 or (1 an
d 1) = 1 tcin3 = coutz2 or (coutp2 and coutzl) or (coutp2 a
nd coutpl and coutz0) 0or (1 and 0) or (1 and 1 and
1) = 1 ovfl = coutz3 or (coutp3 and coutz2) or (coutp3 a
nd coutp2 and coutzl) or (coutp3 and coutp2 and cou
tpl and coutz0) 0 or (1 and 0) or (1 and 1 and 0) o
r (1 and 1 and 1 and 1) = 1 and the output sumz1 of the 8-bit arithmetic unit at the first byte from the least significant
In sump1 and sump1, since tcin1 = 1, sump1 is selected as the final output. Similarly, in this example, sump2 and sump3 are selected, and as a result, the 32-bit output becomes 0x00000000.

Here, the input data is the same, that is, 2 bits of 16 bits.
Consider the case of performing a parallel operation. Similarly, each control signal from the control signal generation circuit is a signal z3 p3 z2 p2 zl pl z0 16-bit addition 0 1 0 0 0 10 and the output of each arithmetic unit is sumz3 = 0xFF coutz3 = 0 sump3 = 0x00 coutp3 = l sumz2 = 0xFF coutz2 = 0 sump2 = 0xFF coutp2 = 0 sumzl = 0xFF coutzl = 0 sumpl = 0x00 coutpl = l sumz0 = 0x00 coutz0 = l. Therefore, the actual carry input to each 8-bit arithmetic unit is

[Equation 2] tcinl = coutz0 = l tcin2 = coutzl or (coutpl and coutz0) = 0 or (l an
dl) = l tcin3 = coutz2 or (coutp2 and coutzl) or (coutp2 a
nd coutpl and coutz0) 0 or (l and 0) or (0 and l an
dl) = 0 ovfl = coutz3 or (coutp3 and coutz2) or (coutp3 an
d coutp2 and coutzl) or (coutp3 and coutp2 and cout
pl and coutz0) 0 or (l and 0) or (0 and l and 0) or
(l and 0 and l and l) = 0, and the output sumz1 of the 8-bit arithmetic unit at the first byte from the least significant
In sum and sum1, since tcin1 = 1 as in the case of 32-bit operation, sum1 is selected as the final output. 2byt from bottom
In the e-th eye, since tcin2 = 1, sump2 is selected.However, the control signal outputs the operation result when there is no carry from lower-order in both sumz2 and sump2. Even if sump2 is selected, carry-up from lower-order is performed. Is output when there is no. In the highest-order 8-bit arithmetic unit, since coutp2 indicating whether the carry from the lower 16 bits propagates in the operation of the second byte from the lower byte is 0, the carry does not propagate to the highest order, and tcin3 = 0, and sumz3 Is selected, and as a result, the 32-bit output becomes 0xFFFF0000.

In the case of 8-parallel 4-parallel operation, the signals z3 p3 z2 p2 zl pl z0 8-bit addition 0 0 0 0 0 0 0, and the output of each arithmetic unit is sumz3 = 0xFF coutz3 = 0 sump3 = 0xFF coutp3 = 0 sumz2 = 0xFF coutz2 = 0 sump2 = 0xFF coutp2 = 0 sumzl = 0xFF coutzl = 0 8umpl = 0xFF coutpl = 0 sumz0 = 0x0O coutz0 = 1. Therefore, the true carry input to each 8-bit operation unit is tcinl = 1 tcin2 = 0 tcin3 = 0, sumz3, sumz2, and sump1 are selected, and the output result is 0xFFFFFF00.

Next, an example of executing the subtraction will be described.

When A = 0x222222222 B = 0xcccccccc,
In 32-bit subtraction, the signal z3 p3 z2 p2 zl pl z0 32-bit subtraction 0 1 0 1 0 1 1 and the output of each arithmetic unit is sumz3 = 0x55 coutz3 = 0 sump3 = 0x56 coutp3 = 0 sumz2 = 0x55 coutz2 = 0 sump2 = 0x56 coutp2 = 0 sumzl = 0x55 coutzl = 0 sumpl = 0x56 coutpl = 0 sumz0 = 0x56 coutz0 = 0. The true carry input to each 8-bit arithmetic unit is tcinl = 0 tcin2 = 0 tcin3 = 0, sumz3, sumz2, and sumz1 are selected, and the output result is 0x55555556.

In the 16-bit 2-parallel subtraction, the signal z3 p3 z2 p2 zl pl z0 16-bit subtraction is 0 1 1 1 0 1 1, and the output of each arithmetic unit is sumz3 = 0x55 coutz3 = 0 sump3 = 0x56 coutp3 = 0 sumz2 = 0x56 coutz2 = 0 sump2 = 0x56 coutp2 = 0 sumzl = 0x55 coutzl = 0 sumpl = 0x56 coutpl = 0 sumz0 = 0x56 coutz0 = 0. The true carry input to each 8-bit operation unit is tcinl = 0 tcin2 = 0 tcin3 = 0, and sumz3, sumz2, and sumz1 are selected. By the control signal, sumz2 outputs the same value as sump2, and the output result is It becomes 0x55565556.

In the 8-bit 4-parallel subtraction, the signal z3 p3 z2 p2 zl pl z0 8-bit subtraction is 1 1 1 1 1 1 1 and the output of each arithmetic unit is sumz3 = 0x56 coutz3 = 0 sump3 = 0x56 coutp3 = 0 sumz2 = 0x56 coutz2 = 0 sump2 = 0x56 coutp2 = 0 sumzl = 0x56 coutzl = 0 sumpl = 0x56 coutpl = 0 sumz0 = 0x56 coutz0 = 0. The true carry input to each 8-bit operation unit is tcinl = 0 tcin2 = 0 tcin3 = 0, sumz3, sumz2, and sumz1 are selected, and the output result is 0x56565656.

This circuit controls the bit inversion of each operation unit for each operation unit, and if the control signal generation circuit is associated, addition and subtraction can be performed in parallel. For example, when the upper 16 bits are subtracted and the lower 16 bits are added in a 16-bit two-parallel addition / subtraction, the addition / subtraction control signal sub input to each arithmetic unit is output from the upper subsub and su.
When b2, sub1, and sub0 are set, sub3 = 1 sub2 = 1 subl = 0 sub0 = 0 Each control signal can be controlled by the signal z3 p3 z2 p2 zl pl z0 16-bit addition / subtraction 0 1 1 1 0 1 0.

In addition to the above example, if a control signal generation circuit is applied, the number of divisions can be changed. For example, in order to realize the addition of the upper 8 bits and the addition of the lower 24 bits, a control signal is output as follows.

The control signal is As another example, when adding the upper 24 bits and subtracting the lower 8 bits, a control signal is output as follows.

The control signal is In the carry generation circuit of the type in which the carry path of the part to be divided is clearly visible as described in the first embodiment, division control can be realized by embedding a control circuit in the carry path as in the conventional example. But for example DEC
In a carry generation circuit such as a carry array used in an adder used in an ALPHA chip, it is very difficult to include a division control circuit. In this case, particularly, the circuit scale increases and the speed increases. The drop is noticeable.

On the other hand, as can be seen from the present description, in the circuit of the present invention, the carry generation circuit higher than the minimum operation unit is the same as that of the conventional adder, including the above-mentioned carry array system. Also, the split parallel operation can be realized without any problem.

According to the present invention, it is necessary to input the operation control signal to the operation unit of the minimum operation unit. Although it depends on the design of the arithmetic unit, it is easier to design the arithmetic unit if the operation control signal is determined at the same time as or before the data to be operated is input to the arithmetic unit if possible. Fortunately, in the current processor, there is a time from when an instruction is determined to when actual data to be operated reaches an arithmetic unit. For example, RISC
The processor reads the data in the register file from the instruction read from the instruction memory, and transfers the data as operation target data to the arithmetic unit. Therefore, there is a time from when the instruction is read to when the data arrives at the arithmetic unit, and it is considered that there is sufficient time for the arithmetic control signal generation circuit of the present invention to generate a signal. Time can hardly be a critical path for the whole circuit. For this reason, in most practical cases, the operation control signal can be considered to be determined before the data to be operated reaches the operation unit.

In this case, the circuit delay for inputting the operation control signal to each operation unit of the minimum operation unit can be concealed. FIG.
FIG. 9 shows a third embodiment of the present invention. In this embodiment, an inverting circuit 31 that receives a signal indicating addition / subtraction is provided in parallel with the operation control signal generation circuit 23 of the fourth embodiment.

In the normal addition / subtraction circuit, a bit inversion circuit is provided for subtraction as described in the second embodiment. Specifically, there is usually one exclusive OR gate,
A subtraction signal indicating that the instruction is a subtraction instruction and a decrement are input, and in the case of subtraction, bit inversion of the decrement is output by exclusive OR. The result of addition and subtraction and carry are
It is generated from the addend / subtract after passing through the exclusive OR. For this reason, the added / subtracted number has a time margin while the added / subtracted number passes through the exclusive OR.

On the other hand, the arithmetic control signal described in this patent is:
This is equivalent to the carry input to the least significant bit.
Therefore, the operation result obtained from the add / subtract number, add / subtract number, and input carry is: add / subtract number xor add / subtract number after bit inversion xor input carry = add / subtract number xor (addition / subtraction xor subtraction signal) xor input carry = add / subtract number xor input carry xor (addition / subtraction number xor subtraction signal) = (addition / subtraction number xor input carry) xor (addition / subtraction number xor subtraction signal), and addition / subtraction is performed in parallel with addition / subtraction of the exclusive OR with the subtraction signal It means that the exclusive OR of the number and the incoming carry can be taken.

For this reason, the delay caused by the addition of the operation control signal can be completely concealed. When the third embodiment is applied to the circuit of the second embodiment, a 32-bit addition / subtraction circuit, A parallel addition / subtraction circuit having substantially the same speed and having various types of division operation functions can be realized.

[0046]

Therefore, in the addition / subtraction circuit according to the present invention,
By giving all 0s as the carry from the lower order to the higher-order arithmetic circuit, a pair of arithmetic circuits performs the same operation, so that a high-speed carry-select type addition / subtraction circuit is realized.

[Brief description of the drawings]

FIG. 1 shows a parallel addition circuit according to a first embodiment of the present invention.

FIG. 2 shows a parallel addition circuit according to a second embodiment of the present invention.

FIG. 3 shows an example of a carry generation circuit used in the parallel addition circuit of the present invention.

FIG. 4 shows another example of the carry generation circuit used in the parallel addition circuit of the present invention.

FIG. 5 shows a parallel addition circuit according to a third embodiment of the present invention.

FIG. 6 shows a prior art parallel addition circuit.

[Explanation of symbols]

 Reference Signs List 11 adder circuit 13, 15-bit adder circuit 13, 15 adder circuit 19 selector 23 arithmetic control signal generator circuit 24 carry generator circuit 25, 26 adder / subtractor 29 selector circuit 111 carry control circuit 111 adder circuit 113, 115 bit adder circuit 113, 115 Adder circuit 119 Selector

Claims (12)

[Claims] An upper pair of unit adders generates in advance two types of addition results when there is a carry from the lower order and when there is no carry from the lower order, and the two types of addition results are obtained by the actual carry from the lower order. In the carry-selection type addition circuit that selects one of the two, the pair of unit addition circuits both generate an addition result when there is no carry from the lower order, and whichever is selected by the actual carry from the lower order. A parallel addition / subtraction circuit characterized in that an addition result is output when there is no carry in a higher order, thereby dividing an addition process and enabling a plurality of additions at the same time. 2. The parallel addition / subtraction circuit according to claim 1, wherein the number of unit addition circuit pairs for generating two types of addition results in advance is two or more, and the number of data divisions in the addition processing is three or more. . 3. The method according to claim 2, wherein, for each unit for generating each addition result, an addition result with and without a carry from the lower order is generated or a carry from both lower order is not generated. A parallel addition / subtraction circuit characterized in that it is possible to execute divisional addition in which the data division unit of functional addition is unequal by adjusting whether to generate an addition result in the case. 4. A pair of upper unit subtraction circuits generates in advance two types of subtraction results when there is a carry from the lower order and when there is no carry from the lower order. In the carry selection type subtraction circuit that selects one of the two, the pair of unit subtraction circuits generates a subtraction result when the data to be operated on by the same unit subtraction circuit is the lowest, and generates the actual lower result. A parallel addition / subtraction circuit characterized in that a subtraction result is output when the data to be operated is at the lowest order regardless of which one is selected by the carry from the subroutine, so that a plurality of subtractions can be performed simultaneously. 5. The parallel addition / subtraction circuit according to claim 4, wherein the number of unit subtraction circuit pairs for generating two types of subtraction results in advance is two or more, and the number of data divisions in the subtraction processing is three or more. . 6. The subtraction circuit according to claim 5, wherein a subtraction result is generated for each unit for generating a subtraction result when there is a carry from the lower order and when there is no carry from the lower order, or a bidirectional unit subtraction circuit is in charge. Parallel addition / subtraction characterized in that by performing a subtraction when the data to be operated is at the lowest order, it is possible to execute the divisional subtraction in which the data division unit of the functional subtraction is unequal by adjusting the subtraction result. circuit. 7. A pair of high-order unit addition / subtraction circuits generates in advance two types of addition / subtraction results when there is a carry from the lower order and when there is no carry, and calculates the two types of addition / subtraction results by the actual carry from the lower order. In the carry-selection type addition / subtraction circuit for selecting one of the above, in both of the pair of unit addition / subtraction circuits, an addition / subtraction result when the operation data handled by the same unit addition / subtraction circuit is the lowest order is generated, and the actual lower order is generated. Regardless of which is selected by the carry from, the result of addition and subtraction when the operand data is the lowest order is output,
A parallel addition / subtraction circuit, which divides addition / subtraction processing and enables a plurality of additions / subtractions at the same time. 8. The method according to claim 7, wherein the number of unit addition / subtraction circuit pairs for generating two types of addition / subtraction results in advance is two or more;
A parallel addition / subtraction circuit, wherein the number of data divisions in the addition / subtraction processing is 3 or more. 9. The addition / subtraction circuit according to claim 8, wherein, for each unit for generating each addition / subtraction result, an addition / subtraction result with and without a carry from the lower order is generated, or a bidirectional unit addition / subtraction circuit is in charge. Parallel addition / subtraction characterized in that by performing addition / subtraction when the data to be operated is at the lowest order, it is possible to perform divisional addition / subtraction with unequal data division units for functional addition / subtraction. circuit. 10. The parallel addition / subtraction circuit according to claim 7, wherein the arithmetic functions of the unit addition / subtraction circuit and the least significant addition / subtraction circuit are independently adjusted to enable simultaneous parallel addition / subtraction in which addition and subtraction are confused. . 11. A parallel addition / subtraction method according to claim 8, wherein the arithmetic functions of the unit addition / subtraction circuit and the least significant addition / subtraction circuit are independently adjusted to enable simultaneous parallel addition / subtraction in which the addition and the subtraction are confused. circuit. 12. The parallel addition / subtraction according to claim 9, wherein the arithmetic functions of the unit addition / subtraction circuit and the least significant addition / subtraction circuit are independently adjusted to enable simultaneous parallel addition / subtraction in which the addition and the subtraction are confused. circuit.