JPH0251732A - Floating point computing element - Google Patents

Abstract

PURPOSE:To perform the division of floating points at a high speed by calculating 2-BXi necessary for a divisor based on a convergent method in a comparatively short time just with the simple improvement of a floating point multiplier. CONSTITUTION:A multiplication circuit 1, a bit inverting circuit 2 and an addi tion circuit 4 calculates 2-BXi which is necessary when the floating point divi sion of A/B is carried out based on a convergent method. In this case, 0<BXi<=1 (i=0, 1...) is satisfied and X0 and Xi show the initial value of the reciprocal of a divisor and the i-th approximate value of the reciprocal of the divisor. Then the circuit 1 calculates Xi+1=Xi (2-BXi) which points the approximate value of the reciprocal of said divisor. Then the data on Xi+1 obtained by repeating each calculation by the prescribed frequency is applied to the circuit 1 together with the data A on a dividend. In such a way, the division of A/B is carried out. As a result, the division of floating points can be performed at a high speed.

Description

[Detailed description of the invention] 〔overview〕.

To speed up the iterative calculation performed when calculating the reciprocal of a divisor based on a convergence method, and to realize high-speed processing of floating-point division, regarding a floating-point arithmetic unit, in particular, technology for performing division processing on numerical values in floating-point notation. For the purpose of a bit inversion circuit that inverts bits; a circuit that selects either the output of the bit inversion circuit or the output of the multiplication circuit in response to a control signal; and the output of the multiplication circuit is selected in the selection circuit. When the output is rounded in response to a predetermined rounding mode signal, and when the output of the bit inversion circuit is selected in the selection circuit, the least significant bit of the output is set to 1 in response to the control signal. 2-BXi, which is necessary when performing A/B floating point division based on the convergence method, <BX(≦
1 (i=0, l,...), Xo is the initial value of the reciprocal of the divisor, X is the i-th approximation of the reciprocal of the divisor, and the calculation is performed using the multiplication circuit, bit inversion circuit, and addition. Xi, which is performed by a circuit and then indicates an approximation of the reciprocal of the divisor;
, =Xi (2-BXi) (7) Calculate the corresponding power 31
X, which is obtained by performing each calculation a predetermined number of times using one circuit. The multiplication circuit is configured to perform the division of A/B by applying data of 1 together with data A of the dividend to the multiplication circuit.

[Industrial application field]

The present invention relates to a floating-point arithmetic unit, and particularly to a technique for performing division processing on numerical values in floating-point notation.

Floating point arithmetic has a wider dynamic range and higher precision than integer arithmetic. For this reason, there has been a recent trend toward demands for devices that meet various sophisticated calculation requirements, and in particular, high-speed processing regarding division has become important.

[Prior art] Conventional division methods are not limited to floating point numbers, but can be roughly divided into two types.
Two methods are used: ■ Method using subtraction and shift operations;
■Methods that use convergence methods such as the Newton-Raphson method. Method (2) is a method in which the divisor subjected to the shift operation is repeatedly subtracted from the dividend, and the separation method is known as an example thereof. Furthermore, the SRT method is known as an improved method of this separation method, but this method has the advantage of being able to obtain the quotient faster. On the other hand, the method "■" calculates the reciprocal of the divisor by calculation based on the convergence method, and obtains the quotient by multiplying it by the dividend. In this case, the number of repeated operations required until convergence is determined by the initial value of the reciprocal. The closer it is to the true value, the smaller it will be.

Many of the floating-point arithmetic units currently available use the Newton-Labrun method for division. This is due to the following reasons. Even with the high-radix SRT method, the quotient that can be found in one iteration is at most 3 to 4 bits, and to obtain the final quotient, iterative calculations about 8 times are required in single precision according to the IEEE standard. On the other hand, in the Newton-Raphson method, if the initial value of the reciprocal is given within a certain precision,
The quotient can be found by performing convergence calculations about four times. Therefore, division using the Newton-Raphson method has the advantage that the quotient can be obtained faster than other methods.

Division using the Newton-Labrun method will be explained below.

To perform division, first find the reciprocal function. For example, C
The division =A/B can be expressed in the reciprocal form of C=A (1/B).Using the Newton-Raphson method, the iterative expression of the reciprocal function (1/B) can be obtained. This is X8. , =X five (2-BXi)
, where i=0, ■, 2, . . . Here, X, is the reciprocal of the first divisor (initial value) for i=0, X, represents the i-th approximation value of (1/B), and when the initial value X0 satisfies the condition of inequality % expression % , the operation ends. A typical method for obtaining the initial value is to use about the upper 10 bits of the divisor as a pointer to a memory (ROM) such as a look-up table.

The contents of the address indicated by the divisor bits are output from the ROM as an initial value. In this case, the number of output bits (
The number of bits of the initial value X0) is the number of input bits (the upper one of the divisor
Usually, it is almost the same as 0 bit). For floating point division, the exponent and mantissa reciprocals are determined from separate look up tables (ROM).

Next, conventional division will be explained with reference to FIG. FIG. 3 shows the configuration of a floating point arithmetic unit as an example of a conventional type, and the illustrated example shows the configuration of a floating point multiplier that handles only normalized numbers.

First, two binary data A in floating point notation,
B, A=(-1)"2°-" (1,Fa), B=(-
1) sb2 "-" (x, Fb), and the processing when multiplication is performed on the data will be explained.

(Operation of mantissa part X) Mantissa parts (1, Fa), (
1, Fb) is converted to (1
, Fa) X (1, Fb) is executed. This result is 1, +nrxx... or lx
, □□...

1, XXX□... have already been normalized, but LX, XXXX...... require normalization processing.

This transfers the data (lx, □.....) to shifter 1
This is realized by shifting the exponent part by 1 bit to the right by 3, and by causing the incrementer 22 to increase the exponent part by +1 in response to the overflow instruction signal F.

Next, "rounding" processing is performed on the normalized numerical values to match the output data format. Specifically, in the rounding control circuit 14, the digits below the least significant bit (LSB) in the output data format are truncated, and the digits below the LSB are rounded down according to the preset rounding mode signal RM and the values of the digits below the LSB. It is determined whether to add 1 to the LSB. The operation of adding 1 to this LSB is executed by the incrementer 15. At this time, all data is r1
゜, overflow will occur. in this case,
Shifter 16 shifts data (LSB +1) one bit to the right in response to overflow instruction signal F2.

As a result, the final output is a normalized number.

(Calculation of exponent part) The first stage adder 20 executes the calculation (Ea+Eb), and the second stage adder 21 adds a negative bias (-BS) to the result. In other words, the operation (Ea + Eb - BS) is executed by these two adders. Next, in the third stage incrementer 22, an increment operation of +1 is performed when it is necessary to correct overflow by normalization processing. Further, in the fourth stage incrementer 23, an increment operation of +1 is performed in advance to correct overflow due to rounding processing, and one of the signals is selected in the multiplexer 24 based on the overflow signal F2.

(Operation of the sign part) This is executed by exclusive OR performed by the exclusive OR gate 30 on the code parts Sa and Sb of input data A and B, respectively.

[Problem to be solved by the invention]

When performing division processing using the conventional floating-point multiplier described above, 2-BX, which is necessary for division based on the convergence method, is
It is not possible to perform base calculations in one step. In other words, according to the configuration shown in FIG. 3, the iterative calculation performed when finding the reciprocal of the divisor based on the convergence method, that is, Xl. ,=Xi (2
-BXi), the multiplication iBX, and
? : fji calculation; 2-BX, and multiplication; Xr (28X
) (7) Three (7) arithmetic operations are required, and therefore, the entire operation processing time is long (which results in the inconvenience that it is difficult to meet the demand for speeding up).

Also, regarding the subtraction of (2-BX,), see 2. The circuit configuration shown in FIG. 3 cannot perform this calculation alone; in order to perform this operation, it is necessary to newly add an addition/subtraction circuit to the configuration shown in FIG. Even if we were to add such a circuit to calculate Xi, , = Xi (2-BX,) above, we would still have to repeatedly perform three arithmetic operations, which would require a lot of floating point division. There is still room for improvement in terms of high-speed processing.

The present invention was created in view of the problems in the prior art, and is based on a floating point system that speeds up the iterative calculations performed when calculating the reciprocal of a divisor based on the convergence method, and can also realize high-speed processing of floating point division. The purpose is to provide arithmetic units.

[Means for Solving the Problems] In order to solve the problems in the prior art described above, the floating point arithmetic unit of the present invention uses a binary system based on floating point notation, as shown in the principle block diagram of FIG. a multiplier circuit 1 that multiplies two data by the mantissa part of the data, performs normalization processing, and outputs the result; a bit inversion circuit 2 that inverts each bit of the data output from the multiplier circuit; a circuit 3 for selecting either the output of the bit inversion circuit or the output of the multiplication circuit in response to a control signal S; and a predetermined rounding mode signal when the output of the multiplication circuit is selected in the selection circuit. Rounding of the output is performed in response to R, and when the output of the bit inverting circuit is selected in the selection circuit, 1 is added to the least significant bit of the output in response to the control signal. 2-BXi, which is necessary when performing A/B floating point division based on the convergence method, provided that 0<BXi≦1( i=o, 1,...)
, Xo is the initial value of the reciprocal of the divisor; X. + = Xi (2BX= ) is calculated by the multiplication circuit, and the data of X i * l obtained by repeatedly performing each calculation a predetermined number of times is applied to the multiplication circuit together with the dividend data A, thereby achieving the above. It is characterized by performing A/B division.

[Function] According to the configuration described above, 2-BXi (however, 0<
The binary calculation of BXi≦1) is performed in one step using an improved floating point multiplier.

Therefore, when calculating the reciprocal of the divisor based on the convergence method,
,,,=Xi (2-BX,) (7) The iterative calculation is performed by calculating 2-BXi and Xi (2
Only two arithmetic operations (-BX, ) are required, and one step of operation can be omitted compared to the conventional type. This contributes to significantly shortening the overall calculation processing time, considering that iterative calculations are usually required about three to four times to obtain the quotient based on the convergence method. Therefore, floating point division can be processed at high speed.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

(Embodiment) Fig. 2 shows the configuration of the main parts of a floating-point arithmetic unit as an embodiment of the present invention. It shows the configuration.

The structural features of this embodiment include a bit inversion circuit 41 that inverts each bit of data output from the shift register between the shifter 13 and the incrementer 15 in the mantissa calculation circuit; A multiplexer 42 is provided which selects either the output or the output of the shift register in response to the division control signal DIV. When performing division processing, the division control signal DIV is set to
On the other hand, when performing normal multiplication processing, the division control signal oxv is set to #L level to select the output of the shift register 16. .

Now, suppose that the two binary input data D1 and D2 in floating point notation are D+= (1) "2"-83(1, Fa), Dt=
(1) Expressed as “2Eto” (1, Fb).

First, in the mantissa calculation circuit, 10 calculates the mantissa part (1, F
a) shows a fixed-point multiplication circuit that performs multiplication processing using (1, Fb) as a fixed-point number, and the circuit is composed of a partial product generation and addition circuit 11 and an addition circuit 12.

Reference numeral 13 denotes a shifter, which internally generates data that is shifted one bit to the right (toward the least significant bit) with respect to the data output from the adder circuit 12, and outputs this generated data from the adder circuit 2. Either one of the data
Overflow instruction signal F generated by the circuit 12
It has a function of selecting in response to the presence or absence of 1. In this embodiment, the shifted data is selectively output when the overflow instruction signal F is output.

14 is a rounding processing control circuit, which functions when performing normal multiplication processing. This rounding control circuit 1
4 cuts off the digits below the LSB in the output data format of the output data of the shifter 13 (rounding process) and adds 1 to the LSB according to the code data SN (described later) and the preset rounding mode signal RM. It has a function of determining whether to add or not and outputting a control signal RC instructing to that effect.

15 is an incrementer which increments the LSB of the output data of the multiplexer 42 (output data of the shifter 13) in response to the control signal RC from the rounding control circuit I4 when performing normal multiplication processing. J and when performing division processing, it has a function of adding 1 to the LSB of the output data of the multiplexer 42 (output data of the bit inversion circuit 41) in response to the division control signal DIν. There is. In this case, the incrementer 15 uses the register 15 when the data resulting from the addition is not normalized.
Similarly, an overflow instruction signal F2 is output.

16 is a shifter which, like the shifter 13, shifts the data output from the incrementer 15 one bit to the right (toward the least significant bit) when the overflow instruction signal F2 is output. Output the signal F2
It has a function to output as is without performing shift processing when it is not being output. In this case, the output data constitutes the mantissa part of the output data D.

Next, referring to the exponent calculation circuit, 20 is the human data D
An adder 21 adds data Ea and Eb of the exponent parts of 1 and D2, and an adder 21 adds a predetermined negative bias -BS to the output data of the adder 20, that is, the temporary exponent (Ea + Eb). 22 is an incrementer that adds the data of "1" of the overflow instruction signal F1 to the output data of the adder 21, that is, the true exponent (Ea + Eb - BS), and 23 is an incrementer for overflow correction by rounding. 1" is added to the output data of the incrementer 22, and 24 represents a multiplexer that selects one of the outputs of the incrementers 22 and 23 in response to the overflow instruction signal P!. In this case, , the multiplexer 24 is
When the overflow instruction signal F2 is output, the output of the incrementer 23 is selected and the overflow instruction signal F2 is output.
When 2 is not output, the output of the incrementer 22 is selected. This selected data constitutes the exponent part of the output data D3.

The sign part arithmetic circuit is constituted by an exclusive OR gate 30, and the gate calculates the sign data S in response to the sign part data Sa and Sb of the input data D5 and D2, respectively.
Output N. Data SN of this code is human data D
When D3 and D2 both have the same sign, it becomes "0" to indicate "positive", and conversely, when they have different signs, it becomes "l" to indicate "negative". The data of this code is sent to the rounding control circuit 14 described above.
It also constitutes the code part of the output data D.

Next, division processing by the floating point arithmetic unit shown in FIG. 2 will be explained. Note that since the calculations for the exponent part and the sign part are the same as in the conventional type (see FIG. 3), only the calculations for the mantissa part will be explained here.

Among the floating point data formats of the IEEE standard, division of normalized numbers (C=A/B) will be considered. That is, C=A/B=A (1/B), where A, B, and C are all normalized numbers, then the (i+1)th approximation value X of the reciprocal function 1/B, *I is, Xi,, = Xi (2-BX,), where O<X, <2/B (Boo), 0>Xo
>2/B (B<O), It is expressed as follows.

Here, if the initial value X0 is set in the range of 0<X0≦1/B by a memory such as a look-up table (not shown), then Q<BXo≦11, . ■≦2-BX, <2, and 2-BX also becomes a normalized number. Therefore, -1 and 2-BX are also normalized numbers.

Next, consider the calculation of 2-BXi (0<BXi≦1). Since 0<BXi≦1, if the bit inversion of BX is ■7, then 2-BXi-IJ double, +LSB (1), however, L
SB(1) can be converted to mean LSB+1.

Specifically, first, with the exponent part calculation circuit and the sign part calculation circuit disabled, the data of the divisor B and the data of the initial value X0 of the reciprocal of the divisor are input data D0, Dt.
is applied to the multiplication circuit IO, and the division control signal Drν is set to the "H" level. Output BX of multiplier circuit lO,
is inputted to the pin 1 and inverting circuit 4I via the shifter 13, where each bit is inverted (TfY; ), further selected by the multiplexer 42, and inputted to the incrementer 15. The incrementer 15 responds to the division control signal DIV at the "H" level to
Add 1 to B. This added data (-BXl+
The LSB (1)), 2-BXi, is normalized through the shifter 16 and output as data D (step l)9.Then, the output data (2-BX,) is input together with the data of the initial value x0. The data D1 and D2 are applied to the multiplication circuit 10, and the division control signal 1) IV is “
The output X of the multiplier circuit 10, (2-BXo
) is further selected by the multiplexer 42 and input to the incrementer 15 via the shifter 13.

In this case, the incrementer 15 is the rounding control circuit 1
The rounding process is executed based on the control signal RC from 4.

Similarly, the output data of the incrementer 15 is the thick 16
The data is normalized through the process and output as data D3 (step 2).

Thereafter, the above steps 1 and 2 are repeatedly executed 3 to 4 times, and the resulting data Xi+l, that is, the (i+1)th approximate value data of 1/B, is combined with the dividend data A and the human data D1. It is applied to the multiplication circuit lO as 0□. At this time, the division control signal DIV is set to “L”.
level, and enables the exponent part calculation circuit and the sign part calculation circuit. As a result, the result based on the floating point division of A/B is output as data D.

In this way, the calculation of 2-BX, (0<BXi≦1) required for division using the Newton-Raphson method can be performed in l steps by adding 1 to the LSB of the bit inversion 1 and 1 of BX. It can be executed with

Therefore, when calculating the reciprocal of the divisor (1/B),
, =X, (2-BXi '') is the operation of 2-BX, and X for - times of iterative calculation.

It only takes two steps to calculate (2-BX,).

In other words, compared to the conventional type (three steps), the calculation for l steps can be omitted. Furthermore, since the iterative calculation is repeated three to four times, the overall processing time required for floating-point division is significantly reduced compared to the conventional method.

〔Effect of the invention〕

As explained above, according to the present invention, by simply improving the floating point multiplier, the 2-
Since the calculation of BX, (0<BXi≦1) can be performed in a relatively short time, it is possible to realize high-speed processing of floating point division, although it is a simpler method than the conventional method.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of a floating-point arithmetic unit according to the present invention, Fig. 2 is a block diagram showing the configuration of the main parts of a floating-point arithmetic unit as an embodiment of the present invention, and Fig. 3 is an example of a conventional type. 1 is a block diagram showing the configuration of a floating point arithmetic unit as shown in FIG. (Explanation of symbols) ■...Multiplication circuit, 2...Bit inversion circuit,
3...Selection circuit, 4...Addition circuit, A...
・Dividend, B...Divisor, S...Control signal, R...Rounding mode signal, Xo...Initial value of the reciprocal of the divisor, X,...I-th approximation of the reciprocal of the divisor. Diagram

Claims (1)

[Scope of Claims] A multiplication circuit (1) that multiplies two binary data in floating point notation by the mantissa part of the data, performs normalization processing, and outputs the result, and an output from the multiplication circuit. a bit inversion circuit (2) for inverting each bit of the data, and a circuit (3) for selecting either the output of the bit inversion circuit or the output of the multiplication circuit in response to a control signal (S); , When the output of the multiplication circuit is selected in the selection circuit, rounding processing is performed on the output in response to a predetermined rounding mode signal (R), and the output of the bit inversion circuit is selected in the selection circuit. and an adder circuit (4) that adds 1 to the least significant bit of the output in response to the control signal, performs normalization processing on each obtained value, and outputs the resulting value, based on a convergence method. 2-BX_i required when performing A/B floating point division, where 0<BX_i≦1 (i=0, 1,...), X_
o is the initial value of the reciprocal of the divisor; X_i is the i-th approximation of the reciprocal of the divisor. The calculation of X_i (2-BX_i) is performed by the multiplication circuit, and the data of X_i_+_1 obtained by repeating each calculation a predetermined number of times is applied to the multiplication circuit together with the dividend data A.
A floating point arithmetic unit characterized by performing division by /B.