JPH11120796A - Semiconductor storage device and method of testing semiconductor storage device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] During inspection using a technology for reducing the number of input / output terminals (I / O compression), an internal data pattern can be arbitrarily set, thereby reducing the I / O compression. Improve the flexibility of inspection. SOLUTION: A test pattern register TP for determining an internal data pattern is arranged inside a chip. EXOR
The circuits EXOR11 to EXOR14 are provided with test data input to the degenerated common input terminal Din and outputs TP1 to TP4 of the register TP.
Are compared with each other, and the comparison result is, as internal data,
Each is supplied to each storage element via write data buses WDB11 to WDB14. The EXOR circuits EXOR15 to EXOR18 compare the test result data of each storage element input via each of the read data buses RDB11 to RDB14 with the outputs TP1 to TP4 of the register TP, and the comparison result is sent to the NOR circuit NOR11. Given, it is determined whether each storage start element is normal or abnormal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor memory device and a method for inspecting a semiconductor memory device.

[0002]

2. Description of the Related Art There is a method of inspecting a semiconductor memory device by increasing the number of simultaneous measurements to reduce the inspection cost. However, with an increase in the number of bits in a semiconductor memory device in response to a request for an increase in the data transfer rate from a peripheral device, the number of simultaneously measured devices has to be reduced due to the limitation of an inspection device. Here, the number of simultaneous measurements is governed by the number of input / output terminals (I / O
Number), by reducing I / O during inspection,
A method of performing multi-bit operation inside and reducing the number of input / output pins with the outside is used.

FIG. 2 is a conceptual diagram of currently used I / O degeneration. In the figure, Din is a data input terminal to which test data is input, Dout is a data output terminal, WDB21 to WDB
The DB 24 is an internal write data bus that is shared at the time of inspection, and is connected to each memory cell. RDB21 ~ RDB24
Are internal read data buses which are shared at the time of inspection, and are respectively connected to the memory cells. EXOR21 is
An EXOR circuit to which the inspection result data from the read data buses RDB21 to RDB24 is input, the output of which is transmitted to the common output terminal Dout. In this circuit configuration, a plurality of write data buses WDB21 to WDB21 are connected to the data common input terminal Din.
Since the WDBs 24 are commonly connected, the inspection can be performed only when the input / output pattern of the internal data is all “0” or “1” in the entire memory cell.

[0004]

However, simply writing all "0" or "1" data to the memory cells causes a problem of lowering the degree of freedom of inspection. The degree of freedom mentioned here relates to a pattern of data to be read and written. As an inspection content, there is a method of screening for a defect related to interference between memory cells due to a difference in data topology between adjacent memory cells. However, in the current I / O compression method, there is a problem that sufficient inspection cannot be performed because the data topology can only input or output "1" or "0" for all bits. Or, if this I / O compression technology is used for inspection during wafer inspection, defects between memory cells must be inspected after packaging using a method that does not use I / O compression technology. It can be performed only by a small number of inspection methods. This leads to a decrease in inspection efficiency and a decrease in the yield of post-package inspection, which leads to an increase in inspection cost.

Further, in response to a recent demand for a rapid increase in the data transfer rate, the x16 word configuration has been replaced with the x32 word or x64 word.
Although the number of bits has been increased to word configuration, it is necessary to reduce the number of input / output terminals to the x4 word configuration and perform inspections, due to the problems of inspection cost and inspection equipment. When the number of input / output terminals is reduced to x4 word configuration for products, the size of the compression circuit is about 1.5 times larger than the method for compressing x16 word configuration products to x4 word configuration, and the chip size is reduced. A disadvantage arises that it becomes larger.

The present invention focuses on the above-mentioned problem, and an object of the present invention is to configure a semiconductor memory device so that reading and writing can be performed in an arbitrary data pattern inside a chip even when the number of input / output terminals is reduced. An object of the present invention is to make inspections related to interference possible.

Another object of the present invention is to provide a method of, for example, using I / O compression for an x32-word component, using an address not used in the x32-word component, and converting the x32-word component into an x16-word component during inspection. It is to operate like a product.

[0008]

In order to solve the above problems, the present invention is configured so that test data can be individually set to a plurality of write data buses connected to a data common input terminal. .

Further, the present invention employs a configuration in which a plurality of pieces of inspection result data to be read out are partly divided and read out in series from a data common output terminal.

That is, the semiconductor memory device according to the first aspect of the present invention is a semiconductor memory device which receives a test signal at the time of an internal inspection and is internally connected to a plurality of input terminals and internally connected to the common input terminal. A plurality of write data buses commonly connected to the semiconductor memory device, and capable of testing a plurality of storage elements via the plurality of write data buses by inputting test data to the common input terminal When inputting inspection data to the common input terminal,
An internal data pattern generating means for generating an internal data pattern for setting test data for each write data bus is provided.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the internal data pattern generating means includes a register for generating a predetermined pattern when test data is input to the common input terminal. And a generation circuit for generating an internal data pattern based on a predetermined pattern generated by the register and test data input to the common input terminal.

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, a plurality of read data buses connected to the plurality of storage elements and from which test result data is read, and each of the read data buses Correct / false judgment means for judging the correctness of each of the storage elements based on the result data of the above, and a test signal received at the time of an internal inspection, internally connected to a plurality of output terminals, and a correct / false judgment result of the right / false judgment means And a common output terminal for inspection.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, the correctness / incorrectness determining means determines whether the plurality of storage elements are all normal based on a predetermined pattern of the register. A conversion circuit for converting the result data of each read data bus to have the same value, and that all of the plurality of storage elements are normal or at least one of them is abnormal upon receiving the conversion result of the conversion circuit And a decision circuit for outputting a decision result to the common output terminal.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the second aspect, the generation circuit of the internal data pattern generation means includes a plurality of EXOR circuits respectively connected to the plurality of write data buses. It is characterized by the following.

According to a sixth aspect of the present invention, in the semiconductor memory device according to the second aspect, the generating circuit of the internal data pattern generating means includes an inverter between the common input terminal and the plurality of write data buses. A plurality of first paths connected via a common data input terminal and a plurality of second paths connected between the common input terminal and the plurality of write data buses without using an inverter. A switch circuit for switching between the first path and the second path is provided for each bus.

According to a seventh aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the conversion circuit of the right / wrong determining means includes a plurality of EXOR circuits respectively connected to the plurality of read data buses. Features.

According to an eighth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the conversion circuit of the right / wrong determining means includes an inverter between each of the plurality of read data buses and the common output terminal. Connected multiple first
A plurality of paths, a plurality of second paths connected between the plurality of read data buses and the common output terminal without using an inverter, and a first path for each of the read data buses. And a switch circuit for switching between the second path and the second path.

According to a ninth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the judgment circuit of the right / wrong judgment means comprises a NOR circuit.

According to a tenth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the internal data pattern input from the register to the generation circuit of the internal data pattern generation unit and the correctness / incorrectness determination unit based on the register. Is characterized by being complementary to the internal data pattern input to the conversion circuit.

The invention according to claim 11 is the invention according to claim 10.
In the semiconductor memory device described above, an inverting circuit capable of inverting the internal data pattern of the register is disposed on an input path of the internal data pattern from the register to the conversion circuit of the right / wrong determining means. And

The invention according to claim 12 is the invention according to claim 11.
In the semiconductor memory device described in the above, the inverting circuit, based on a value of test data input to the common input terminal,
The internal data pattern is inverted or not inverted.

According to a thirteenth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the judgment circuit of the right / wrong judgment means includes a NOR circuit, a NAND circuit connected in parallel to the NOR circuit, and the NOR circuit. The output of the circuit and the NA
A switch circuit for switching the output of the ND circuit based on the inspection data input to the common input terminal.

According to a fourteenth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the judgment circuit of the right / wrong judgment means comprises an EXOR circuit.

According to a fifteenth aspect of the present invention, in the semiconductor memory device according to the first aspect, the internal data pattern generating means includes an inverter arranged on a part of the plurality of write data buses. It is characterized by having.

The invention according to claim 16 is the invention according to claim 15.
5. The semiconductor memory device according to claim 2, wherein the plurality of read data buses are connected to the plurality of storage elements, and read test result data.
An inverter arranged on a part of the read data bus corresponding to the write data bus on which the inverter is arranged;
An EXOR circuit for receiving detection result data of a read data bus on which the inverter is disposed and a read data bus on which the inverter is not disposed, and a test signal received during an internal test, and commonly connected internally to a plurality of output terminals;
And a common output terminal for inspection for receiving the output of the EXOR circuit.

In the semiconductor memory device according to the present invention, when testing a plurality of storage elements provided therein, a plurality of read data buses from which test result data is read from the plurality of storage elements; Control means for receiving a common output terminal for inspection to which a bus is connected, and an address valid only at the time of the inspection, and controlling the number of read data buses connected to the common output terminal based on the received address And characterized in that:

[0027] The invention according to claim 18 is the invention according to claim 17.
3. The semiconductor memory device according to claim 1, wherein the control unit includes a switch circuit that receives an address that is valid only during the test and connects a part of the read data bus to the common output terminal.

According to a nineteenth aspect of the present invention, in the inspection method for a plurality of storage elements provided therein, the inspection result data is read from the plurality of storage elements to a plurality of read data buses, and the inspection is performed. A plurality of read data buses are sequentially connected to a common output terminal for inspection based on an address that is valid only when the data is read.

With the above arrangement, according to the first to sixteenth aspects of the present invention, even when one test data is input to the common input terminal at the time of testing the internal elements, a plurality of test data connected to the common input terminal can be obtained. The write data bus of
Since the internal data can be set individually, it is also possible to perform an inspection related to interference between adjacent cells (storage elements).

According to the seventeenth to nineteenth aspects of the present invention, the number of internal data can be halved from, for example, x32 to x16. You can use the same degenerate circuit as the product compressed to x4 word configuration. Therefore, it is possible to easily inspect the x32 word component in the x4 word configuration without increasing the chip size. In the present invention, x3
Since the two-word component is inspected as if there are two x16-word components, the inspection time is doubled compared to the case where the inspection method with reduced number of input / output terminals is not used, but the number of simultaneously measured items is 32. /
Since the number is increased by 4, that is, by 8/1, the inspection efficiency is increased by a factor of 4 as a whole.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor memory device according to a first embodiment of the present invention. In the figure, Din is a data common input terminal, Dout is a data common output terminal, and the data common input terminal Din receives a test signal (not shown) at the time of testing the internal storage element and internally receives a plurality of input terminals (not shown). Connected in common. Similarly, the data common output terminal Dout is internally connected to a plurality of output terminals (not shown) at the time of the inspection.

Also, WDB11 to WDB14 are plural (4 in the figure).
RDB11 to RDB14 are four read data buses. The write data buses WDB11 to WDB14
Are respectively connected to internal storage elements, and these storage elements are further connected to the respective read data buses RDB11 to RDB14. Therefore, each of the write data buses WDB11 to WDB14 and each of the read data buses RDB11 to RDB14 correspond one by one.

Further, reference numeral 1 denotes an internal data pattern generating means, which includes a test pattern register (register) TP;
EXOR circuits EXOR11 to EXOR14. The test pattern register TP has EXOR circuits EXOR11 to EXOR.
A test data pattern consisting of a combination of four data TP11 to TP14 corresponding to 14 is stored and output when an internal storage element is inspected. Each of the EXOR circuits EXOR11 to EXOR14
Receive the corresponding data in the test data pattern of the test pattern register TP, receive the input data to the data common input terminal Din in common, and generate internal data. To the corresponding write data buses WDB11 to WDB14. The four Es
The XOR circuits EXOR11 to EXOR14 constitute a generation circuit 2 for generating an internal data pattern composed of a combination of four internal data.

In addition, reference numeral 5 denotes a right / wrong judgment circuit, which has four EXOR circuits EXOR15 to EXOR18 and a NOR circuit (judgment circuit) NOR11. Each of the EXOR circuits EXOR15 to EXO
R18 receives the data on the four read data buses RDB11 to RDB14 and receives the corresponding data from the test data pattern of the test pattern register TP.
Therefore, the four EXOR circuits EXOR15 to EXOR18 constitute a conversion circuit 6 that converts all data on the read data buses RDB11 to RDB14 to the data value of the data input terminal Din. The NOR circuit NOR11 is connected to each of the EXOR circuits EXOR1.
5 to EXOR18, and the output is transmitted to the data common input terminal Din.

Next, a method of inspecting the internal storage element in the semiconductor memory device of FIG. 1 will be described.

First, when the value of the input data of the data common input terminal Din is "1", the output TP11 of the register TP,
Assuming that TP12, TP13, and TP14 are (0, 1, 0, 0) in this order, the values of the write data buses WDB11 to WDB14, which are the outputs of the EXOR circuits EXOR11 to EXOR14, are (0, 1, 0,
0). That is, the same pattern as the pattern of the outputs TP11 to TP14 of the register TP is written inside.

Next, the method of reading the written data to determine pass / fail (correct / false) is as follows. That is, the pattern of the register TP is normally (0, 1,
(0,0), read data bus RDB1
1 to RDB 14 are also sequentially read as (0, 1, 0, 0). When the values of the read data buses RDB11 to RDB14 are compared with the pattern (0, 1, 0, 0) of the register TP by the EXOR circuits EXOR15 to EXOR18, the result of the comparison is (0, 0, 0, 0). Becomes
Finally, the comparison result is input to the NOR circuit NOR11, so that in the case of pass (normal), the data common output terminal Dout
Will be output as "1". Conversely, if there is a defect and the value of the read read data bus RDB11 to RDB14 is not (0,1,0,0) but is, for example, (0,1,1,0), , EXOR circuits EXOR15 to EXOR18 have a comparison result of (0, 0, 1, 0), and the output of the NOR circuit NOR11 is "0".

As described above, when there is a defect inside, a difference from the output pattern of the register TP occurs when the inspection result data is read out.
By passing through the R circuit NOR11, it is possible to determine the presence of an internal defect in which a part of the storage element has failed.

Also, since the logic of the write data buses WDB11 to WDB14 can be inverted by the data topology "0" or "1" of the data common input terminal Din, it is necessary to prepare registers TP for all patterns. And the number of registers in the register TP can be reduced.

(Second Embodiment) FIG. 3 shows a semiconductor memory device having a configuration according to a second embodiment of the present invention.

In FIG. 3, an internal data generating circuit 2 '
Is a data common input terminal Din and four write data buses W
Four first paths 10 each having an inverter INV31 to INV34 inserted between DB11 to WDB14, and the inverter INV3
1 to 4 for switching between the four second paths 11 in which the INV 34 is not inserted and the corresponding first path 10 and second path 11
Switch circuits SW31 to SW34. Each of the switch circuits SW31 to SW34 is connected to the register TP shown in FIG.
The switching operation is performed in response to test data MRS31 to MRS34 forming a test data pattern from the same register (not shown).

Also, in FIG. 3, the conversion circuit 6 '
Write data buses RDB11 to RDB14 and NOR circuit NOR11
, Four first paths 15 in which the inverters INV35 to INV38 are inserted, four second paths 16 in which the inverters INV35 to INV38 are not inserted, and the corresponding first paths 15 and 15, respectively. It has four switch circuits SW35 to SW38 for switching between the two paths 16. Each of these switch circuits SW35 ~
The SW 38 performs a switching operation upon receiving test data MRS35 to MRS38 based on the test data pattern from the register (not shown) at the time of inspection.

Next, an inspection method according to the present embodiment will be described.

First, the case where patterns (0, 1, 0, 0) are sequentially written to the write data buses WDB11 to WDB14 will be described. Input data value of data common input terminal Din is Low
Set to “0”. Switch circuits SW31 to SW3 by register TP
4 to control the path without the inverter (second path 1
If 1) is “normal” and the path through the inverter (the first path 10) is “INV”, (normal, INV, norm
al, normal).

Next, the written pattern (0, 1, 0, 0)
The method of reading pass to determine pass / fail will be described. Read data bus by switch circuits SW35 to SW38
The first and second passes 11 and 12 of RDB11 to RDB14 are performed by (norma
l, INV, normal, normal). As a result, the read test result data of the read data buses RDB11 to RDB14 are all "0" when operating normally, and these values are input to the NOR circuit NOR11 and the data common output terminal Dout Outputs “1”. If there is a defect in something and the data cannot be written normally, the output of the NOR circuit NOR11 becomes "0", thereby making it possible to judge pass / fail.

Next, a case where the input data value of the data common input terminal Din is High “1” will be described. Assuming that the setting of the register TP is the same as when the input data value of the input terminal Din is Low “0”, the values of the internal write data buses WDB1 to WDB14 become (1, 0, 1, 1). Becomes When reading these, switch circuits SW35 to SW
The setting of 38 changes the input data value of the input terminal Din to Low “0”.
If "" is the same as "," the data pattern of the read data buses RDB11 to RDB14 is (1, 1, 1, 1). In this case, N
The output of the OR circuit NOR11 is the value of the data common output terminal Dout (that is, the NOR circuit) unless all four bits cause an error.
Since the output of NOR11 is “0”, the pass / fail determination cannot be performed well.

Therefore, the test data pattern of the register TP that controls the internal data pattern is inverted and input between the writing and the reading. As a result, when the input / output operation is performed normally, the output of the data common output terminal Dout becomes “1”. When the normal operation cannot be performed even with 1 bit, “0” is output. Pass / fail can be determined favorably.

(Third Embodiment) FIG. 4 shows an overall configuration of a semiconductor memory device according to a third embodiment of the present invention. This embodiment is different from the second embodiment in the method of pass / fail determination at the time of reading data.

That is, in the present embodiment, the register TP
And the switch circuits SW31 to SW34 of the internal data generating circuit 2 'are controlled by the test data MRS31 to MRS34 from the first and second, and an inverting circuit 30 for inverting the test data MRS31 to MRS34 is arranged. make use of,
It controls each of the switch circuits SW35 to SW38 of the conversion circuit 6 '.

The inverter 30 inverts the test data MRS31 to MRS34 from the register TP.
9 to INV52, four second paths 56 for propagating the test data MRS31 to MRS34 from the registers without inverting them, and two corresponding paths 55,
56, and four switch circuits SW49 to SW52. Each of the switch circuits SW49 to SW52 switches according to the data value “0” or “1” of the data common input terminal Din.

Therefore, in this embodiment, the data topology (“1”) input from the outside to the data common input terminal Din without the need for an external command at the time of inspection is provided.
Alternatively, by using a circuit for determining “0”), there is no need to externally execute an inspection method of switching the register between writing and reading.

(Fourth Embodiment) FIG. 5 shows a configuration of a fourth embodiment of the present invention. This embodiment is different from the second embodiment in that pass / fail at the time of reading data is performed.
The judgment method is different.

In this embodiment, the read data bus RDB1
The determination circuit 60 that determines whether the internal storage element is normal or abnormal in response to the test result data of the
R11, NAND circuit NAND61, and both circuits NOR11, NAND61
Is provided, and the output selected by the switch circuit SW59 is transmitted to the data common output terminal Dout. The switching of the switch circuit SW59 is controlled by the data value of the data common input terminal Din.

The inspection method according to the present embodiment will be described with an example.

The case where the input data value of the data common input terminal Din is "1" when reading the inspection result data will be described. When input / output can be executed normally, read data buses RDB11 to RDB14 at the time of reading are sequentially (1, 1, 1, 1).
, The pass is determined only when all bits are “1”.
The output of the D circuit NAND61 is selected, and the data common output terminal Do
When the output of ut is "1", it is pass, and when it is "0", it is fail.

Similarly, when the test data value "0" is input to the data common input terminal Din, the register setting is the same as when the input is "1", so that the read data buses RDB11 to RDB14 Are all "0" when input / output is performed normally. Pass only when this is all “0”
In this case, the output of the NOR circuit NOR51 is selected by the switch circuit SW59 for the data common output terminal Dout. The determination of pass / fail is the same as when the input data value of the data common input terminal Din is “1”. When the output of the data common output terminal Dout is “1”, the pass is determined. It is.

(Fifth Embodiment) FIG. 6 shows a configuration of a fifth embodiment of the present invention. This embodiment is different from the second embodiment in that pass / fail at the time of reading data is performed.
The judgment method is different.

That is, the present embodiment is different from the second embodiment in that an EXOR circuit EXOR71 is provided as a circuit for judging inspection result data in FIG.

Next, the operation of the present embodiment will be described with an example. The case where the input data value of the data common input terminal Din is “0” will be described.

At the time of writing, write data buses WDB11 to WDB
Assume that the registers are set so that patterns (0, 1, 0, 0) can be written in order to 14. Next, when reading this,
If the setting is normal, read data bus
Assuming that (0, 0, 0, 0) is sequentially read out to RDB11 to RDB14, the output of the EXOR circuit EXOR71 becomes "0" in the case of pass and "1" in the case of fail. Similarly, when the input data value of the data common input terminal Din is “1”, when the register setting is the same as when the input data value of the input terminal Din is “0”, the read data Bus RDB1
The output of 1 to RDB14 is (1,1,1,1) and the EXOR circuit
The output of EXOR71 is "0" for pass and "1" for fail. As a result, pass / fail can be determined. However, even if all 4 bits of data are inverted, a pass is determined in this method.

(Sixth Embodiment) FIG. 7 shows a configuration of a sixth embodiment of the present invention. In the present embodiment, as compared with the second embodiment, the number of internal data buses that are switched according to the presence or absence of an inverter is reduced, thereby simplifying the configuration and control, and checking the internal data pattern with all “0” s during inspection. Alternatively, a data pattern other than all "1" can be set.

That is, in FIG. 7, INV81 and INV82 are inverters inserted between the write data buses WDB11 and WDB13 and the data common input terminal Din, respectively. There are two systems, a path having a path and a path having no path. SW81, SW
A switch circuit 82 switches between the two paths in each of the write data buses WDB11 and WDB13. INV83, I
NV84 is a write data bus having the two paths, respectively.
Read data bus RDB11, RDB13 corresponding to WDB11, WDB13
And a data common output terminal Dout, and there are two systems, one for each of the read data buses RDB11 and RDB13, a path having this inverter and a path having no inverter.

Further, an EXOR circuit in which the read data buses RDB11 and RDB13 via the inverters INV83 and INV84 and the remaining read data buses RDB13 and RDB14 are connected.
An EXOR 81 and an EXOR circuit EXOR 82 to which only a system that does not pass through an inverter is input are provided. The switch circuit SW83 switches between the EXOR circuits EXOR81 and EXOR82, and the output selected by the switching is transmitted to the data common output terminal Dout.

Next, the inspection method of this embodiment will be described. All internal data patterns are "0" or "1"
Whether to use a topology pattern (TPL 0/1 pattern) or a checker pattern (CHK pattern) is set by a register (not shown) (register TP in FIG. 1).

First, the TPL 0/1 mode will be described.
With the register, the switch circuits SW81 to SW84 select a path that does not pass through the inverter. As a result, the data (“0” or “1”) input from the data common input terminal Din is
The data is transmitted to the write data buses WDB11 to WDB14 and written. During reading, the write data buses WDB11 to WDB
The data of DB14 is directly input to the EXOR circuit EXOR81, and the comparison result is output from the data common output terminal Dout via the switch circuit SW83.
In the case of l, it becomes "1".

Next, the input / output of the CHK pattern will be described. When the CHK mode is selected by the register, a path via the inverter is selected in the write data buses WDB11 and WDB13. As a result, the data common input terminal Di
If the input data value of n is “0”, the write data bus WD
The values of B11 to WDB14 are (1, 0, 1, 0) in order, with CH
K pattern can be written. A method of reading this data to determine pass / fail will be described below.

When the CHK mode is selected by the register, the read data buses RDB11 to RDB14 are sequentially set to (1, 0,
1, 0) is read, but the read data bus RDB11
In RDB13, the value is inverted by an inverter, and the result is transmitted to EXOR circuit EXOR82. Therefore, when there is no defect, all “0” s input to the data common input terminal Din are read out as they are. Also, even when the value of the input data of the data common input terminal Din is “1”, the values of the read data buses RDB11 and RDB13 are inverted by the inverter, and if normal, all “1”
become. As a result, the output of the EXOR circuit EXOR82 becomes
Is "0" in case of "1" and "1" in case of fail.

(Seventh Embodiment) FIG. 8 shows a semiconductor memory device according to a seventh embodiment of the present invention.

In the figure, Din is a data common input terminal, Dout is a data common output terminal, WDB10 to WDB17 are write data buses, and RDB10 to RDB17 are read data buses.
SW91 to SW94 are switch circuits (control means), which are switched by an address CA8 set to be valid only during the I / O degeneration test. Switch circuit S
W91 switches and selects one of the two read data buses RDB10 and RDB14, and the switch circuit SW2 switches between the two read data buses RDB10 and RDB14.
The switch circuit SW3 switches and selects one of the two read data buses RDB12 and RDB16, and the switch circuit SW4 switches and selects one of the two read data buses RDB13 and RDB17. . Accordingly, eight read data buses are provided by these four switch circuits SW91 to SW94.
RDB10 to RDB17 are four read data buses RDB10 to RDB13
Is switched to the other four read data buses RDB14 to RDB17. Outputs of the four read data buses selected by the switch circuits SW91 to SW94 are output to a comparison circuit (EX).
OR circuit) is input to EXOR91 and compared, and the comparison result is propagated to data common output terminal Dout.

Hereinafter, the operation of this embodiment will be described. At the time of writing the test data, the test data input from the data common input terminal Din is written through the write data buses WDB10 to WDB17 without using the address CA8.

At the time of reading the inspection result data, when the read data buses RDB10 to RDB17 are divided in half by the address CA8 and the switch circuits SW91 to SW94, for example, four read data buses RDB10 to RDB13 are selected. , And these outputs are input to an EXOR circuit EXOR91 and compared, and a correct / incorrect judgment signal as a result of the comparison is output to a data common output terminal Dout.

Therefore, in this embodiment, the number of test result data read at a time can be halved at the time of the test in which the number of input / output terminals is reduced. The same degenerate circuit can be used as if the word components were compressed to x4 word configuration. Therefore, x32 word components etc. can be easily converted to x4 without increasing the chip size.
It is possible to check by word composition.

[0074]

As described above, according to the first to sixteenth aspects of the present invention, when the number of input / output terminals is reduced, the write data buses commonly connected to the common input terminals are individually connected. Since you can set internal inspection data,
Data pattern can be simple all "1" or all "0"
In addition to this, it is possible to perform inspections with other complicated patterns, and to inspect semiconductor memory devices including inspections related to interference between adjacent storage elements without reducing the degree of freedom of the inspection pattern. This has the effect of being able to be implemented.

According to the seventeenth to nineteenth aspects of the present invention, when performing an inspection in which the number of input / output terminals is reduced,
Using a valid address only at the time of the inspection, a plurality of inspection result data are divided and read one by one, so especially for a semiconductor memory device having a word configuration such as x32 or x64, x1
Using a degeneration circuit of the same scale as a degeneration circuit that compresses a six-word component to an x4 word configuration, it is possible to perform a test in which the input / output terminals are degenerated.

[Brief description of the drawings]

FIG. 1 is a diagram showing a main part of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a conventional technique according to the present invention.

FIG. 3 is a diagram illustrating a main part of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 4 is a diagram illustrating a main part of a semiconductor memory device according to a third embodiment of the present invention;

FIG. 5 is a diagram illustrating a main part of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a main part of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing a main part of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 8 is a diagram showing a main part of a semiconductor memory device according to a seventh embodiment of the present invention.

[Explanation of symbols]

Din data common input terminal (common input terminal) Dout data common output terminal (common output terminal) 1 Internal data pattern generation means TP test pattern register (register) 2, 2 'generation circuit EXOR11 to EXOR14 EXOR circuit RDB11 to RDB14 Read data bus 5 Correct / error judgment circuit 6, 6 'conversion circuit NOR11 NOR circuit INV31 to INV34 Inverter 10, 15 First path 11, 16 Second path SW31 to SW34 Switch circuit EXOR15 to EXOR18 EXOR circuit SW35 to SW38, SW59 Switch circuit 30 Inversion Circuit NAND60 NAND circuit EXOR71, EXOR81 EXOR circuit INV81-INV84 Inverter SW91 Switch circuit (control means)

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masashi Agata 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (19)

[Claims] 1. A common input terminal for inspection which is internally connected to a plurality of input terminals in response to a test signal during an internal inspection, and a plurality of write data buses commonly connected to the common input terminal. A semiconductor memory device capable of inspecting a plurality of storage elements via the plurality of write data buses by inputting inspection data to the common input terminal, wherein the inspection data to the common input terminal is provided. And an internal data pattern generating means for generating an internal data pattern for setting test data for each write data bus at the time of input. 2. The internal data pattern generating means includes: a register for generating a predetermined pattern when test data is input to the common input terminal; a predetermined pattern generated by the register; and an input to the common input terminal. 2. The semiconductor memory device according to claim 1, further comprising: a generation circuit for generating an internal data pattern based on the test data obtained. 3. A plurality of read data buses which are connected to the plurality of storage elements and from which test result data is read, and whether the storage elements are correct or not based on the result data of the respective read data buses. Means for receiving a test signal at the time of internal inspection, and commonly connected to a plurality of output terminals internally, and a common output terminal for inspection for receiving the result of the right / wrong judgment of the right / wrong judgment means. The semiconductor memory device according to claim 2. 4. A method according to claim 1, wherein said correctness determination means converts the result data of each of said read data buses to have the same value when all of said plurality of storage elements are normal, based on a predetermined pattern of said register. A conversion circuit that receives the conversion result of the conversion circuit, determines that all of the plurality of storage elements are normal or at least one is abnormal, and outputs a determination result to the common output terminal. 4. The semiconductor memory device according to claim 3, comprising: 5. A generation circuit of said internal data pattern generation means, comprising: a plurality of E data lines respectively connected to said plurality of write data buses.
3. The semiconductor memory device according to claim 2, comprising an XOR circuit. 6. The generation circuit of the internal data pattern generation means, comprising: a plurality of first paths connected via an inverter between the common input terminal and the plurality of write data buses; A plurality of second paths connected between a terminal and the plurality of write data buses without using an inverter, and a switch between the first path and the second path for each of the write data buses 3. The semiconductor memory device according to claim 2, further comprising a switch circuit. 7. The conversion circuit of the right / wrong determining means includes a plurality of E data lines respectively connected to the plurality of read data buses.
5. The semiconductor memory device according to claim 4, comprising an XOR circuit. 8. A conversion circuit of said right / wrong determining means, comprising: a plurality of first paths connected between said plurality of read data buses and said common output terminal via respective inverters; A plurality of second paths connected to each other without an inverter between a bus and the common output terminal; and a switch circuit for switching between the first path and the second path for each of the read data buses. 5. The semiconductor memory device according to claim 4, comprising: 9. The judgment circuit of the right / wrong judgment means is NOR.
5. The semiconductor memory device according to claim 4, comprising a circuit. 10. The internal data pattern input from the register to the generation circuit of the internal data pattern generation means and the internal data pattern input from the register to the conversion circuit of the correctness determination means have a complementary relationship. 5. The semiconductor memory device according to claim 4, wherein: 11. An inverting circuit capable of inverting an internal data pattern of the register is provided on an input path of the internal data pattern from the register to the conversion circuit of the right / wrong judgment means. Claim 10
The semiconductor memory device according to claim 1. 12. The semiconductor memory device according to claim 11, wherein said inverting circuit inverts or does not invert an internal data pattern based on a value of test data input to said common input terminal. 13. A determination circuit of the right / wrong determination means, comprising: a NOR circuit; a NAND circuit connected in parallel to the NOR circuit; an output of the NOR circuit and an output of the NAND circuit;
5. The semiconductor memory device according to claim 4, further comprising: a switch circuit that switches based on test data input to said common input terminal. 14. A judgment circuit of the right / wrong judgment means, EX
5. The semiconductor memory device according to claim 4, comprising an OR circuit. 15. The semiconductor memory device according to claim 1, wherein said internal data pattern generating means includes an inverter arranged on a part of the plurality of write data buses. 16. A plurality of read data buses connected to the plurality of storage elements and from which test result data is read, and one of the plurality of read data buses corresponding to a write data bus on which the inverter is arranged. An inverter arranged on a read data bus of the unit, an EXOR circuit receiving detection result data of a read data bus on which the inverter is arranged and a read data bus on which the inverter is not arranged; 16. The semiconductor memory device according to claim 15, further comprising: a common output terminal for inspection which is internally connected in common to said output terminals and receives an output of said EXOR circuit. 17. A plurality of read data buses for reading test result data from the plurality of storage elements when testing a plurality of storage elements provided therein, and a common output for inspection to which each of the read data buses is connected. A semiconductor memory, comprising: a terminal; and a control unit that receives an address that is valid only at the time of the test, and controls the number of read data buses connected to the common output terminal based on the received address. apparatus. 18. The control unit according to claim 17, further comprising a switch circuit that receives an address that is valid only at the time of the test and connects a part of the read data bus to the common output terminal. 13. The semiconductor memory device according to claim 1. 19. When testing a plurality of storage elements provided therein, read out test result data from the plurality of storage elements to a plurality of read data buses, and based on an address that is valid only at the time of the test, A method for inspecting a semiconductor memory device, wherein a part of read data buses is sequentially connected to a common output terminal for inspection.