JPH11122103A - Frequency correction circuit - Google Patents

Abstract

(57) [Summary] The present invention relates to a frequency correction circuit for an oscillator,
In an electronic device, it is possible to obtain a high-precision operating frequency of the device regardless of the accuracy of the internal oscillator. SOLUTION: A frequency correction circuit for correcting the output frequency of a digital synthesizer 2 for generating a signal having a frequency in accordance with frequency data received in response to a data write instruction, using an output frequency of an internal oscillator 1 as an operating frequency. A means 3 for detecting a deviation between a reference frequency supplied from the outside and an output frequency of the oscillator 1, a means 4 for calculating a correction value corresponding to the detected deviation, a means 5 for outputting frequency data, A means 6 for adding and subtracting a correction value to and from the frequency data output by the means 5 and outputting corrected frequency data; and a means 7 for outputting a data write command to the digital synthesizer 2 and causing the corrected frequency data to be captured as frequency data.
And characterized in that:

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a frequency correction circuit for an oscillator. An electronic device has an oscillator that regulates the operating frequency inside the device, but it is desirable that the oscillator inside the device be one that is highly accurate and highly stable, and that does not need to correct the frequency deviation due to aging. It is.
Particularly, in recent years, the development of mobile communication has been remarkable, but in this mobile communication system, since a large number of base stations are arranged, from the viewpoint of maintenance-free, the oscillator in the base station needs to correct the frequency deviation due to aging. Nothing is desired.

[0002]

2. Description of the Related Art Conventionally, a highly stable crystal oscillator is used to obtain a high-precision frequency, and when high precision and high stability are required, a crystal is kept in a thermostat so as to eliminate the influence of a change in ambient temperature. The use of an oven-type crystal oscillator placed in an oven is performed. To obtain a frequency other than the crystal oscillation frequency, a phase comparator, a loop filter,
A PLL synthesizer using a CO (voltage controlled oscillator) is used.

[0003]

Even when a high-precision and high-stability crystal oscillator is used, a frequency shift due to aging is inevitable. Therefore, it is necessary to adjust the oscillation frequency once every predetermined period. Therefore, when a large number of similar devices are arranged like base stations in a mobile communication system, the amount of work required for maintenance is enormous.

In the case of the PLL synthesizer, it has been pointed out that a component of the comparison frequency is mixed into the output frequency, thereby deteriorating the purity of the output frequency. In addition, when the component of the comparison frequency is cut off for some reason, the output is reduced. Since the frequency is not guaranteed, this is a problem in applications where the possibility of breaking the component of the comparison frequency must be taken into account. Further, even in the case of a PLL synthesizer using a crystal oscillator having high frequency stability, the deviation of the oscillation frequency may exceed the standard, but such a case cannot be detected.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a frequency correction circuit for an electronic device, which can obtain a high-precision operating frequency of the device regardless of the accuracy of the internal oscillator.

[0006]

FIG. 1 is a block diagram showing the principle of the first to fourth aspects of the present invention.

According to the first aspect of the present invention, an internal oscillator 1 is provided.
A frequency correction circuit for correcting the output frequency of the digital synthesizer 2 for generating a signal having a frequency in accordance with the frequency data received in response to the data write command, with the output frequency of Deviation detecting means 3 for detecting a deviation between the frequency and the output frequency of the internal oscillator 1, correction value calculating means 4 for calculating a correction value according to the detected deviation value, and frequency data output means for outputting frequency data 5, a correction frequency data output means 6 for adding and subtracting a correction value to and from the frequency data output by the frequency data output means 5 to output correction frequency data, and a data write instruction to the digital synthesizer 2 to output the correction frequency data. And a write command output means 7 for taking in as frequency data.

That is, according to the first aspect of the present invention, when the deviation detecting means 3 detects a deviation between a reference frequency supplied from the outside and an output frequency of the internal oscillator 2, the correction value calculating means 4 outputs the correction value. A correction value according to the detected deviation value is calculated, and the correction frequency data output means 6 adds and subtracts the correction value to and from the frequency data output by the frequency data output means 5 to output the correction frequency data. Output means 7
Outputs a data write command to the digital synthesizer 2 to write the corrected frequency data.

As a result, the digital synthesizer 2
It is possible to output a frequency signal of the same accuracy as the reference frequency supplied from outside regardless of the accuracy of the internal oscillator 1. According to a second aspect of the present invention, in the frequency correction circuit according to the first aspect, the detection means for detecting whether or not the signal of the reference frequency is supplied, and the digital synthesizer when the detection means detects the absence of the supply. And a holding command output means 9 for outputting a holding command for holding and outputting a signal of a frequency generated by a data write command immediately before detection.

In other words, according to the second aspect of the present invention, when the detecting means 8 detects that the reference frequency signal is not supplied, the holding instruction output means 9 sends the digital synthesizer 2 a data write instruction immediately before the detection. The signal of the generated frequency is held and output. As a result, when the supply of the reference frequency is interrupted for some reason, the digital synthesizer 2 can continuously output the frequency output with the corrected frequency data immediately before the interruption.

According to a third aspect of the present invention, in the frequency correction circuit according to the first or second aspect, an alarm means 10 for outputting an alarm when a deviation value or a correction value exceeds a threshold value is provided. Features. That is, according to the third aspect of the present invention, when the deviation value or the correction value exceeds the threshold value, the alarm means 10 detects this and notifies the outside.

According to a fourth aspect of the present invention, in the frequency correction circuit according to any one of the first to third aspects, the frequency data output means 5 is storage means for setting frequency data for generating various frequencies. It is characterized by. That is, according to the fourth aspect of the present invention, the digital synthesizer 2
Generates various frequencies with the accuracy of the reference frequency. If the operating frequency in the device is a small number such as one or two, the frequency data output means 5 may be a frequency setting device which can be constituted by a switch, a simple logic circuit or the like.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a configuration diagram of an embodiment corresponding to claims 1 to 4. In FIG. 2, the frequency correction circuit of this embodiment includes a GPS receiver 21, an internal oscillator 22, a counter 23, a memory 24, an adder / subtractor 2
5, a digital synthesizer 26, a central processing unit (hereinafter, referred to as “CPU”) 27, and the like.

The GPS receiver 21 is a GPS (Global Posi
reception system), demodulates time information, and
The second pulse (a) is extracted and given to one input of the counter 23. This one-second pulse (a) corresponds to the “reference frequency supplied from the outside”. In addition, the GPS receiver 21
Has an intensity meter for measuring the received electric field intensity, and provides the CPU 27 with the received electric field intensity value (b) measured for the GPS radio wave. This received electric field strength value (b) is a signal for detecting whether or not the “reference frequency supplied from the outside” is supplied.

The output of the internal oscillator 22 is provided to the other input of the counter 23 and a digital synthesizer 26. The counter 23 counts the oscillating frequency of the internal oscillator 22 using the one-second pulse (a) as a gate signal, and supplies the counting result (c) to the CPU 27. That is, the counter 23 operates as a comparator that determines the deviation of the oscillation frequency of the internal oscillator 22 from the reference frequency supplied from the outside.

The CPU 27 monitors the electric field intensity value (b) received from the GPS receiver 21 and, if it is equal to or more than a predetermined value, based on the counting result (c) of the counter 23, one of the adders / subtractors 25. Find the adjustment value (e) given to the input of
The contents of the frequency data transmission command (d) given to the memory 24 are determined, and the writing command (g) is output to the digital synthesizer 26.

The CPU 27 outputs an alarm when the add / sub value (e) output to the adder / subtractor 25 is larger than a threshold value (expected add / sub value). Further, the CPU 27
The received electric field intensity value (b) from the receiver 21 is monitored, and if it becomes equal to or less than a predetermined value, a holding instruction (h) is output to the digital synthesizer 26. In the memory 24, data of various frequencies to be generated by the digital synthesizer 26 is set. The memory 24 supplies frequency data according to the frequency data transmission command (d) from the CPU 27 to the other input of the adder / subtractor 25. The adder / subtractor 25 generates correction frequency data (f) based on the frequency data from the memory 24 and the addition / subtraction value (e) from the CPU 27, and outputs it to the digital synthesizer 26.

The digital synthesizer 26 has a DDS (D
IC marketed as irect Digital Synthesizer)
It is. Hereinafter, the digital synthesizer 26
26, a predetermined frequency signal is generated as follows. The DDS 26 internally has a phase angle database capable of outputting sine waves of various frequencies, and fetches uncorrected data set from outside in accordance with a write command from the CPU 27, and outputs the oscillation frequency of the internal oscillator 22. Is used as the operating frequency, phase angle data for generating the specified frequency is extracted from the database, and the specified frequency is output.

In the illustrated example, the DDS 26 is an adder / subtracter 25
The correction frequency data (f) is read in according to the write command (g) from the CPU 27. Also,
When the holding command (h) is input from the CPU 27, the DDS 26 holds and outputs the frequency immediately before the input of the holding command (h). The correspondence between the above configuration and the claims is as follows. The internal oscillator 1 corresponds to the internal oscillator 22. The DDS 26 corresponds to the digital synthesizer 2. The deviation detecting means 3 includes a counter 23 and a CPU.
27 correspond to the whole. The correction value calculation means 4 includes a CPU
27 corresponds. The memory 24 corresponds to the frequency data output means 5. The addition / subtraction unit 25 and the entire CPU 27 correspond to the correction frequency data output means 6. Detecting means 8
Corresponds to the entirety of the GPS receiver 21 and the CPU 27. The CPU 27 corresponds to the write command output means 7, the hold command output means 9, and the alarm means 10.

Next, FIG. 3 is an operation flowchart of an embodiment according to the first to fourth aspects of the present invention. Hereinafter, the operation of this embodiment will be described with reference to FIG. In FIG. 3, at S1, when the power is turned on, the CPU 27
The initialization processing of the frequency correction circuit is performed. That is, CPU
27 outputs, to the memory 24, a frequency data transmission command (d) for outputting frequency data for generating a frequency when there is no deviation. Further, the CPU 27 outputs to the adder / subtractor 25 an addition / subtraction value (e) in which the operation value a = 0.

As a result, frequency data for generating a frequency when there is no deviation with respect to the DDS 26 is output from the adder / subtractor 25, so that the CPU 27 causes the DDS 26 to take in the output (correction frequency data) of the adder / subtractor 25. When the command (g) is output, a signal of a certain frequency is output from the DDS 26. On the other hand, when the power is turned on, the GPS receiver 21 starts the operation of receiving the GPS radio wave, gives the measured received electric field intensity value (b) to the CPU 27, and outputs the extracted one-second pulse (a) to the counter 23. Give to. The counter 23 performs an operation of counting the oscillation frequency of the internal oscillator 22 using the one-second pulse (A) as a gate signal, and starts an operation of outputting the count value to the CPU 27.

In step S2, the CPU 27 compares the input received electric field strength (b) with a threshold value to determine whether the received electric field strength (b) is an appropriate value. Is a proper value, the one-second pulse (a) is correctly input with a regular amplitude. That is, this is a case where the reference frequency is smoothly supplied from the outside. In this case, the CPU 27 performs the processing of S3, S4 or S5, S6.

In S3, the CPU 27 determines whether the count value of the counter 23 is smaller than an expected value. This expected value is a predetermined value by which it can be determined that the internal oscillator 21 is generating a correct frequency without deviation. For example, if the correct oscillation frequency of the internal oscillator 21 is 10 MHz,
When gated and counted with a second pulse, it is 10 ⁷ times. The value of 10 ⁷ times is the expected value. This is an expected value in the sense that it is expected that the value of 10 ⁷ times can be obtained, and is set in advance.

The CPU 27 determines that the count result of the counter 23 is
If (10 ⁷ -1) times, the count value of the counter 23 is smaller than the expected value.
Correction is made to increase the output frequency of the operating DDS 26 based on the oscillation frequency of the internal oscillator 22 that has shifted to the lower side, and the process proceeds to S7. That is, in S4, since the deviation of the internal oscillator 22 is (1/10 ⁷ ) in the above example, the CPU 27 sets the output frequency of the DDS 26 to (1/1).
0 ⁷ ), an add / sub value (e) is calculated, output to the adder / subtractor 25, outputs a frequency data transmission instruction (d) to the memory 24, and gives a write instruction (g) to the DDS 26. .

As a result, the adder / subtractor 25 generates corrected frequency data (f) by adding the addition / subtraction value (e) to the frequency data output from the memory 24 and outputs the corrected frequency data (f) to the DDS 26.
At this time, the DDS 26 operates at the oscillation frequency of the internal oscillator 22 shifted to the lower side by (1/10 ⁷ ), but receives the write command (G) from the CPU 27 and changes the output frequency to (1). / 10 ⁷ ), and a signal of a correct frequency with a shift correction increased.

In short, in S4, the CPU 27 determines the frequency deviation from the difference between the expected value determined in relation to the oscillation frequency of the internal oscillator 21 and the count value of the counter 23, and adds (+ a) based on the frequency deviation. ) Is calculated and output to the adder / subtractor 25, frequency data defining the phase and amplitude corresponding to the frequency deviation obtained from the memory 24 is output, and a write command (g) is sent to the DDS 26.
, And a frequency shift correction for shifting a frequency shifted to a lower one to a higher one is performed.

On the other hand, in S5, the CPU 27 determines whether or not the count value of the counter 23 is larger than an expected value. In the previous example, the count result of the counter 23 is (1
If 0 ⁷ +1), since the count value of the counter 23 is larger than the expected value, the CPU 27 executes a subtraction process in S6, and operates based on the oscillation frequency of the internal oscillator 22 shifted to the higher side. Correction to lower the output frequency of the existing DDS 26 is performed, and the process proceeds to S7.

That is, in S6, in the above example, the deviation of the internal oscillator 22 is (1/10 ⁷ ).
7 calculates an addition / subtraction value (e) to lower the output frequency of the DDS 26 by (1/10 ⁷ ), outputs it to the adder / subtractor 25, and outputs a frequency data transmission command (d) to the memory 24. Further, it outputs a write command (g) to the DDS 26.

As a result, the adder / subtractor 25 generates corrected frequency data (f) by subtracting the addition / subtraction value (e) from the frequency data output from the memory 24, and outputs the corrected frequency data (f) to the DDS 26.
At this time, the DDS 26 operates at the oscillation frequency of the internal oscillator 22 shifted to the higher side by (1/10 ⁷ ).
A signal of a correct frequency corrected by a shift that is reduced by 10 ⁷ ) is output.

In short, in S6, the CPU 27 obtains a frequency deviation from the difference between the count value of the counter 23 and the expected value, calculates an (-a) subtraction value (e) based on the frequency deviation, and calculates the subtraction value (e). Output to memory 2
4 to output frequency data defining the phase and amplitude according to the deviation, and also gives a write command (g) to the DDS 26 to correct the frequency shift that shifts the higher shifted frequency to the lower one.

If the count value of the counter 23 is equal to the expected value in the comparison processing in S3 and S5, the CPU 27 directly proceeds to S3 without performing the correction processing in S4 and S6.
Proceed to 7. In S7, the CPU 27 determines whether the adjustment value calculated based on the count value of the counter 23 is larger than the expected adjustment value. Normally, since the adjustment value calculated based on the count value of the counter 23 does not become larger than the expected adjustment value, the CPU 27 returns to S2 and confirms that the received electric field strength (b) is an appropriate value. The correction process described above is repeatedly executed.

According to the above corrective measures, even if the oscillation frequency of the internal oscillator 22 is shifted, the DDS 26 is not affected by the shift, and the DDS 26 is a reference frequency 1 provided from the outside.
A signal with a frequency determined by the accuracy of the second pulse is output. Then, when the process returns to S2 in the course of the above corrective measures and checks the received electric field strength (b), if the received electric field strength is not an appropriate value,
The PU 27 does not perform the correction processing (S3 to S7), and waits for the received electric field strength (b) to recover to an appropriate value. At this time, when the CPU 27 determines that the received electric field strength (b) is not an appropriate value, it immediately stops outputting to the memory 24 and the adder / subtractor 25 and outputs a holding instruction (h) to the DDS 26. As a result, the DDS 26 maintains the output operation based on the correction frequency data output immediately before by the adder / subtracter 25.

When a GPS radio wave is received as a reference signal, such a measure is necessary because it is not always possible to receive the signal in a good state. Of course, when the receiving state is restored, the above-described correction operation is automatically restarted.
Considering the aging of the internal oscillator 22, etc., S
In 7, it is possible that the adjustment value calculated based on the count value of the counter 23 becomes larger than the expected adjustment value. In this case, the CPU 27 drives an alarm lamp, a buzzer, or the like provided on the operation panel to issue an alarm to the outside (S8), and notifies a maintenance person or the like. This makes it possible to take appropriate measures promptly.

It should be noted that the GPS receiver 21 in this embodiment is assumed to be a device in which it is difficult to receive a reference signal from another device, for example, an isolated device such as a base station in a mobile communication system. It is. When the reference signal can be obtained from another device, the circuit configuration is simplified. Although the counter 23 serving as a comparator directly compares the reference signal (1 second pulse) with the output frequency of the internal oscillator 22, the counter 23 may compare the output frequency of the internal oscillator 22 with the divided frequency. The adder / subtractor 25
Although the individual components are used, the addition / subtraction process may be executed in a series of calculation processes performed by the CPU 27.

Although the memory 24 is provided in consideration of the DDS 26 being capable of generating a plurality of types of frequencies, in applications where it is sufficient to generate fixed or a small number of frequencies,
Instead of the memory 24, a frequency setting device using a switch, a simple logic circuit, or the like can be provided. Further, the alarm may be generated when the count value of the counter 23 exceeds the expected count value.

[0036]

As described above, according to the first aspect of the present invention, a correction value corresponding to the deviation between the reference frequency supplied from the outside and the output frequency of the oscillator in the device is calculated and corrected to the frequency data. Correction frequency data is obtained by adding and subtracting the values, and the correction frequency data is written into a digital synthesizer, and a signal having a frequency determined by the correction frequency data is output.

Therefore, the digital synthesizer is
It is possible to output a frequency signal with the same accuracy as the reference frequency supplied from outside regardless of the accuracy of the oscillator in the device. Also,
Since the digital synthesizer is used, the correction speed is increased. According to the second aspect of the present invention, when the supply of the signal of the reference frequency is cut off, the digital synthesizer can continuously output the frequency output with the correction frequency data immediately before the cutoff.

According to the third aspect of the present invention, when the deviation of the oscillator in the device exceeds the expected deviation, the deviation can be detected and notified to the outside. According to the invention described in claim 4, various frequencies can be generated with the accuracy of the reference frequency. In particular, since a digital synthesizer is used, PL
There is no restriction that it can be generated only at the interval of the comparison frequency as in the L synthesizer, and any frequency can be generated at any interval.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the invention described in claims 1 to 4;

FIG. 2 is a configuration diagram of an embodiment corresponding to claims 1 to 4;

FIG. 3 is an operation flowchart of the embodiment corresponding to claims 1 to 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Internal oscillator 2 Digital synthesizer 3 Deviation detection means 4 Correction value calculation means 5 Frequency data output means 6 Correction frequency data output means 7 Write command output means 8 Detecting means 9 Holding command output means 10 Alarm means 21 GPS receiver 22 Internal oscillator 23 Counter 24 Memory 25 Adder / Subtracter 26 Digital Synthesizer 27 CPU

Claims (4)

[Claims] 1. A frequency correction circuit for correcting an output frequency of a digital synthesizer that generates a signal having a frequency in accordance with frequency data received in response to a data write instruction by using an output frequency of an internal oscillator as an operating frequency. A deviation detecting means for detecting a deviation between a reference frequency supplied from the outside and an output frequency of the oscillator in the device; a correction value calculating means for calculating a correction value according to the detected deviation value; and frequency data. Frequency data output means for outputting, correction frequency data output means for adding and subtracting the correction value to and from the frequency data output by the frequency data output means to output corrected frequency data, and outputting the data write command to the digital synthesizer And write command output means for taking in the corrected frequency data as the frequency data. Frequency correction circuit which is characterized. 2. The frequency correction circuit according to claim 1, wherein: a detecting means for detecting whether or not the signal of the reference frequency is supplied; and when the detecting means detects a non-supply, the digital synthesizer transmits the signal immediately before the detection. And a holding command output means for outputting a holding command for holding and outputting a signal of a frequency generated by the data write command. 3. The frequency correction circuit according to claim 1, further comprising: an alarm unit that outputs an alarm when the deviation value or the correction value exceeds a threshold value. 4. The frequency correction circuit according to claim 1, wherein said frequency data output means is storage means for setting frequency data for generating various frequencies. .