JPH11135692A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit in which a Peltier element is arranged, so as to effectively radiate Joule heat generated from a semiconductor chip with the Peltier element built-in in a package. SOLUTION: MOS transistors 12a, 12b and wiring metal 16a are formed on a semiconductor substrate 11 and covered with insulating films 14a, 14b. A Peltier element 15 is arranged on the insulating films 14a, 14b or in an etched part on the lower surface of the semiconductor substrate 11, and packaged with resin or ceramic, thereby forming an integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to integrated circuits,
In particular, the present invention relates to an integrated circuit having a Peltier element in a package and capable of efficiently cooling a semiconductor device.

[0002]

2. Description of the Related Art A conventional integrated circuit has been used by encapsulating a semiconductor circuit chip in which a plurality of electronic elements are embedded in a package made of plastic or ceramic, which is an insulator, in order to protect it from external static electricity and the like. Was.

Most of the power consumed by integrated circuits is
Released to the outside as Joule heat. Conventionally, semiconductor chips have been cooled by natural heat dissipation, or by adding a heat sink made of a material having high thermal conductivity on an insulating package, attaching a cooling fan, or adding a Peltier element. Was.

[0004] In recent years, the power consumption of integrated circuits has been reduced as the degree of integration of integrated circuits has increased, but the power consumption per unit chip area has not changed significantly. In particular, in a central processing circuit used in a computer or the like, an increase in resistance due to a high clock speed for high-speed operation, an increase in heat generation due to an increase in the number of transistors, an increase in heat generation from wiring due to multi-layer wiring, an increase in chip area. The heat dissipation is deteriorated due to the decrease of the heat dissipation area accompanying the decrease.

Therefore, if the chip is not cooled,
The chip temperature rises, causing problems such as thermal runaway of the circuit. Such a tendency of thermal runaway is remarkable in a central processing circuit used in a personal computer or a work station with a high clock number.

In order to improve the cooling efficiency of an integrated circuit, an integrated circuit having a cooling function built in a package has been proposed. For example, an integrated circuit in which a temperature control circuit including a Peltier element and a temperature measuring element for controlling the Peltier element are all incorporated in a package (Japanese Patent Application Laid-Open No. 1-258449),
There is an integrated circuit in which a Peltier element is monolithically formed on the back surface of a semiconductor substrate (Japanese Patent Application Laid-Open No. 9-64255).

In a conventional integrated circuit having the above structure, in the case of an integrated circuit in which a Peltier element and a temperature control circuit are all incorporated in a package (Japanese Patent Laid-Open No. 1-258449), the temperature of the chip itself is measured without passing through the package. Further, it is characterized in that the cooling is actively performed by the Peltier element without using a passive method by heat conduction.

An integrated circuit in which a Peltier element is monolithically formed on the back surface of a semiconductor substrate (Japanese Patent Laid-Open No. 9-6425)
In 5), the power consumption of the Peltier device can be suppressed by selectively providing the Peltier device in a portion generating a large amount of heat.

[0009]

However, among the above-mentioned conventional integrated circuits, chip cooling means (heat sinks, cooling fans and Peltier elements) are provided outside the package.
However, there is a problem that sufficient cooling efficiency cannot be obtained because the package, which is an insulator, has low thermal conductivity.

When a Peltier element is mounted outside the package, the thermal conductivity of the package becomes a rate-determining factor for heat dissipation, and the power consumption of the Peltier element must be increased in order to obtain a cooling efficiency that compensates for this. There is also a problem.

Even in the case of an integrated circuit in which a Peltier element is incorporated in a package, in the case of a configuration in which a chip to be cooled is mounted on a heat absorbing plate of the Peltier element, as shown in Japanese Patent Application Laid-Open No. 1-258449, Since the power consumption is large, there is a problem that the power consumption increases when a large Peltier element is used according to the size of the chip to be cooled.

Also, when the Peltier element and the integrated circuit are sealed in the same package, a part of the cooling surface of the Peltier element is usually exposed from the package, resulting in dew condensation around the integrated circuit. May be destroyed.

[0013] In recent years, as the number of wiring metal layers increases with the increase in the number of layers of integrated circuits, the heat generated from wiring lines cannot be ignored. When a Peltier device is monolithically formed on the back surface of a semiconductor substrate as disclosed in Japanese Patent Application Laid-Open No. 9-64255, when an integrated circuit is to be laminated, a heat sink attached to the Peltier device comes into contact with a wiring metal, and It is difficult to apply it to multilayer circuits.

The present invention has been made in view of the above problems, and accordingly, the present invention provides an integrated circuit having a Peltier element in a package and capable of efficiently cooling a semiconductor device. The purpose is to do.

[0015]

In order to achieve the above object, an integrated circuit according to the present invention is an integrated circuit having a package formed of an insulator, wherein the integrated circuit has an upper part covered with the insulator. A Peltier element is integrally formed on the insulator.

Thus, the integrated circuit is actively cooled by utilizing the Peltier effect (a phenomenon in which cooling occurs on one side of the Peltier element when a current flows) without using a passive method such as heat conduction. Can be. Since the Peltier element is arranged on the insulator, the Peltier element is selectively provided on the upper surface of the heat generating portion of the integrated circuit, whereby power consumption can be suppressed and high cooling efficiency can be obtained.

The integrated circuit according to the present invention is preferably characterized in that a heat radiating means is provided in a package of the integrated circuit. Thereby, the heat radiation effect outside the package is added to the cooling effect of the Peltier element provided in the package, and the cooling efficiency of the integrated circuit is improved.

An integrated circuit according to the present invention is an integrated circuit having a package formed of an insulator, wherein a Peltier element is integrally formed below the semiconductor substrate of the integrated circuit.

As a result, the Peltier element is embedded in the semiconductor substrate, and the cooling surface of the Peltier element is not exposed. Therefore, the dew condensation caused by exposing the cooling surface of the Peltier element is eliminated, and the destruction of the peripheral circuit due to the dew condensation can be avoided.

The integrated circuit according to the present invention is preferably characterized in that a heat radiating means is provided in a package of the integrated circuit. Even when the Peltier element is embedded in the lower surface of the semiconductor substrate, the cooling efficiency of the integrated circuit is improved by providing a heat radiating means such as a heat sink or a heat radiating fan outside the package.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the integrated circuit of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view of an integrated circuit according to an embodiment of the present invention. In the semiconductor substrate 11,
MOS transistors 12a and 12b are formed,
An element isolation insulator 13a is provided between the transistors 12a and 12b, and an element isolation insulator 13b is provided as necessary.

Semiconductor substrate 11 and MOS transistor 1
On the upper surfaces of 2a and 12b, insulators 14a and 14b are deposited, and a metal wiring layer 16a is formed between the insulators. The Peltier element 15 and the metal wiring layer 16b are formed on the insulator 14b.

2 (a) to 2 (c) and 3 (a),
FIG. 2B is a cross-sectional view illustrating a manufacturing step of the integrated circuit according to the first embodiment illustrated in FIG. 1. First, as shown in FIG.
Element isolation insulators 13a and 13b are provided on a semiconductor substrate 11.
For example, a selective oxidation method (Locos method; local o method).
xidation of silicon.

By the selective oxidation method, an SiO ₂ layer is formed as an insulator for element isolation. Element isolation insulator 13
The distance between a and 13b can be about several μm,
A transistor is formed in that part.

In order to form the insulator for element isolation by the selective oxidation method, first, a Si semiconductor substrate is heated in oxygen or water vapor, and a SiO ₂ film having a thickness of about 0.1 to 0.5 μm is formed on the surface. To form

[0027] In an Si ₃ N ₄ film on the SiO ₂ film, a SiO ₂ film and Si ₃ N ₄ by lithography
When an opening is provided in a specific region of the film and heat treatment is performed in an oxygen atmosphere, only the opening is oxidized deeply (about 1 μm). After that, when only the Si ₃ N ₄ film is removed, the insulating portions 13a and 13b for element isolation are formed.

Next, as shown in FIG. 2B, MOS transistors 12a and 12b are formed on the semiconductor substrate 11 in regions separated by the element isolation insulators 13a and 13b. Impurities are introduced into the semiconductor substrate 11 by an ion implantation method, a vapor diffusion
The source region 17 and the drain region 18 of a and 12b are respectively formed.

For example, the surface of the Si semiconductor substrate is oxidized to form an SiO ₂ film having a thickness of about 100 nm, and then the Si region at the position where the source region 17 and the drain region 18 are formed is formed.
An opening is formed by etching the O ₂ film. A source region 17 and a drain region 18 are formed by diffusing a donor from the opening to form an n ⁺ region.

By depositing a metal on the SiO ₂ film in the channel portion and using the metal as the gate electrode 19, MOS transistors 12a and 12b can be formed on the surface of the semiconductor substrate. As the metal to be deposited, a silicide (MoSi ₂ , TaSi ₂ ) such as molybdenum or tantalum can be used in addition to an aluminum-based alloy.

In a MOS transistor, the gate electrode 19
Is insulated from the source region 17 and the drain region 18 by an insulator, so that the input resistance is almost infinite. Further, since the transistor is insulated from the substrate, a small transistor element is formed on a two-dimensional plane. Easy to form.

Subsequently, as shown in FIG.
An insulator 14a is formed to cover the wiring from the electrodes attached to the transistors 12a and 12b. Insulator 14
The metal wiring 16a is formed so as to be embedded in a.

As shown in FIG. 3A, an insulator 14b is further formed on the insulator 14a and the metal wiring 16a. The insulator 14b is usually formed of the same material as the insulator 14a.

The electric circuits formed on the semiconductor chip and the Peltier element 15 formed on the upper layer are electrically insulated by the insulators 14a and 14b. Insulators have low thermal conductivity, so they do not interfere with heat dissipation from the semiconductor chip.
It is formed thinly on the order of nanometers or micrometer.

As shown in FIG. 3B, a Peltier element 15 is arranged above the insulator 14b. Insulator 14
MOS transistors 12a and 12b via a and 14b
Is the cooling side of the Peltier element 15. Further, by providing the metal wiring 16b on the upper layer, the configuration of the integrated circuit of this embodiment as shown in FIG. 1 is obtained.

Since the metal wiring layer 16b is formed on the heat radiation side of the Peltier element 15, the portion of the metal wiring layer 16b that generates a large amount of heat should be kept away from the Peltier element 15 as much as possible. Finally, the integrated circuit in which the Peltier element is integrally formed is packaged using a resin such as plastic or ceramic.

According to the integrated circuit of this embodiment, since the cooling side of the Peltier element is in contact with the heat-generating portion of the transistor element only through the thin insulator, the heat generation of the integrated circuit can be efficiently suppressed.

(Embodiment 2) FIG. 4 shows Embodiment 1 of FIG.
A top view (a) and a side view (b) of Embodiment 2 in which a heat sink 23 is further added to the integrated circuit of FIG.

In order to further improve the heat dissipation of the integrated circuit 21 by a passive method based on heat conduction, a heat sink 23 is provided outside the package 22. The heat sink 23 is arranged in a portion where the Peltier element is built in the package. The wiring metal for the integrated circuit 21 is stored in the wire frame 24.

Since the heat sink 23 needs to quickly radiate heat from the Peltier element while maintaining insulation between the electrodes, the heat sink 23 is formed using, for example, an insulator having high thermal conductivity such as alumina.

The heat sink 23 can be formed by applying a heat sink plating layer to the surface of the package 22 in addition to attaching a component formed separately from the integrated circuit 21. In this case, heat is radiated from the plating layer.

(Embodiment 3) FIG. 5 shows Embodiment 1 of FIG.
A top view (a) and a side view (b) of a third embodiment in which a heat dissipation fan 33 is further added to the integrated circuit of FIG.

In order to further improve the heat radiation of the integrated circuit 31 as compared with the case where the heat is naturally radiated, the package 32 is used.
A heat dissipation fan 33 is provided outside. The heat-dissipating fan 33 is disposed in a portion where the Peltier element is built in the package. The wiring metal for the integrated circuit 31 is stored in the wire frame 34.

(Embodiment 4) FIG. 6 is a sectional view of an integrated circuit representing an embodiment of the present invention. In the semiconductor substrate 11,
MOS transistors 12a and 12b are formed,
An element isolation insulator 13a is provided between the transistors 12a and 12b, and an element isolation insulator 13b is provided as necessary.

Semiconductor substrate 11 and MOS transistor 1
On the upper surfaces of 2a and 12b, insulators 14a and 14b are deposited, and a metal wiring layer 16a is formed therebetween.
The metal wiring layer 16b is formed on the insulator 14b. On the lower surface of the integrated circuit, a Peltier element 15 is embedded in a semiconductor substrate 11 to be integrally formed.

In the manufacturing process of the integrated circuit according to the fourth embodiment, first, device isolation insulators 13a and 13b are formed on a semiconductor substrate 11 in the same manner as in the first embodiment (FIG. 2).
(A)). Next, MOS transistors 12a and 12b are formed (FIG. 2B). Then, the insulator 1
4a, a wiring metal 16a is formed (FIG. 2C). Further, an insulator 14b is formed (FIG. 3A).

After an integrated circuit is formed on the upper surface of the semiconductor substrate 11, the lower surface of the semiconductor substrate 11, which is a portion of the transistor generating a large amount of heat, is etched using a fine processing technique, and an insulator 14c is deposited thereon.

After the Peltier device 15 is formed on the lower surface of the insulator 14c, the insulator 14d is further sealed and the Peltier device 15 is embedded. Finally, the integrated circuit in which the Peltier element 15 is integrally formed is packaged using a resin such as plastic or ceramic.

With the insulator 14c, the semiconductor substrate 11
The Peltier element 15 formed in the lower layer is electrically insulated. Usually, a large voltage is applied to the Peltier element,
Since the current is large, even if the semiconductor substrate has extremely low electric conductivity, the direct contact of the Peltier element with the semiconductor substrate affects the electrical characteristics of the transistor. Therefore, the insulator 14c is provided.

By selectively providing a Peltier element in a portion generating a large amount of heat, the transistor can be efficiently cooled with low power. When the number of multilayer wirings in the upper layer portion of the integrated circuit is not so large, cooling from the lower surface of the semiconductor substrate as in the present embodiment is more effective than cooling from the upper surface of the transistor element through the insulator as in the first embodiment. This is advantageous in view of the thermal conductivity of the material.

In the present embodiment, the Peltier device is embedded in the semiconductor substrate, and the cooling surface of the Peltier device is not exposed. Therefore, the dew condensation caused by exposing the cooling surface of the Peltier element is eliminated, and the destruction of the peripheral circuit due to the dew condensation can be avoided.

(Embodiment 5) FIG. 4 shows Embodiment 4 of FIG.
A top view (a) and a side view (b) of the fifth embodiment in which a heat sink 23 is further added to the integrated circuit of FIG.
In order to further improve the heat dissipation of the integrated circuit 21 by a passive method using heat conduction, a heat sink 23 is provided outside the package 22. The heat sink 23 is arranged in a portion where the Peltier element is built in the package. The wiring metal for the integrated circuit 21 is stored in the wire frame 24.

The heat sink 23 is formed in the same manner as in the second embodiment. When a heat sink is added to the integrated circuit of Embodiment 1 (Embodiment 2), the cooling effect is improved. Similarly, in the fifth embodiment in which a heat sink is added to the integrated circuit in the fourth embodiment, the cooling effect is improved.

(Embodiment 6) FIG. 5 shows Embodiment 4 of FIG.
A top view (a) and a side view (b) of the sixth embodiment in which a heat dissipation fan 33 is further added to the integrated circuit of FIG.

In order to further improve the heat radiation of the integrated circuit 31 as compared with the case where the heat is naturally radiated, the package 32 is used.
A heat dissipation fan 33 is provided outside. The heat-dissipating fan 33 is disposed in a portion where the Peltier element is built in the package. The wiring metal for the integrated circuit 31 is stored in the wire frame 34.

When a cooling fan is added to the integrated circuit of the first embodiment (third embodiment), the cooling effect is improved.
Similarly, in the sixth embodiment in which a heat dissipation fan is added to the integrated circuit of the fourth embodiment, the cooling effect is improved.

The integrated circuit of the present invention is not limited to the above embodiment. For example, a MOS transistor can be changed to another type of transistor. In this case, the semiconductor substrate can be changed from a Si substrate to another semiconductor substrate such as a GaAs substrate. In addition, various changes can be made without departing from the gist of the present invention.

[0058]

According to the integrated circuit of the present invention, a Peltier element is formed integrally with the integrated circuit on the upper part of the transistor element or the lower surface of the semiconductor substrate, and the Peltier element is sealed in the package, so that the semiconductor device can be efficiently manufactured. Thus, an integrated circuit that can be cooled is obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an integrated circuit according to a first embodiment.

FIGS. 2A to 2C are cross-sectional views illustrating a manufacturing process of the integrated circuit according to the first embodiment.

FIGS. 3A and 3B are cross-sectional views illustrating a manufacturing process of the integrated circuit according to the first embodiment.

FIG. 4A is a top view of the second embodiment or the fifth embodiment. FIG. 4B is a side view of the second embodiment or the fifth embodiment.

FIG. 5A shows a top view of the third embodiment or the sixth embodiment. FIG. 5B shows a side view of the third embodiment or the sixth embodiment.

FIG. 6 is a cross-sectional view of an integrated circuit according to a fourth embodiment.

[Explanation of symbols]

11: semiconductor substrate, 12a, 12b: MOS transistor, 13a, 13b: element isolation insulator, 14a, 14
b, 14c, 14d: insulator, 15: Peltier element, 1
5 ': Peltier element wiring, 16a, 16b: wiring metal, 17: source region, 18: drain region, 19: gate electrode, 21: integrated circuit, 22: package, 23 ...
Heat sink, 24: wire frame, 31: integrated circuit, 32: package, 33: heat dissipation fan, 34: wire frame.

Claims (8)

[Claims] 1. An integrated circuit having a package formed of an insulator, wherein the integrated circuit has an upper portion covered with an insulator, and a Peltier element is provided on the insulator. 2. The integrated circuit according to claim 1, wherein said package is provided with heat radiating means. 3. The integrated circuit according to claim 2, wherein said heat radiating means is a heat sink. 4. The integrated circuit according to claim 2, wherein said heat radiating means is a heat radiating fan. 5. An integrated circuit having a package formed of an insulator, wherein a Peltier element is integrally formed below a semiconductor substrate of the integrated circuit. 6. The integrated circuit according to claim 5, wherein said package is provided with heat radiating means. 7. The integrated circuit according to claim 6, wherein said heat radiating means is a heat sink. 8. The integrated circuit according to claim 6, wherein said heat radiating means is a heat radiating fan.