JPH11143682A - Buffer memory occupancy amount detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a buffer memory occupancy amount detection circuit of 1 byte detection accuracy. SOLUTION: A write side multiple circuit 2 outputs a double speed write clock (c), a write binary counter 3 frequency-divides the double speed write clock (c) into two and outputs a dual port memory write clock (e) and a write side n-ary counter 4 generates the write address (f) of a dual port memory 1. A read side multiple circuit 6 outputs a double speed read clock (d), a read binary counter 7 outputs a dual port memory read clock (g) and a read side n-ary counter 8 generates a read address (h). A subtraction circuit 11 detects a buffer memory occupancy amount (k) with 1 byte accuracy by subtracting the read address (j) transferred to a write clock (a) which is the output of a read address register 10 from the write address (i) which is the output of a write address register 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory occupancy detection circuit, and more particularly to a buffer memory occupancy detection circuit for controlling the amount of encoded information in a high-efficiency image compression encoding transmission apparatus at a constant speed.

[0002]

2. Description of the Related Art In a readable / writable dual port memory in which input data generated in a burst form is written by a write clock and read by a read clock at a constant speed, a buffer memory occupancy indicating the amount of data remaining unread in the memory Detect the amount,
There is a high-efficiency image compression encoding transmission device using a buffer memory circuit for controlling the amount of encoded information to a constant amount (speed).

In a conventional buffer memory circuit, FIGS.
8, the occupation amount of the buffer memory is detected. That is, in FIG. 5, the write binary counter 15 divides the write clock a by 2 and outputs the LSB (least significant bit) s of the write address. The write-side (n-1) -decimal counter 4 counts using the LSBs of the write address as a clock enable signal and the write clock a as a clock, and outputs a (n-1) -bit write upper address f.

The dual port memory 1 writes input data 1 by a write clock a using the write address LSBs and the write upper address f as addresses. The write address register (data type flip-flop; D-FF) 9 inputs the write upper address f, and latches the write upper (bit) address f by the write clock a using the LSBs of the write address as a clock enable signal.

The read binary counter 16 divides the read clock b by 2 and outputs the read address LSBt. The read-side (n-1) -base counter 8 counts using the read clock b as a clock using the LSBt of the read address as a clock enable signal, and
1) Generate a high-order (bit) address h for reading bits.

The dual port memory 1 outputs read data m by a read clock b using the read address LSBt and the read upper address h as address signals. The read address register 10 uses the LSBt of the read address as a clock enable signal and uses the write clock a to read the upper address h.
Is latched and changed to the clock on the write side (synchronous conversion).

A write address i output from the write address register 9 and a read address register 10
, And a difference value is output from the subtracter 11 with the read address j which is replaced with the write clock a.
The buffer memory occupancy k is detected.

FIG. 6 shows a timing relationship of the conventional buffer memory occupancy detection circuit shown in FIG. 5, and FIG. 7 shows a graph of the output result of the buffer memory occupancy of the conventional circuit. Therefore, as shown in FIG.
Since the divided address LSBs, t is used as a clock enable signal for the address registers 9 and 10, the buffer memory occupancy can be detected only with 2-byte precision.

[0009]

In the conventional circuit shown in FIG. 5, a dual port memory is used as a transmission line buffer (memory) by a write clock which is a burst clock asynchronous with a read clock. The read-side memory address is changed to the write clock using the LSB as the latch timing.

That is, as shown in the detailed diagram of the clock change operation in FIG. 8, the clock is changed by reading the address with the write clock using the address LSB as the clock enable signal of the register. For this reason, the read-side address after the clock change is a 2-byte accurate address excluding the LSB, and the detection accuracy of the buffer memory occupancy is also a 2-byte (1 byte less) accuracy.

An object of the present invention is to provide a buffer memory occupancy detection circuit capable of detecting the memory occupancy with 1-byte detection accuracy.

[0012]

According to the present invention, in a readable and writable buffer memory in which input data generated in a burst is written by a write clock and read by a read clock at a constant speed, the buffer memory remains in the buffer memory. A buffer memory occupancy indicating a data amount is detected by storing write and read address signals in write and read address registers, respectively, and subtracting the write and read address signals stored in the write and read address registers, respectively. A buffer memory occupancy detection circuit, comprising: a write clock doubling means for doubling the write clock to obtain a doubling write clock for a write address counter; A read clock doubling means for doubling a read clock of an address counter, and writing the read address signal by using the doubling write clock as a clock of the write address register and the doubling write clock as a clock of the read address register. And means for changing to a clock on the side of the buffer memory.

[0013] The doubled write and read clocks are each divided by two to provide the write and read clocks, and the write and read clocks are respectively used by the write and read address registers. It is characterized by being an enable signal.

The operation of the present invention is as follows. A multiplying circuit for doubling the frequency of the write clock and the read clock of the dual port memory is provided. The read clock is used as a clock enable signal of the register.
By latching the read side memory address,
The clock can be switched up to the address of the LSB bit, and the detection accuracy of the buffer memory occupancy can be made in units of 1 byte.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a buffer memory occupancy detection circuit according to the present invention.
5 are denoted by the same reference numerals.

In FIG. 1, a buffer memory occupancy detection circuit according to an embodiment of the present invention includes a buffer memory (dual port memory) 1, a write clock (CL).
K) a write-side multiplier 2 for multiplying the clock frequency of a by 2; a write binary counter 3 for dividing the double-speed write clock c by 2; a write-side n-ary counter 4 for generating a write address (WA) f; Write clock a
And a dual-port write clock e.

Further, a read-side multiplier 6 for doubling the clock frequency of the read clock b, a read binary counter 7 for dividing the double-speed read clock d by 2,
It has a read-side n-ary counter 8 for generating a read address h, a write address register 9 for latching a write address f, a read address register 10 for latching a read address h, and a subtraction circuit 11 for subtracting addresses i and j. .

The operation of the embodiment of the present invention will be described. A write clock for input data (WD) 1 generated in a burst and a read clock for output data (RD) m
In the readable / writable dual port memory (element) 1, the buffer memory occupancy k indicating the amount of data remaining unread in the memory is detected as follows.

That is, the write clock a is doubled in clock frequency by the write-side multiplying circuit 2,
A double-speed write clock c is output. The write binary counter 3 divides the frequency of the double speed write clock c by 2, and outputs a dual port memory write clock e. The write-side n-ary counter 4 counts the sum 5 of the dual port memory write clock (WCLK) e and the write clock a as the clock enable signal (En) e ′ using the double speed write clock c and writes the dual port memory 1. An address (WA) f is generated.

The read-side multiplying circuit 6 receives the read clock b, doubles the clock frequency, and outputs a double-speed read clock d. The read binary counter 7 is 2
The dual-speed read clock d is divided by 2 to output a dual-port memory read clock (RCLK) g. The read-side n-ary counter 8 counts the double-port memory read clock d using the dual-port memory read clock g as a clock enable signal and generates a read address (RA) h.

The write address register 9 uses a dual port memory write clock e as an enable signal and latches a write address f with a double speed write clock c. The read address register 10 uses the dual-port memory read clock g as a clock enable signal, latches the read address h with the double-speed write clock c, and replaces the read address h with the write clock.

The subtraction circuit 11 subtracts the read address j replaced by the write clock a output from the read address register 10 from the write address i output from the write address register 9 to provide a buffer with 1-byte precision. The memory occupancy k is detected.

FIG. 2 shows the timing relationship of the embodiment of the present invention shown in FIG. 1, FIG. 3 shows the output result of the buffer memory occupancy k in a graph, and FIG. 4 shows the detection result of the conventional circuit shown in FIG. (A chain line in the figure indicates the detection result of the conventional circuit). That is, it can be seen that the detection accuracy of the embodiment of the present invention is higher than that of the conventional circuit. As shown in the figure, in the embodiment of the present invention, the occupation amount with 1-byte precision can be detected.

[0025]

As described above, according to the present invention, a multiplying circuit for doubling the frequency of each of the write clock and the read clock of the dual port memory is provided, and a clock having a frequency twice that of the write clock is provided. , The read-side memory address is replaced, and the memory address L
Since even the SB bits can be detected, there is an effect that the detection accuracy of the buffer memory occupancy can be made in units of 1 byte.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of an output result according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram for comparing output results between the embodiment of the present invention and a conventional circuit.

FIG. 5 is a block diagram of a conventional buffer memory occupancy detection circuit.

FIG. 6 is a timing chart of a conventional buffer memory occupancy detection circuit.

FIG. 7 is an explanatory diagram of an output result of a conventional buffer memory occupancy detection circuit.

FIG. 8 is a detailed diagram of a clock transfer operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Dual-port memory 2,6 Doubler circuit 3,7 Divide-by-2 circuit 4,8 N-ary counter 9,10 Address register 11 Subtraction circuit

Claims (4)

[Claims] In a readable and writable buffer memory, input data generated in a burst is written by a write clock and read by a read clock at a constant speed, a buffer memory occupancy indicating the amount of data remaining in the buffer memory is determined by: A buffer memory occupancy detection circuit that stores write and read address signals in write and read address registers, respectively, and detects by subtracting the write and read address signals stored in the write and read address registers, respectively. A write clock doubling means for doubling the write clock to use a doubling write clock of a write address counter; doubling the read clock to read a doubling of the read address counter A read clock doubling means as a read clock; and using the double write clock as a clock of the write address register, and using the double write clock as a clock of the read address register, changing the read address signal to a write clock. Means for detecting the occupancy of the buffer memory. 2. The buffer memory occupancy detection circuit according to claim 1, wherein the doubled write and read clocks are divided by two to generate the write and read clocks. 3. The buffer memory occupancy detection circuit according to claim 1, wherein the write and read clocks are used as enable signals for the write and read address registers, respectively. 4. The buffer memory occupancy detection circuit according to claim 1, wherein said buffer memory is a dual port memory device.