JPH11143733A - Memory testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory testing device for easily changing a test condition even for a memory to which a control signal such as writing should be applied in the same cycle, or a memory to which a control signal should be distributed and applied in different cycles. SOLUTION: Cycle delay circuits 18A-18M are provided at the output side of each pattern generating channel of a pattern generator 13, and desired cycle delay amounts are set in the cycle delay circuit connected with the channel which outputs control data for generating a control signal to be applied to a memory 15 to be tested. Then, the desired cycle delay amounts are applied to the necessary control data by hardware, and the cycle delayed control data are applied to a waveform generator, and converted into the control signal having an actual waveform, and applied to the memory 15 to be tested.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test apparatus for testing various types of semiconductor memories, and more particularly, to a memory test apparatus having a function of freely delaying the application cycle of various control signals applied to a memory under test. Memory in which control signals must be distributed and applied in different cycles,
Another object of the present invention is to provide a memory test device capable of performing a test without changing a pattern program in any of the memories to which a control signal must be applied in the same cycle.

[0002]

2. Description of the Related Art FIG. 6 shows an outline of a conventional memory test apparatus. In the figure, 11 is a main controller, 12 is a timing generator, 1
Reference numeral 3 denotes a pattern generator, 14 denotes a waveform generator, 15 denotes a memory under test, 16 denotes a logical comparator, and 17 denotes a failure analysis memory. The main controller 11 is composed of, for example, a computer such as a workstation. The pattern generator 13 is controlled according to a pattern program and a main program stored in the main controller 11, and the pattern data, address data, Control data is output, and the pattern data, address data, and control data are input to the waveform generator 14.

The waveform generator 14 changes to H logic and L logic according to the logic values of pattern data, address data and control data given from the pattern generator 13, and is defined by a timing signal given from the timing generator 12. An analog waveform having a real waveform rising and falling at a timing is generated. That is, a test pattern signal having an analog waveform, an address signal, and a control signal are generated,
The test pattern signal, the address signal, and the control signal are applied to the memory under test 15, and the test pattern signal is written to the memory cell accessed by the address signal, and the read test pattern signal is given to the logical comparator 16.

The logical comparator 16 is provided with an expected value pattern from the pattern generator 13, compares the expected value pattern with a test pattern read from the memory under test 15, and generates a defect every time a mismatch is detected. The presence of the defective cell is stored in the defect analysis memory 17 having the same address as the address. After the test, the number of defective cells stored in the failure analysis memory 17 is counted, and it is determined whether or not the defect can be remedied.

The pattern generator 13 has at least pattern generation channels corresponding to the number of terminals of the memory under test 15 and output terminals for each channel, and generates pattern data for each channel. In a memory generally called a general-purpose DRAM, each control signal such as a write control signal WE, a control signal RAS indicating a row address application timing, and a control signal CAS indicating a column address application timing is shared in the same cycle. Given within
Control of writing and reading of the test pattern to and from the memory under test 15 is performed.

FIG. 7 shows the control signals RAS, CAS, W
The timing chart of E etc. is shown. 7A shows a chip select signal, ADD shown in FIG. 7E shows an address signal, and DQ shown in FIG. 7F shows read data. FIG. 9 shows a description example of a pattern program for generating control data for generating the control signals RAS, CAS, and WE. NOP shown in FIG. 9 is a control command for shifting to the next line, and X <XC and Y <YC are control commands for updating the X and Y values of the pattern generation address.
In FIG. 9, Q + starts from the first cycle of the pattern generation cycle.
A description example of a program up to the first cycle is shown. In the Nth cycle, the Pth cycle, and the Qth cycle, the write command WE and the control signal R indicating the application timing of the row address are set.
AS and a control signal C indicating the application timing of the column address.
A description for generating AS is added, and the control data WE _DAT , RAS _DAT , and CAS _DAT are generated from the pattern generator 13 when the Nth, Pth, and Qth cycles are executed.

In a high-speed memory called an SDRAM or the like, a signal processing circuit having a high-line structure is built in the memory, and WE, RAS, CAS are provided for each control data.
Are applied to the memory under test 15 in different cycles.
FIG. 10 shows an example of the pattern program in that case.
A description RAS for generating the control signal RAS in the Nth cycle of the pattern program is described. When the cycle further proceeds from the N cycle to the Q cycle, a description for generating the write control signal WE and a description for generating the control signal CAS indicating the application timing of the column address are added, and a cycle delayed by a predetermined cycle from the cycle in which RAS is described. WE
, And a write control command WE and a control signal CAS indicating the application timing of the column address.

In FIGS. 9 and 10, the pattern generation cycle is shown only from 1 cycle to Q cycle. However, since a pattern program needs to describe several thousand cycles or several 10,000 cycles,
Even if only the control signal generation cycle is picked up, the number becomes a great number.

[0009]

As described above, conventionally, the description of the pattern program is changed between when the control signal is applied to the memory under test 15 in the same cycle and when the control signal is applied in a different cycle. Therefore, setting the test conditions for each type of the memory under test 15 is troublesome. In other words, since the pattern program is long and the number of control signal generation cycles is large, only correcting the control signal generation cycle requires a large amount of work.

An object of the present invention is to control the generation of a control signal between a case where a memory type to be tested tests a memory to which all control signals are applied in the same cycle and a case where a memory to be applied is tested in a different cycle. It is an object of the present invention to provide a memory test apparatus capable of performing a test without changing the description of a pattern program to be executed.

[0011]

According to a first aspect of the present invention, a test pattern signal to be applied to a memory under test is generated from each pattern generation channel of a pattern generator having a plurality of pattern generation channels in accordance with a description of a pattern generation program. Pattern data for generating an address signal to be supplied to the memory under test, and control data for generating a control signal to be supplied to the memory under test. The association with each pin of the test memory is set according to the description of the main program, and the pattern data, address data, and control data output from each pattern generation channel of the pattern generator are given to the waveform generator. Timing signal generated by the generator Generates a test pattern signal, an address signal, and a control signal in which rise and fall timings are defined in accordance with the following. The test pattern signal, the address signal, and the control signal are supplied to a memory under test, and a test pattern is written to a specified address. An operation and an operation of reading the written test pattern are executed by a control signal, the test pattern signal read from the memory under test is compared with an expected value pattern, an address where a defective cell exists due to a match or mismatch is detected, and pass / fail is determined. In the memory test apparatus for determination, a cycle delay circuit that can be set to a delay amount of an arbitrary cycle is provided on the output side of each pattern generation channel of the pattern generator, and a delay setting file that stores and holds the delay amount of the cycle delay circuit is provided. The delay setting stored in this delay setting file It proposes a memory testing apparatus that constitutes the data output from each pattern generating channels to be able to delay any cycle according to the value.

According to the memory test apparatus proposed in claim 1, since data output from any pattern generation channel can be delayed by an arbitrary cycle, any control data in the control data can be changed to an arbitrary control data. The waveform can be supplied to the waveform generator after being delayed by a cycle. Therefore, according to the present invention, a desired control signal can be delayed by a desired cycle and supplied to the waveform generator without changing the description of the pattern program, so that a memory for applying all control signals in the same cycle can be provided. Even if there is, a test condition can be easily set even in a memory to which a control signal is applied in different cycles.

A memory test apparatus proposed in claim 2 of the present invention proposes a memory test apparatus configured to rewrite the storage of a delay setting file for controlling the amount of delay of a cycle delay circuit in accordance with the description of a main program. Claim 3 proposes a memory test apparatus configured to rewrite the contents of the delay setting file input from the input means and set the amount of cycle delay of the cycle delay circuit.

According to the memory test apparatus proposed in claim 2, since the main program is a program only for setting the correspondence between each pattern generation channel of the pattern generator and the pin of the memory under test, the amount of description is small. It is. Therefore, the description can be easily changed,
Since the delay amount of the cycle delay circuit can be set only by changing the description of the main program, there is an advantage that the setting of the test condition can be easily changed.

According to the memory test apparatus proposed in claim 3, the delay setting file generated by inputting from the input means only needs to input the cycle delay amount and its pin number. Is slight. Therefore, also in this case, there is an advantage that the setting can be easily changed.

[0016]

FIG. 1 shows an embodiment of the present invention. Parts corresponding to those in FIG. 6 are denoted by the same reference numerals. In the present invention, cycle delay circuits 18A, 18B... 18 are provided on the output side of each pattern generation channel of the pattern generator 13.
N and a delay setting file 1 in the main controller 11.
1A is provided.

Cycle delay circuits 18A, 18B... 18N
Respectively selects a cascade circuit of flip-flops FF, a signal input to the head of the cascade circuit of each flip-flop FF, and a signal output between each stage of the flip-flop FF, as shown in FIG. And a multiplexer MUX for extracting the data. A reference clock CLK for operating the pattern generator 13 is supplied to a clock input terminal of each flip-flop FF, and the input data is sequentially transmitted to the next stage in synchronization with the pattern generation cycle of the pattern generator 13, and the multiplexer MU
It is configured so that data delayed by an arbitrary cycle can be taken out according to the selection of X.

The means for controlling the switching state of the multiplexer MUX can be constituted by a delay setting file 11A provided in the main controller 11. At the same time, a description portion for setting each delay cycle of the cycle delay circuits 18A, 18B... 18N is provided in the main program stored in the main controller 11, and the description content of the delay setting file 11A is rewritten by the description of the main program. It is possible to configure so that each cycle delay amount of the cycle delay circuits 18A to 18N can be set. As another method, the delay setting file 11A is directly input from the input unit 19.
There is a way to rewrite.

In the configuration shown in FIG. 1, a control signal RAS for instructing a row address application timing, a control signal CAS for instructing a column address application timing, and a control signal WE for giving a write instruction are provided in the same cycle shown in FIG. When testing a memory to be applied, the cycle delay amount of each pin described in the delay setting file 11A provided in the main controller 11 is set to 0 cycle, and each cycle of each cycle delay circuit 18A to 18N is set. What is necessary is just to set the delay amount to 0 cycle.

On the other hand, when testing a memory in which the control signal must be distributed in different cycles and applied,
The cycle delay amount of each pin described in the delay setting file 11A provided in the main controller 11 is limited to the pin requiring the delay, and the required cycle delay amount may be described. By setting the delay amount in the delay setting file 11A in this manner, the cycle delay amount of the cycle delay circuit connected to the channel to which the control data for generating the control signal is output is delayed by a desired cycle. Multiplexer M
The UX switching state is set.

In the example shown in FIG. 1, the control signal RAS for instructing the row address application timing is 0 cycle, and the control signal CAS for instructing the column address application timing and the control signal WE for giving the write command are the control signal RAS from the control signal RAS. A case where the setting is made so as to be given to the memory under test 15 in a cycle delayed by three cycles is shown. That is, the control data RA
The cycle delay amount of the cycle delay circuit 18A connected to the channel from which the S _DAT is output is set to 0 cycle, and the cycle delay amount of the cycle delay circuit 18M connected to the channel to which the control data CAS _DAT is output is set to 3 cycles. In this case, the cycle delay amount of the cycle delay circuit 18N connected to the channel to which the control data WE _DAT is output is set to three cycles.

By setting as described above, the pattern generator 13 controls the control data RAS _DAT , CAS _DAT ,
Even if WE _DAT occurs in the same cycle, CAS data in these control data RAS _DAT , CAS _DAT and WE _{DAT
Since DAT} and WE _DAT are delayed by three cycles by the cycle delay circuits 18M and 18N and input to the waveform generator 14, the waveform generator 14 outputs the control signal RAS having an actual waveform as shown in FIG. Control signals CAS and WE are generated in a cycle delayed by three cycles from the generation cycle,
It is applied to the memory under test 15.

As described above, the cycle delay circuits 18M, 1
By giving a delay amount of a desired cycle at 8N,
The pattern generator 13 outputs control data RAS _DAT and CAS data.
_{Even if DAT} and WE _DAT are generated in the same cycle, the memory under test 15 can be tested normally. As a result, the control data RAS _DAT , CAS _DAT ,
The description for generating WE _DAT is as shown in FIG.
It may be described in the same write cycle. This description is the same as the description of the pattern program when the control signals RAS, CAS, and WE are applied to the memory under test 15 in the same cycle, so that memories of different models can be tested with the same description contents.

Therefore, it is not necessary to rewrite a pattern program having an enormous length for each product type. It is possible to rewrite the description of the extremely short main program or directly rewrite the description of the delay setting file 11A by the input means 19. In this case, the trouble of changing the type of memory to be tested can be greatly simplified. FIG. 5 shows a description example of the main program. In the description of the main program shown in FIG. 5, P1-5, 7-10 = I on the first line
N1, NRZA, ACLK1, and <Y0-9> designate pin numbers 1 to 5 and 7 to 10 of the memory under test 15 as input terminals, and generate address signals Y0 to Y9 having an NRZ waveform synchronized with the A clock. Generated in the vessel 14. The signal input to the pin numbers P1-5 and 7-10 is Y0
-9 means a Y address signal.

P13-17 shown in the second line is IC1 under test.
5 is assigned an X address (X0
9) are set to the input terminals. Further, the descriptions P6 and P12 in the third row mean that the pin numbers 6 and 12 are set as the input terminals, and the control signal given to the pin numbers 6 and 12 is delayed by three cycles according to the description of the DRDLY3. . This description is sent to the pattern generator 13 via the delay setting file 11A in the initial setting state in which the test is started, so that each pattern generation channel of the pattern generator 13 is associated with each pin number of the memory under test 15. And the signals to be supplied to each pin are allocated.

At the same time, the delay cycle of the cycle delay circuit assigned to the pin numbers 6 and 12 is set by the description of DRDLY3. When changing the cycle delay circuit to be delayed and when changing the delay amount,
It is only necessary to change the designation of the pin number and the numerical part in the description of DRDLY3. Since this change needs to be made only in one place in the main program, the change of the condition is very easy. In other words, since the main program is a short program of at most several lines, it is easy to search for a changed portion.

[0027]

As described above, according to the present invention, even if the memory under test 15 is a memory to which a control signal must be applied in the same cycle, the memory 15 under test is distributed to different cycles to apply the control signal. Even if the memory has to be changed, there is no need to change the long pattern program,
Alternatively, it is possible to arbitrarily change the generation cycle of the desired control signal only by directly inputting the change of the set value from the input means 19 to the delay setting file 11A. Therefore, it is possible to provide a memory test apparatus that is easy to handle, and the effect is extremely large for practical use.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of a memory test device according to the present invention.

FIG. 2 is a connection diagram for explaining a specific example of a cycle delay circuit used in the embodiment shown in FIG. 1;

FIG. 3 is a waveform chart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 4 is a diagram showing a description example of a pattern program used when the present invention is applied.

FIG. 5 is a diagram for explaining an example of a description of a main program used when the present invention is applied.

FIG. 6 is a block diagram for explaining the general outline of a conventional memory test apparatus.

FIG. 7 is a waveform chart for explaining the application timing of each control signal of a memory in which a control signal must be applied in the same cycle.

FIG. 8 is a waveform chart for explaining the application timing of each control signal of a memory in which a control signal must be distributed in different cycles and applied.

FIG. 9 is a diagram showing an example of a description of a pattern program used when testing a memory to which a control signal must be applied in the same cycle in a conventional memory test apparatus.

FIG. 10 is a diagram showing an example of a description of a pattern program used for testing a memory in which a control signal must be distributed and applied in different cycles in a conventional memory test apparatus.

[Explanation of symbols]

 Reference Signs List 11 Main controller 11A Delay setting file 12 Timing generator 13 Pattern generator 14 Waveform generator 15 Memory under test 16 Logic comparator 17 Failure analysis memory 18A to 18N Cycle delay circuit 19 Input means RAS, CAS, WE Control signal

Claims (3)

[Claims] 1. Pattern data for generating a test pattern signal to be applied to a memory under test from each channel of a pattern generator having a plurality of pattern generation channels according to a description of a pattern program, and an address signal to be applied to a memory under test And the control data for generating a control signal to be applied to the memory under test, and associating each pattern generation channel of the pattern generator with each pin of the memory under test in accordance with the description of the main program. Initially set, pattern data output from each pattern generation channel,
Address data and control data are supplied to a waveform generator. Rise and fall timings are defined according to a timing signal output from the waveform generator from the waveform generator, and a test pattern signal, an address signal, and a control signal having a real waveform are defined. The test pattern signal, the address signal, and the control signal are supplied to the memory under test, and the operation of writing the test pattern signal to the address specified by the address signal and the operation of reading the written test pattern are executed by the control signal. Compares the test pattern signal read from the memory under test with the expected value pattern,
In a memory test apparatus for detecting an address where a defective cell exists due to a mismatch and determining the quality of a memory under test, a cycle delay capable of setting an arbitrary cycle delay amount on the output side of each pattern generation channel of the pattern generator. A delay setting file for storing the amount of delay of the cycle delay circuit is provided in the controller, and the data output to each channel is delayed by an arbitrary cycle according to the delay setting value stored in the delay setting file. A memory test apparatus characterized in that the memory test apparatus is configured to be able to perform the test. 2. The memory test apparatus according to claim 1, wherein a cycle delay amount set in said cycle delay circuit is described in said main program, and the delay amount of said delay setting file is changed according to the description of said main program. A memory test apparatus characterized in that: 3. The memory test apparatus according to claim 1, wherein a cycle delay amount set in said cycle delay circuit is inputted from an input means, and said delay setting file is rewritten and set. Memory testing equipment.