JPH11143768A - Microprocessor and memory system - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To arbitrarily divide a logical address space for use of a plurality of banks without changing a connection state of a microprocessor connected to a memory having a plurality of banks with a memory. Provide a microprocessor capable of A register for storing which bit position of a logical address is used as a bank selection signal
(6) and means (2) for rewriting the contents of this register. As a result, an arbitrary address bit of the logical address can be set as a bank selection signal, and the logical address space is arbitrarily divided for use of a plurality of banks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor connected to a semiconductor memory, and more particularly, to reading data from a specific bank of a semiconductor memory having a plurality of banks and transferring data to a specific bank. The present invention relates to a technique that is effective when applied to a microprocessor that performs writing.

[0002]

2. Description of the Related Art A technique of connecting a microprocessor to a semiconductor memory having a plurality of banks, reading data from a specific bank of the memory, or writing data to a specific bank has conventionally been used. On this occasion,
In a microprocessor, an address is output by a central processing unit provided therein. In a conventional microprocessor, a bit used for selecting a bank of a memory is fixed to the most significant bit of the address.

Therefore, in a conventional microprocessor, a signal of the most significant bit of an address is always output to a signal pin for outputting a bank signal used for selecting a memory bank.

[0004]

In the conventional microprocessor, the bits used for selecting the memory bank are fixed to the most significant bit of the address as described above. However, there is a problem that the flexibility of bank allocation when using the first bank cannot be secured. That is, in the conventional microprocessor, the bit of the bank selection is fixed at the highest address, so that the signal pin of the highest address is fixedly output to the signal pin for outputting the bank signal. In a logical address space in which a plurality of processes are continuous, the logical address space can only be fixedly divided into two and different banks can be assigned to the two.

Therefore, in a system using a conventional microprocessor, there is also a demand for use such that a space is divided so that a plurality of banks can be switched and used alternately in a logical address space in which a plurality of processes are continuous. When trying to satisfy, if the signal pin where the signal of the most significant bit of the address is fixedly output is treated as a bank signal pin, a problem occurs, so the connection state of the pin between the memory and the microprocessor is changed A problem that must be done.

When the microprocessor and the memory are formed on one semiconductor substrate, it is difficult to change the connection between the microprocessor and the memory.
The above problem is exacerbated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microprocessor and a memory using a microprocessor which can divide a logical address space for use of a plurality of banks without changing the connection state with the memory outside the microprocessor. It is to provide a system.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, according to the present invention, in order to achieve the above object, data is read from or written to a memory having a plurality of banks by an address signal consisting of a plurality of bits from the central processing unit. The microprocessor includes means for switching which bit position of the plurality of bits of the address signal is used as a bank selection signal. In addition, the storage device has storage means for storing information indicating which bit position signal is to be used as the bank selection signal.

Thus, it is possible to select which bit of the address the bank select bit corresponds to, so that the logical address space can be divided without changing the connection with the memory.

[0012]

FIG. 1 shows a memory system in which a microprocessor according to an embodiment of the present invention and a memory are connected.

The microprocessor (27) shown in FIG. 1 has a central processing unit (2), a DMAC module (direct memory access control unit) (3) and a memory interface module (1). (In this embodiment, since the central processing unit (2) has a built-in cache and is connected to the memory interface module (1) via this cache, the central processing unit (2)
Called he module (2). The memory interface module (1) has CPU / Cache
The module (2) or the DMAC module (3) outputs an access request as a request. CPU / Cache module
An access request from (2) to the memory interface module (1) includes a memory access request for reading from and writing to memory and a memory interface module.
(1) There is a read / write register access request to the internal register (6). The access request from the DMAC module (3) to the memory interface module (1) includes a memory access request for memory read / write.

When there is a memory access request from the CPU / Cache module (2), the CPU / Cache module outputs a memory access request and an address as a request to the request control unit (4) in the memory interface module (1). Upon receiving the request, the request control unit (4) recognizes that the request is a memory access request, and the external bus control unit
The memory access request (18) is output to (7). External bus controller (7) receiving memory access request (18)
Controls the address control unit (8), the control signal generation unit (9), and the data control unit (10), and performs memory access.

The address control section (8) is a bank bit control signal which is bank information (contents of a register bit AMXEXT described later) stored in the register (6) in advance.
(21), and outputs a bank signal (23) for selecting a bank according to the bank bit control information, and outputs an address (26) to the memory (28). Register in advance
The bank information stored in (6) is the CPU / Cache module
(2) is information indicating which bit of the address signal output by the address control unit is used as the bank signal.
(8) selects a predetermined bit of the address signal based on the bank information and stores it as a bank signal (23) in the memory (2).
Output to 8).

The control signal generator (9) outputs a memory control signal (102) required for memory access to the memory (28), and gives a command such as READ / WRITE to the memory.

The data controller (10) controls the data buffer (11) to exchange data.

In this embodiment, a microprocessor having a built-in DMAC module is used, but a microprocessor having no built-in DMAC module may be used.

The bank information stored in the register (6) is C
The contents can be changed by rewriting the contents from the PU / Cache module (2), and the address
In (8), any bit of the address can be output as the bank signal (23). When there is a write request from the CPU / Cache to the register, the CPU / Cache module (2) outputs a register write access request as a request to the request control unit (4) and simultaneously outputs data (105) to be written to the register. . Upon receiving the register write request, the request control section (4) outputs a register access request (103) to the register R / W control section (5). Register R / W that received the register access request
Control unit (5) sends register write signal (104) to register (6).
Is output, the data (105) is written to the register.

The microprocessor (27) shown in FIG. 1 is formed on one semiconductor substrate, although not particularly limited, and the bank signal (23), the address (26) and the like are provided on pads provided on the semiconductor substrate. The signal is output to a signal output pin via a connection line, and is input to the memory (28) through the connection wiring.

A plurality of banks are formed in the memory (28). In this embodiment, a synchronous DRAM is used.

In this embodiment, the memory (28) and the microprocessor (27) are formed on separate semiconductor substrates, but in the present invention, the memory (28) is
It is apparent that the present invention can be applied to the case where the semiconductor device is formed on the same semiconductor substrate as in 7).

FIG. 2 shows an address control unit according to this embodiment.
It shows details of (8).

In FIG. 2, the request control unit (4) recognizes that the access request is a memory access request,
When the read or write access is determined, a memory access request (18) is sent to the external bus control unit (7). The external bus control unit (7) generates an output address control signal (19) according to the memory access timing. At the same time, the request address (22) is sent to the address control unit (8).

In the row address generation section (14), the row address
(24) is generated, and the column address generation unit (15) generates the column address (25). Generated row address (24)
And the column address (25) are selected according to the memory access timing according to the output address control signal (19).
The output address selected in (17) is generated.

The timing of memory access is controlled / generated by the external bus control unit (7) from the memory information (20) stored in the register (6) in advance.

The bank bit generator (13) determines which bit of the logical address is to be output as the bank signal (23) according to the bank bit control signal (21) which is the bank information stored in the register (6) in advance. Determined by selector (16) and output. Thus, by changing the bank information in the register (6), it is possible to output information at an arbitrary bit position of the logical address as a bank signal to an output pin at a predetermined position. In other words, it is possible to change the correspondence between each bit position of the logical address and the signal output pin.

In this embodiment, the register for storing the bank information is provided in the memory interface (1). However, the register may be provided outside the memory interface module (1), and the CPU / Cache module (2) Bank information may be stored in an internal storage unit.

FIG. 3 shows a connection example between a microprocessor and a synchronous DRAM having a two-bank configuration.

Since the interior of the synchronous DRAM is composed of two banks, the bit required for selecting this bank is 1 bit, and the synchronous DR is used as a bank signal (BANK).
Input to AM.

The memory control signals required for accessing the synchronous DRAM (28) include a clock (CLK), a clock enable signal (CKE), a chip select signal (CS), a row address strobe signal (RAS), and a column address strobe ( CA
S), a write enable signal (WE), a data mask enable signal (DQM), and a bank signal (BANK) ((23) in FIG. 1). These memory control signals and address (A), data
(DATA) is connected to the microprocessor (27). The microprocessor (27) outputs various control signals to give various commands to the synchronous DRAM (28), thereby realizing read and write access.

FIG. 4 is a schematic diagram of the register (6). This register is a 32-bit register.
In the bit AMXEXT, information (bank information) for selecting whether to use the bank signal (23) as the most significant bit of the address or the second most significant bit of the address is set.

When the content of the register bit AMXEXT is 0, the most significant bit of the address is used as a bank signal,
When the content of AMXEXT is 1, the second highest bit of the address is used as a bank signal.

The register (6) also stores information used for other purposes, and the other bits TRC [2-0] and TPC [2-
0], RCD [1-0], and TRWL [2-0] are bits that define the timing of memory access, and are set according to the type and operating frequency of the synchronous DRAM to be used.

In this embodiment, the bank information bits are
Although AMXEXT is one bit, a plurality of bits may be provided. This makes it possible to use the n-th bit from the upper address as a bank signal. It is also conceivable to use a plurality of bits in an address as a bank signal in accordance with the number of banks of the memory to be used.

FIG. 5 shows an address space when the bank selection bit AMXEXT is set to 0. By using the most significant bit of the address as a bank signal, the address space is divided into two areas depending on whether the most significant bit of the address is 0 or 1, and each is mapped to banks A and B of the synchronous DRAM. You.

FIG. 6 shows an address space when the bank selection bit AMXEXT is set to 1. The address space is divided into four regions by using the second highest bit of the address as a bank signal. The area where the second most significant bit of the address is 0 is mapped to bank A of the synchronous DRAM, and the area where the second most significant bit of the address is 1 is mapped to bank B of the synchronous DRAM.

As shown in FIG. 6, Process 1 and Process 2 can use different banks in a continuous address space. In this embodiment, the address space is divided into four regions because the second bit from the upper address is used as a bank signal for the synchronous DRAM, but the n-th bit from the upper address must be used. May be used to divide the address space into 2 n areas.

In this embodiment, since a synchronous DRAM having a two-bank configuration is used, the bank signal is one bit. However, a synchronous DRAM having a four-bank configuration may be used. A synchronous DRAM having a 4-bank configuration has a 2-bit bank signal. When these 2 bits are selected from the most significant 2 bits of the address, the address space is divided into four areas, which are mapped to banks A, B, C, and D, respectively. Assuming that these two bits are the second and third bits from the top of the address, the address space is divided into eight areas, each of which is a synchronous DRAM bank A, B, C, D, A, B, C and D are mapped.

FIG. 7 is a timing chart at the time of read access of the synchronous DRAM, and FIG. 8 is a timing chart at the time of write access of the synchronous DRAM.

In FIG. 7, AC is applied to the synchronous DRAM in the Tr cycle.
By issuing a TV command, the row address is notified and Tr
Wait for synchronous DRAM specified cycle with w. Thereafter, a READ command is issued in the Tc1 cycle to notify the column address, and after waiting for the latency defined by Tc2 and Tc3 and the synchronous DRAM, sampling of the read DATA is performed.

In FIG. 8, similarly, the row address is notified by issuing the ACTV command in the Tr cycle, and the synchronous DRAM specified cycle waits in Trw. Then WRI in Tc1 cycle
Issue a TE command to notify the column address. At the same time, drive the write DATA.

In the case where the subsequent access is to access the same address as the row address at the time of issuing Tr, the access can be continued only by issuing a Tc1 cycle READ or WRITE command, and the access can be performed at high speed by Tr and Trw cycles. Can do it. Normal synchronous DR
AM has multiple banks, and each bank has
It can be activated by ACTV command,
Access can be continued simply by issuing a READ or WRITE command.

When the program configuration as shown in FIG. 6 is implemented, even if the row address differs between the access to the program of the process 1 and the data access of the process 1, the above-mentioned high-speed access is possible because the banks are different. . The same applies to the access of the program and data of the process 2.

Further, when accesses from different banks are consecutive, a command for a subsequent access can be issued after a previous access READ command is issued. In the case of continuous read access, after issuing a READ command as the first access in Tc1 cycle in FIG. 7, the second access command can issue an ACTV command after Tc3 and a READ command after Td2 cycle. Not only when the row address of the second access is the same, but also when the row address is different, data can be made continuous on the data bus, and high-speed access can be performed because unnecessary empty cycles do not occur. Similarly, in the case where write access is continuous, after issuing a WRITE command in the Tc1 cycle as the first access in FIG. 8, the second access can be started by issuing the ACTV command after the Tc3 cycle, and the Trw following the Tc4 cycle
Since the WRITE command can be issued in the l1 cycle, useless empty cycles do not occur even if the row addresses of the write access of the second access are different, and high-speed access is possible.

[0046]

According to the microprocessor of the present invention,
Since there is means for switching which bit position of a plurality of bits of the address signal is used as the bank selection signal, the logical address space can be used for a plurality of banks without changing the connection state with the memory. It can be divided arbitrarily.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory system using a microprocessor according to one embodiment of the present invention.

FIG. 2 is a block diagram of an address control unit of the microprocessor according to one embodiment of the present invention.

FIG. 3 is a connection diagram of a microprocessor and a synchronous DRAM according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a register of a microprocessor according to one embodiment of the present invention.

FIG. 5 is an address space diagram when the bank selection bit of the synchronous DRAM of the two-bank configuration is set to the most significant bit of the address.

FIG. 6 is an address space diagram when the bank selection bits of the synchronous DRAM of the two-bank configuration are the second most significant bit of the address.

FIG. 7 is a timing chart when a synchronous DRAM is read-accessed using the microprocessor according to one embodiment of the present invention.

FIG. 8 is a timing chart when a synchronous DRAM is write-accessed using the microprocessor according to the embodiment of the present invention.

[Explanation of symbols]

(1) Memory interface module, (2) CP
U / Cache module, (3) DMAC, (4) request controller, (5) register R / W controller, (6) register, (7) external bus controller, (8) address Control section, (9) control signal generation section, (10) data control section, (11) data buffer, (13) bank bit generation section, (14) row address generation section, (15) ...
Column address generation unit, (16) ... bank bit selector, (17) ... output address selector, (27) ... microprocessor, (28) ... synchronous DRAM.

Claims (6)

[Claims] 1. A central processing unit and a memory for inputting an address signal from the central processing unit, outputting an address to a memory having a plurality of banks, and reading data from the memory or writing data to the memory. A microprocessor comprising: a storage unit that stores bank information indicating which bit of the address signal is used as a bank signal for selecting a bank. . 2. The microprocessor according to claim 1, wherein bank information stored in said storage means is input, and a bit at a predetermined position in said address signal is output to a memory as a bank signal in accordance with said bank information. And a control unit for performing the control in the memory control unit. 3. A microprocessor having a central processing unit for reading data from a memory having a plurality of banks or writing data to the memory in response to an address signal composed of a plurality of bits from the central processing unit. A microprocessor for storing information on which bit position of the plurality of bits of the address signal is to be used as a signal for selecting a bank. 4. A microprocessor having a central processing unit for reading data from a memory having a plurality of banks or writing data to the memory in response to an address signal composed of a plurality of bits from the central processing unit. A microprocessor for changing which bit position of the plurality of bits of the address signal is used as a signal for selecting a bank; 5. A plurality of signal output pins, and a bank signal for designating an address and a bank is output to the memory from these pins to read data from the memory or write data to the memory. In the semiconductor integrated circuit device, a correspondence relationship between each bit position of an address issued in the semiconductor integrated circuit device and the signal output pin is represented by:
A semiconductor integrated circuit device, comprising: means for changing within the semiconductor integrated circuit device. 6. A memory system having a microprocessor and a memory connected to the microprocessor, wherein the memory has a plurality of banks, the microprocessor has a central processing unit, and a central processing unit. Storage means for storing bank information indicating which bits of the output address signal for accessing the memory are to be used as a bank signal for selecting a bank.