JPH11143823A - Computer device and bus control method applied to the device - Google Patents

Abstract

(57) Abstract: A bus request of an external bus master is put on hold based on an operating state of a CPU, so that an operation of the CPU required for a priority process can be reliably executed. . In a microcomputer having a CPU, a local bus, and a bus arbitration circuit, the bus arbitration circuit holds a bus request from an external bus master when a specific operation state of the CPU by a CPU monitoring logic circuit. I do. As a result, the bus priority of the CPU 1 is ensured, and the CPU 1 reliably executes, for example, a specific operation for which the processing should be completed within a certain time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a CP
The present invention is applied to a microcomputer in which U, bus, and bus control circuits are integrated, and particularly relates to a computer device having an external bus master function.

[0002]

2. Description of the Related Art Conventionally, for example, a one-chip microcomputer used for an embedded microcomputer includes a CPU.
In addition to the (CPU core), a bus (hereinafter referred to as a local bus) for the CPU to access an I / O device and a memory and a bus arbitration circuit for performing arbitration control (bus arbitration) of the local bus are integrated. Built-in methods have been developed.

Further, microcomputers have been developed in which an external bus master function is added to this system. The external bus master function is a function in which a certain external I / O device obtains a right to use a local bus and can access another I / O device or memory connected to the local bus.

The bus arbitration circuit arbitrates the right to use the bus of the CPU when there is a bus request from an external bus master. Here, the right to use the bus of the CPU is not always high in priority, and the right to use the local bus may be given to the external bus master in response to a bus request from the external bus master regardless of the operation content of the CPU. .

[0005]

As described above, in the conventional microcomputer having the external bus master function, the external bus master obtains the right to use the local bus irrespective of the operation of the CPU, and gives the right to use the local bus. In some cases, another connected I / O device or memory is accessed. However, in the operation content of the CPU, there is a process that needs to end the processing within a certain time.
When the CPU shifts the right to use the local bus in response to a bus request from the external bus master during execution of the process, the CPU loses the right to use the local bus, so that access such as memory access becomes impossible. A situation occurs in which the processing of the process cannot be completed within a certain time. It is desirable to suspend a bus request from an external bus master during such a critical process of the CPU.

An object of the present invention is to suspend the bus request of an external bus master based on the operation state of the CPU so that the operation of the CPU required for priority processing can be executed reliably. It is in.

[0007]

SUMMARY OF THE INVENTION The present invention relates to a computer device in which a CPU, a bus, and a bus control means having a bus arbitration function are integrated in one chip. The present invention is applied to a computer device having means for suspending the external bus master function accordingly. The external bus master function means that an I / O device other than the CPU is used as an external bus master means.
This function obtains the right to use the local bus connected to the CPU and can access other I / O devices and memories connected to the local bus.

According to the present invention, when the CPU is using a local bus to execute a process, such as an interrupt process, which needs to be terminated within a certain period of time, the bus control means is connected to the external bus master means. , And control is exercised to secure the bus priority of the CPU. Therefore, the CPU can secure the right to use the local bus during the processing of a critical process, so that the processing of the process can be completed within a predetermined time.

More specifically, the present invention has a monitoring means for monitoring a predetermined specific operating state of the CPU, and the bus control means, when the specific operating state of the CPU is recognized by the monitoring means, the monitoring means. The bus priority of the CPU is secured, and the right to use the bus from the external bus master is suspended. The monitoring means has a logic circuit for setting information such as a flag when the CPU is in a specific operation state, for example.

As another aspect of the present invention, there is provided timer means for monitoring the elapse of a priority time for securing a bus priority of a CPU for a predetermined time, and the bus control means includes a bus use right from an external bus master. When the request is received, the timer means recognizes that the priority time has not elapsed, and secures the bus priority of the CPU and suspends the bus use right of the external bus master. Even in such a method, the CPU can perform a so-called critical process.
The right to use the local bus is surely secured, and the processing of the process can be completed within a certain time.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a computer device related to the first embodiment, and FIG. 2 is a flowchart for explaining the operation of the same embodiment. (First Embodiment) As shown in FIG.
This is a microcomputer in which a CPU core (hereinafter simply referred to as a CPU) 1, a local bus 2, and a bus arbitration circuit (bus control means) 3 are integrated in one chip. Further, the device 10 has an external bus master control unit 4 for controlling an external bus master function. The external bus master control unit 4 includes a CPU monitoring logic circuit 5 and an AND gate circuit 6.

The CPU monitoring logic circuit 5 is a circuit for monitoring a specific operation state among the internal operation states of the CPU 1, and more specifically, for holding information indicating the operation state at the time of interrupt processing, for example. It has a flip-flop. The AND gate circuit 6 is a gate circuit for controlling the transfer of the bus request BREQ from the external bus master 7 to the bus arbitration circuit 3, and is controlled by information held in the CPU monitoring logic circuit 5.

The bus arbitration circuit 3 has a CP
It has a function of arbitrating the right to use the local bus 2 between U1 and the external bus master 7. In the present embodiment, the bus arbitration circuit 3 sends the bus request B from the external bus master 7 to the AND gate circuit 6 of the external bus master control unit 4.
When receiving the REQ, the external bus master 7 outputs a grant signal BGNT for acknowledging the use of the local bus 2.

Here, the external bus master 7 is assumed to be an I / O device that uses the local bus 2 in order to access a memory or an I / O device connected to the local bus 2 in addition to the CPU 1. External bus master 7
Obtains the priority of the local bus 2, the CPU 1 cannot use the local bus 2 during the period of the priority. (Operation of the First Embodiment) The operation of the first embodiment will be described below with reference to the flowchart of FIG. 2 together with FIG.

First, when there is a bus request from the CPU 1 to obtain the right to use the local bus 2, the bus arbitration circuit 3 outputs a grant signal BGNT and
U1 is given priority over the local bus 2 (step S1).
1, S2). The CPU 1 uses the local bus 2 to
A data processing operation for accessing a memory or an I / O device connected to the local bus 2 is executed.

A bus request B for obtaining the right to use the local bus 2 from the external bus master 7 during the operation of the CPU 1
When REQ is output, the external bus master control unit 4 checks the internal operation of the CPU 1 (step S3).
YES, S4). Here, the CPU monitoring logic circuit 5
Holds information indicating the operation state when the CPU 1 is executing a specific operation (for example, interrupt processing) set in advance. The AND gate circuit 6 functions to inhibit the transfer of the bus request BREQ from the external bus master 7 when the CPU monitoring logic circuit 5 holds the information.

That is, if the CPU 1 is executing a specific operation such as an interrupt process, the bus arbitration circuit 3 outputs the grant signal BGNT to the external bus master 7 even if the bus request BREQ is output from the external bus master 7.
, The priority of the local bus 2 of the CPU 1 is secured (YES in step S5, S6). In other words, during the period of the specific operation state of the CPU 1, the bus request BREQ of the external bus master 7 is suspended.

On the other hand, when the CPU monitoring logic circuit 5 does not hold the information (CP
To release the specific operation state of U1, the bus request BREQ from the external bus master 7 is transferred to the bus arbitration circuit 3 (NO in step S5). The bus arbitration circuit 3 outputs a grant signal BGNT to the external bus master 7 in response to the bus request BREQ from the external bus master 7, and gives the right to use the local bus 2 (step S7). Thereby, the external bus master 7
Can access a memory, an I / O device, and the like connected to the local bus 2 using the local bus 2. When the external bus master 7 obtains the priority of the local bus 2, the CPU 1 cannot use the local bus 2 during the period of the priority.

As described above, according to the present embodiment, the CPU
1 is monitored, and in the specific operation state, even if the bus request BREQ is output from the external bus master 7,
The bus request BREQ is put on hold. Therefore, CPU1
By securing the priority of the local bus 2 of the
U1 can continue a critical specific operation such as an interrupt process, for example, and end the process within a certain time. (Modification of First Embodiment) FIG. 3 is a block diagram related to a modification of the first embodiment.

This modified example is an external bus master control unit 14 having a register 20 for holding information indicating the specific operation state of the CPU 1 and an AND gate circuit 21 in addition to the CPU monitoring logic circuit 5 and the AND gate circuit 6.
It has.

The register 20 is configured so that information can be set and changed by an application program. The AND gate circuit 21 outputs a control signal for opening the gate to the AND gate circuit 6 when the information set in the register 20 matches the information held in the CPU monitoring logic circuit 5. That is, the AND gate circuit 6 responds to the control signal from the AND gate circuit 21 when the information of the register 20 and the information of the CPU monitoring logic circuit 5 match, and the bus request BREQ from the external bus master 7 is bus arbitrated. Circuit 3
Transfer to

According to such a modified example, it is easy to change the specific operation state of the CPU 1 for securing the priority of the local bus 2 by an application program. In the above-described first embodiment, the specific operation state monitored by the CPU monitoring logic circuit 5 is set in advance. On the other hand, in the present modified example, the setting of the specific operation state can be changed by using the register 20, so that not only the operation such as the interrupt processing but also the CPU 1 necessary for executing the application program is executed. Can be arbitrarily set as the critical operation state. (Second Embodiment) FIGS. 4 and 5 are a block diagram and a flowchart relating to the second embodiment. This embodiment is a computer device including an external bus master control unit 24 having a timer circuit 22 and an AND gate circuit 6.

The timer circuit 22 operates according to time information set by an application program.
1 and the bus request B from the external bus master 7 from the AND gate circuit 6 until a predetermined time elapses.
A control signal for prohibiting REQ transfer is output. That is, the timer circuit 22 is a timer means for holding a priority time for securing the priority of the local bus 2 during the period when the CPU 1 executes the specific operation.

The operation of this embodiment will be described below with reference to the flowchart of FIG. First, when there is a bus request from the CPU 1 to obtain the right to use the local bus 2, the bus arbitration circuit 3 outputs a grant signal BGNT to give the CPU 1 priority over the local bus 2 (steps S10 and S11). . The CPU 1 uses the local bus 2 to execute a data processing operation for accessing a memory, an I / O device, and the like connected to the local bus 2. At this time, if the operation of the CPU 1 is a specific operation set in advance, the timer circuit 22 sets time data for securing a predetermined priority time by the application program (step S12). The timer circuit 22 performs a time counting operation from the start of the specific operation of the CPU 1 to the set time data.

During the operation of the CPU 1, a bus request B for obtaining the right to use the local bus 2 from the external bus master 7
When REQ is output, in the external bus master control unit 24, the elapsed time is checked by the timer circuit 22 (step S14). That is, it is determined whether or not a predetermined time has elapsed since the specific operation state of the CPU 1 started.

If the priority time has not passed by the timer circuit 22, the AND gate circuit 6 sets the external bus master 7
The transfer of the bus request BREQ is prohibited. Therefore, if the CPU 1 is executing a specific operation such as an interrupt process, the bus request BREQ
Is output, the bus arbitration circuit 3 does not output the grant signal BGNT to the external bus master 7 and secures the priority of the local bus 2 of the CPU 1 (NO in step S14, S15). In other words, CP
Due to the period of the specific operation state of U1, the bus request BREQ of the external bus master 7 is in a suspended state.

On the other hand, after the elapse of the priority time by the timer circuit 22 or when the timer circuit 22 is not operating (when the CPU 1 is in an operating state other than the specific operation), the AND gate circuit 6 controls the bus from the external bus master 7. The request BREQ is transferred to the bus arbitration circuit 3 (step S
14 YES). The bus arbitration circuit 3
In response to the bus request BREQ from the external bus master 7, a grant signal BGNT is output to the external bus master 7 to grant the right to use the local bus 2 (step S16). As a result, the external bus master 7 can use the local bus 2 to access a memory, an I / O device, and the like connected to the local bus 2. When the external bus master 7 obtains the priority of the local bus 2, the CPU 1 cannot use the local bus 2 during the period of the priority.

As described above, according to the present embodiment, the CPU
1 can be secured as a priority time of the local bus 2 for a predetermined time after the start of the specific operation. That is, during the priority time, the bus request BRE is
Even when Q is output, the bus request BREQ can be put on hold and the priority of the local bus 2 of the CPU 1 can be maintained. Therefore, the CPU 1 can continue until a critical specific operation such as an interrupt process is completed. (Third Embodiment) FIGS. 6 and 8 are a block diagram and a flowchart relating to the third embodiment. The present embodiment is a computer device including an external bus master control unit 34 having an interrupt controller 23 and an AND gate circuit 6.

When an external interrupt signal to the CPU 1 is generated, the interrupt controller 23 outputs an interrupt signal to the CPU 1 and prohibits the transfer of the bus request BREQ from the external bus master 7 from the AND gate circuit 6 during the interrupt processing. Output a control signal for

The operation of this embodiment will be described below with reference to the flowchart of FIG. First, when there is a bus request for obtaining the right to use the local bus 2 from the CPU 1, the bus arbitration circuit 3 outputs a grant signal BGNT to give the CPU 1 priority over the local bus 2 (steps S20, S21). . The CPU 1 uses the local bus 2 to execute a data processing operation for accessing a memory, an I / O device, and the like connected to the local bus 2.

During the operation of the CPU 1, a bus request B for obtaining the right to use the local bus 2 from the external bus master 7
When the REQ is output, the external bus master control unit 34 checks whether or not the CPU 1 is executing an interrupt process (YES in step S22, S23). That is, when a control signal is output from the interrupt controller 23 in response to the external interrupt signal, the AND gate circuit 6 prohibits the transfer of the bus request BREQ from the external bus master 7. Therefore, since the CPU 1 is executing the interrupt processing, even if the bus request BREQ is output from the external bus master 7, the bus arbitration circuit 3 does not output the grant signal BGNT to the external bus master 7,
The priority of the local bus 2 of the CPU 1 is secured (YES in step S23, S25). In other words, CPU
When 1 is the interrupt processing period, the bus request BREQ of the external bus master 7 is in a suspended state. Here, step 2
The processing of No. 4 will be described later as a modified example.

On the other hand, when the CPU 1 operates other than the interrupt processing, the AND gate circuit 6 transfers the bus request BREQ from the external bus master 7 to the bus arbitration circuit 3 (NO in step S23). The bus arbitration circuit 3 receives a bus request B from the external bus master 7
In response to REQ, a grant signal BGNT is output to the external bus master 7 to grant the right to use the local bus 2 (step S26). As a result, the external bus master 7 can use the local bus 2 to access a memory, an I / O device, and the like connected to the local bus 2. When the external bus master 7 obtains the priority of the local bus 2, the CPU 1 cannot use the local bus 2 during the period of the priority.

As described above, according to the present embodiment, the CPU
At the time of interrupt processing in which 1 is a critical specific operation, even when the bus request BREQ is output from the external bus master 7, the bus request BREQ can be put on hold and the priority of the local bus 2 of the CPU 1 can be maintained. Therefore, the CPU 1 can continue the interrupt processing until the processing ends. Although the external interrupt processing has been described in the embodiment, the present invention can be similarly applied to the internal interrupt processing. (Modification of Third Embodiment) FIG. 7 is a block diagram related to a modification of the third embodiment.

In this modification, in addition to the interrupt controller 23 and the AND gate circuit 6, a register 25 for holding information for securing the bus priority of the CPU 1 for a part or all of the external / internal interrupt processing. An external bus master control unit 44 having The register 25 is configured so that information can be set and changed by an application program (SW).

The AND gate circuit 6 has a register 25 in response to an interrupt control signal from the interrupt controller 23.
Is set in the external bus master 7
From the bus request BREQ.

The operation of this modification is the same as that shown in the flowchart of FIG. However, in this modified example,
As shown in step S24, the external bus master control unit 4
At 4, it is determined whether to secure the bus priority of the CPU 1 or to accept the bus request BREQ from the external bus master 7 based on the information held in the register 25.

That is, when a control signal is output from the interrupt controller 23 in response to an external interrupt signal, the AND gate circuit 6 outputs a bus request BREQ from the external bus master 7 when information is set in the register 25.
Is prohibited (YES in step S24). Therefore, even when the bus request BREQ is output from the external bus master 7 at the time of the interrupt processing of the CPU 1, the bus arbitration circuit 3 does not output the grant signal BGNT to the external bus master 7, and gives priority to the local bus 2 of the CPU 1. (Step S25). In other words, C
While PU1 is performing the interrupt processing, the bus request BREQ of the external bus master 7 is in a suspended state.

On the other hand, even when the CPU 1 performs the interrupt processing, if the information is not set in the register 25, the AND gate circuit 6 outputs the bus request B from the external bus master 7.
REQ is transferred to the bus arbitration circuit 3 (NO in step S24). The bus arbitration circuit 3 outputs the grant signal BGNT to the external bus master 7 in response to the bus request BREQ from the external bus master 7, and gives the right to use the local bus 2 (step S2).
6).

In the case of such a modified example, external /
For some or all of the internal interrupt processing, the register 25 can be used to arbitrarily select whether or not to secure the bus priority of the CPU 1. (Fourth Embodiment) FIGS. 9 and 11 are a block diagram and a flowchart relating to a fourth embodiment. The present embodiment is a computer device including an external bus master control unit 54 having an internal operation monitoring circuit 30 for outputting an operation instruction signal corresponding to an internal operation of the CPU 1 and a priority controller 31.

The internal operation monitoring circuit 30 outputs operation instruction signals corresponding to internal operations of the CPU 1 such as instruction fetch, data write, data read, I / O write, I / O read, and interrupt processing. The priority controller 31 has a function of setting the internal operation state of the CPU 1 corresponding to each operation instruction signal and the priority including the bus request BREQ from the external bus master 7 based on the preset information.

Hereinafter, the operation of this embodiment will be described with reference to the flowchart of FIG. First, when there is a bus request from the CPU 1 to obtain the right to use the local bus 2, the bus arbitration circuit 3 sends the grant signal BGNT
To give the CPU 1 the priority of the local bus 2 (steps S30 and S31). The CPU 1 uses the local bus 2 to execute a data processing operation for accessing a memory, an I / O device, and the like connected to the local bus 2.

A bus request B for obtaining the right to use the local bus 2 from the external bus master 7 during the operation of the CPU 1
When the REQ is output, the external bus master controller 54 executes the internal operation of the CPU 1 and the priority setting process including the bus request BREQ from the external bus master 7 (YES in step S32, S34). Here, the process of step 33 will be described later as a modified example.

The priority controller 31 determines the internal operation of the CPU 1 such as instruction fetch, data write, data read, I / O write, I / O read, and interrupt processing, and the priority including the bus request BREQ from the external bus master 7. Is set and the bus request BREQ is sent from the external bus master 7.
It is determined whether the internal operation state of the CPU 1 has a relatively high priority. That is, even if the bus request BREQ is output from the external bus master 7 while the CPU 1 is executing the interrupt processing of a relatively high priority, the bus arbitration circuit 3 sends the grant signal BGNT to the external bus master 7. Is not output and the CPU
The priority of the local bus 2 is secured (NO in step S35, S37). In other words, the bus request BR of the external bus master 7 is
The EQ is put on hold.

On the other hand, when the CPU 1 is executing a relatively low priority operation, for example, an I / O read operation, the bus arbitration circuit 3 operates in accordance with the priority order from the priority order controller 31. , Bus request BREQ from external bus master 7
, The grant signal BGNT is output to the external bus master 7 to grant the right to use the local bus 2 (step S
35, YES, S36). As a result, the external bus master 7 can use the local bus 2 to access a memory, an I / O device, and the like connected to the local bus 2. When the external bus master 7 obtains the priority of the local bus 2, during the period of the priority, the CPU 1 cannot use the local bus 2 except for an operation having a relatively high priority.

As described above, according to the present embodiment, the CPU
1 together with the bus request B from the external bus master 7
By setting the priority order of the REQ, during the internal operation of the CPU 1 having a relatively high priority, even if the bus request BREQ is output from the external bus master 7, the bus request BREQ is suspended and the local bus 2 of the CPU 1 is set. Priority can be maintained. Therefore, by setting the priority of the critical specific operation of the CPU 1 relatively high, even when the bus request BREQ is output from the external bus master 7, the priority of the bus can be secured until the operation is completed. It becomes possible. (Modification 1 of Fourth Embodiment) FIG. 10 is a block diagram related to Modification 1 of the fourth embodiment.

This modified example includes an external bus master control unit 64 having a register 32 for setting a priority order for the bus request BREQ from the external bus master 7 in addition to the internal operation monitoring circuit 30 and the priority order controller 31. The register 32 is configured so that information on the priority order is set by the application program and can be changed. The priority order controller 31 sets the priority order for the bus request BREQ from the external bus master 7 based on the information set in the register 32, and determines whether or not to give priority to the internal operation of the CPU 1 currently being executed. I do.

The operation of this modification is the same as that shown in the flowchart of FIG. However, in the present modified example, as shown in step S33, the priority controller 31 refers to the register 32 and determines whether to secure the bus priority of the CPU 1 or to accept the bus request BREQ from the external bus master 7. I do.

That is, when the CPU 1 is executing the interrupt processing of a relatively high priority, the external bus master 7
, The bus arbitration circuit 3 does not output the grant signal BGNT to the external bus master 7 and secures the priority of the local bus 2 of the CPU 1 (NO in step S35, S3).
7). When the CPU 1 is executing an operation of a relatively low priority, for example, an I / O read operation, the bus arbitration circuit 3 sets the external bus master in accordance with the priority from the priority controller 31. 7 outputs a grant signal BGNT to the external bus master 7 in response to the bus request BREQ from the external bus master 7 to grant the right to use the local bus 2 (step S35).
YES, S36).

According to such a modification, the relative priority of the bus request BREQ from the external bus master 7 can be arbitrarily set by the register 32 with respect to the priority of the internal operation of the CPU 1. Become. (Modification 2 of Fourth Embodiment) FIG. 12 is a block diagram related to Modification 2 of the fourth embodiment.

In this modification, the priority order controller 31
Based on information set in advance, a function for setting the internal operation state of the CPU 1 corresponding to each of the operation instruction signals and a priority including a bus request BREQ from the external bus master 7 and a function for setting the priority, It has a function of notifying an I / O device connected to the local bus 2 via the pin 60. Such a priority controller 31
, The I / O device can function as the external bus master 7 that actively performs the bus request BREQ. (Third Modification of the Fourth Embodiment) FIG. 13 is a block diagram related to a third modification of the fourth embodiment.

In this modification, the priority order controller 31
Receives a plurality of bus requests BREQ from a plurality of external bus masters via the external pins 61 and receives the plurality of bus requests BREQ.
It has a function of setting the priority order including the REQ and the internal operation state of the CPU 1. Therefore, the priority of the external bus master 7 of the present embodiment is set for the bus request BREQ from another external bus master together with the priority for the internal operation state of the CPU 1. (Modification 4 of Fourth Embodiment) FIG. 14 is a block diagram related to Modification 4 of the fourth embodiment.

This modification is the modification 1 shown in FIG.
And a modification 3 shown in FIG. 13. That is, an external bus master control unit 64 having a register 32 for setting a priority order for each bus request BREQ received from a plurality of external bus masters via the external pins 61 is provided. The register 32 is configured so that information on the priority order is set by the application program and can be changed. Based on the information set in the register 32, the priority controller 31
A priority is set for each bus request BREQ from a plurality of external bus masters.

[0053]

As described above in detail, according to the present invention, by applying the present invention to a microcomputer having an external bus master function, a bus request from an external bus master can be received when the operating state of the CPU is a so-called critical process. By suspending, the bus priority of the CPU can be secured. Therefore, it is possible to reliably execute the operation of the CPU necessary for the priority processing.

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram showing a configuration of a computer device related to a first embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment.

FIG. 3 is an exemplary block diagram showing the configuration of a computer device according to a modification of the embodiment.

FIG. 4 is an exemplary block diagram illustrating a configuration of a computer device related to the second embodiment.

FIG. 5 is a flowchart for explaining the operation of the second embodiment.

FIG. 6 is an exemplary block diagram showing the configuration of a computer device related to the third embodiment.

FIG. 7 is an exemplary block diagram showing the configuration of a computer device related to a modification of the third embodiment.

FIG. 8 is a flowchart for explaining the operation of the third embodiment.

FIG. 9 is a block diagram showing a configuration of a computer device related to the fourth embodiment.

FIG. 10 is an exemplary block diagram illustrating a configuration of a computer device related to a first modification of the fourth embodiment.

FIG. 11 is a flowchart for explaining the operation of the fourth embodiment.

FIG. 12 is a block diagram showing a configuration of a computer device related to a second modification of the fourth embodiment.

FIG. 13 is a block diagram showing a configuration of a computer device related to a third modification of the fourth embodiment.

FIG. 14 is a block diagram showing a configuration of a computer device related to a fourth modification of the fourth embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU core 2 ... Local bus 3 ... Bus arbitration circuit (bus control means) 4, 14, 24, 34, 44, 54, 64 ... External bus master control unit 5 ... CPU monitoring logic circuit (monitoring means) 6 ... AND Gate circuit 7 External bus master 10 Computer device 20 Register 21 AND gate circuit 22 Timer circuit 23 Interrupt controller 25 Register 30 Internal operation monitoring circuit 31 Priority controller (priority setting means) 32 Register

Claims (16)

[Claims] 1. A computer device in which a CPU, a bus, and a bus control means having a bus arbitration function are integrated in one chip, wherein the bus control means receives a request for a bus use right from an external bus master means. A computer device having means for securing a bus priority of the CPU according to an operation state of the CPU when receiving the bus, and suspending a bus use right from the external bus master means. 2. A computer device in which a CPU, a bus, and a bus control means having a bus arbitration function are integrated in one chip, comprising a monitoring means for monitoring a predetermined specific operation state of the CPU. When the bus control means receives a request for the right to use the bus from the external bus master means, the bus control means controls the C bus by the monitoring means.
A computer apparatus comprising: means for securing a bus priority of a CPU when recognizing a specific operation state of a PU and suspending a bus use right from the external bus master means. 3. The computer device according to claim 2, wherein the specific operation state of the CPU is an operation of an interrupt process. 4. A bus control method applied to a computer device in which a CPU, a bus, and a bus control means having a bus arbitration function are integrated in one chip, wherein the bus control means comprises a bus from the CPU. CPU in response to a request for usage right
Giving a bus priority to the CPU; determining whether or not the CPU is in a predetermined specific operation when receiving a bus use right request from an external bus master means; In the case of an operation, a process of suspending the right to use the bus from the external bus master means, and in a case where the CPU is not in a specific operation, a step of giving a bus priority to the external bus master means. A bus control method, which is executed. 5. The monitoring means has register means for setting contents of a specific operation state of the CPU by application software, and changes the contents of the specific operation state according to the contents set in the register means. 3. The computer device according to claim 2, wherein the computer device is capable of performing. 6. A computer device in which a CPU, a bus, and a bus control means having a bus arbitration function are integrated in one chip, wherein a lapse of a priority time for securing a bus priority of the CPU for a predetermined time. When the bus control means receives a request for the right to use the bus from the external bus master means, when the timer means recognizes that the priority time has not passed, The C
A computer device having means for securing a bus priority of a PU and suspending a bus use right of the external bus master means. 7. A bus control method applied to a computer device in which a CPU, a bus, and a bus control means having a bus arbitration function are integrated in one chip, wherein the bus control means comprises a bus from the CPU. CPU in response to a request for usage right
Giving a bus priority to the CPU, setting a priority time for securing the bus priority of the CPU for a predetermined time in the timer means, and receiving a bus use right request from an external bus master means, A process is executed which comprises a step of determining whether or not the priority time has elapsed before the timer means has elapsed, and a step of holding the bus use right of the external bus master means if the priority time has not elapsed. A bus control method characterized by the above-mentioned. 8. A computer device in which a CPU, a bus, and a bus control means having a bus arbitration function are integrated in one chip, the computer device having an interrupt control means for controlling external or internal interrupt processing. The bus control means, upon receiving a bus use right request from the external bus master means, secures the bus priority of the CPU during interrupt processing according to a control signal from the interrupt control means, and Computer means having means for reserving the right to use the bus from the means. 9. A bus control means, comprising: register means for setting, when an interrupt signal is output from the interrupt control means, information for instructing the external bus master means to reserve the right to use the bus. When receiving a request for the right to use the bus from the external bus master means, the CPU secures the bus priority of the CPU at the time of interrupt processing based on the information set in the register means, and 9. The computer device according to claim 8, wherein the right is reserved. 10. A bus control method applied to a computer device in which a CPU, a bus, a bus control means having a bus arbitration function, and an interrupt control means for controlling interrupt processing are integrated in one chip. The bus control means has register means for setting information for instructing to suspend the right to use the bus of the external bus master means when an interrupt signal is output from the interrupt control means, CPU in response to a request for the right to use the bus from
Assigning a bus priority to the timer means when the interrupt signal is output from the interrupt control means, and setting a priority time for securing the bus priority of the CPU for a predetermined time in the timer means; Determining whether to secure the bus priority of the CPU at the time of interrupt processing based on the information set in the register means when receiving the request for the bus use right from the CPU; A bus control method for reserving the right to use the bus from the external bus master means. 11. A computer device in which a CPU, a bus, and a bus control means having a bus arbitration function are integrated in one chip, wherein an external bus master means is included in a bus priority according to an internal operation of the CPU. Priority setting means for setting a bus priority including the bus priority of the bus control means. The bus control means, when receiving a request for a bus use right from an external bus master means, When the bus priority of the external bus master means is relatively low based on the bus priority set by the
A means for securing bus priority according to the internal operation of the computer. 12. A register unit for changing a bus priority of the external bus master unit, wherein the priority setting unit refers to the register unit and sets a bus priority according to an internal operation of the CPU. 12. The computer device according to claim 11, further comprising means for setting a bus priority of said external bus master means. 13. A CPU, a bus, a bus control means having a bus arbitration function, and a bus priority including a bus priority of an external bus master means in a bus priority according to an internal operation of the CPU. Control method applied to a computer device in which priority order setting means is integrated in one chip, wherein the bus control means, upon receiving a bus use request from an external bus master means, Determining from the order setting means the relative priority of the external bus master means with respect to the bus priority according to the internal operation of the CPU; and, if the external bus master means has a relatively low bus priority, the external bus master means And a step of suspending the right to use the bus from the server. 14. A computer device in which a CPU, a bus, and a bus control means having a bus arbitration function are integrated in a single chip, wherein a bus priority according to an internal operation of the CPU is determined by an external device. A priority setting means for setting a bus priority including a bus priority; and means for notifying the external device of the bus priority set by the priority setting means. Receiving a bus use request from the external device, when the bus priority of the external device is relatively low based on the bus priority set by the priority setting means, A means for suspending the right to use the bus and securing a bus priority according to the internal operation of the CPU. Place. 15. The priority setting means has means for receiving a bus request from a plurality of external bus master means, and includes a bus priority of the plurality of external bus master means in a bus priority according to an internal operation of the CPU. The computer device according to claim 11, wherein a bus priority including the priority is set. 16. A register for changing a bus priority of the plurality of external bus masters, wherein the priority setting means refers to the register and controls a bus priority according to an internal operation of the CPU. 16. The computer device according to claim 15, wherein bus priorities of said plurality of external bus master means are set in the order.