JPH11145802A - Clock generation circuit - Google Patents

Abstract

(57) [Problem] To provide a clock generation circuit whose frequency and phase change. An oscillator circuit for generating a reference clock,
The reference clock CK generated by the oscillation circuit is divided by a predetermined dividing ratio of 1
A frequency dividing circuit 2 that outputs a first frequency-divided clock CLK1 frequency-divided by / n and outputs a second frequency-divided clock CLK2 obtained by dividing the reference clock by a frequency division ratio of 1 / (2n); And a phase control circuit 4 for detecting the rising edge of the divided clock signal and outputting negative count enable signals ENP1 and ENP2 to the frequency dividing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock generation circuit for generating a divided clock by dividing a reference clock.

[0002]

2. Description of the Related Art Generally, digital circuits such as CPUs operate in synchronization with a clock, and require a clock generation circuit.

FIG. 5 is a circuit diagram showing a conventional clock generation circuit. In FIG. 5, reference numeral 1 denotes an oscillation circuit that generates a reference clock, and 2 denotes a reference clock generated by the oscillation circuit 1.
A frequency dividing circuit for dividing by / 4, a digital circuit 3 such as a CPU driven by a frequency-divided clock output from the frequency dividing circuit 2, a CMOS inverter 11, and a crystal oscillator 12. In FIG. 5, the oscillation circuit 1 and the frequency dividing circuit 2 constitute a clock generating circuit.

The operation of the clock generation circuit configured as described above will be described with reference to FIG. FIG.
6A is a timing chart showing an oscillation clock (reference clock) CK output from the oscillation circuit 1, and FIG. 6B is a timing showing a １ ／ frequency clock CLK of the reference clock output from the frequency divider 2. FIG.

The oscillation circuit 1 has a CMOS inverter 11 and a crystal oscillator 12, and has a stable reference clock C
Output K. The reference clock CK output from the oscillation circuit 1 is input to the terminal CK of the frequency dividing circuit 2, and becomes a frequency-divided clock CLK that is frequency-divided by 1/4 as shown in FIG. The frequency-divided clock CLK output from the terminal Q1 is input to the terminal CLK of the digital circuit 3.

[0006]

However, in the above-described conventional clock generation circuit, a clock having a constant frequency and phase is generated. Therefore, the operation noise of a digital circuit operating in synchronization with this clock also has a frequency and a phase. Is always constant. Accordingly, there has been a problem that the frequency spectrum of the operation noise of the digital circuit is also stabilized, and a standing wave is generated in a pattern on a substrate, a cable, or the like, thereby generating radiation noise. In order to reduce this radiation noise, expensive unnecessary radiation suppression components such as a filter and a ferrite core are required.

In this clock generation circuit, the frequency and phase of the generated clock are changed to prevent a standing wave from being generated on a board pattern, a cable, and the like, thereby preventing generation of radiation noise. Is required.

An object of the present invention is to provide a clock generation circuit whose frequency and phase change.

[0009]

In order to solve the above-mentioned problems, a clock generation circuit according to the present invention comprises an oscillation circuit for generating a reference clock and a reference clock generated by the oscillation circuit at a predetermined dividing ratio of 1 / n. A frequency divider circuit for outputting a frequency-divided first frequency-divided clock and outputting a second frequency-divided clock obtained by frequency-dividing the reference clock by a frequency division ratio of 1 / (2n), and a rise of the second frequency-divided clock A phase control circuit for detecting an edge and outputting a negative count enable signal to the frequency dividing circuit.

Thus, a clock generation circuit whose frequency and phase change can be obtained.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to a first aspect of the present invention is directed to an oscillation circuit for generating a reference clock and a first clock obtained by dividing the reference clock generated by the oscillation circuit by a predetermined frequency division ratio of 1 / n. A frequency dividing circuit for outputting a second divided clock obtained by dividing the reference clock by a dividing ratio of 1 / (2n), and detecting a rising edge of the second divided clock. A phase control circuit for outputting a negative count enable signal to the frequency dividing circuit, wherein the frequency dividing circuit does not count the reference clock when the negative count enable signal is generated. Having.

According to a second aspect of the present invention, an oscillation circuit for generating a reference clock and a first frequency-divided clock obtained by dividing the reference clock generated by the oscillation circuit by a predetermined frequency division ratio of 1 / n are output. A frequency divider that outputs a second frequency-divided clock obtained by dividing the reference clock by a frequency division ratio of 1 / (2n);
And a frequency control resistor for feeding back the second divided clock to the oscillation circuit, which is disposed between the output terminal of the divided clock and the oscillation circuit. This has the effect that the frequency of the reference clock changes according to the level of the peripheral clock.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. (First Embodiment) FIG. 1 is a circuit diagram showing a clock generation circuit according to a first embodiment of the present invention. In FIG.
The oscillating circuit 1, the frequency dividing circuit 2, the digital circuit 3, the CMOS inverter 11, and the crystal oscillator 12 are the same as those shown in FIG. Reference numeral 4 denotes a phase control circuit that detects a rising edge of the divided clock and outputs a negative count enable signal to the frequency dividing circuit 2.
In FIG. 1, the oscillation circuit 1, the frequency dividing circuit 2, and the phase controlling circuit 4 constitute a clock generating circuit. That is, the portion excluding the digital circuit 3 is the clock generation circuit.

The operation of the clock generation circuit configured as described above will be described with reference to FIG. FIG.
2A is a timing chart showing an oscillation clock (reference clock) CK output from the oscillation circuit 1, and FIG. 2B shows a first frequency-divided clock CLK1 which is a quarter frequency clock of the reference clock CK. The timing diagram, FIG.
FIG. 2 is a timing chart showing a second frequency-divided clock CLK2 that is a 1/2 frequency-divided clock of the frequency-divided clock CLK1 of FIG.
(D) is a timing chart showing the count enable signal enp obtained by detecting the rising edge of the second frequency-divided clock CLK2.

The oscillation circuit 1 has a CMOS inverter 11 and a crystal oscillator 12, and has a stable reference clock C
K (see FIG. 2A) is output. The reference clock CK output from the oscillation circuit 1 is input to a terminal CK of the frequency dividing circuit 2 and is a frequency-divided clock (first frequency-divided clock) divided by a quarter as shown in FIG. CLK1 is output from the terminal Q1. The first frequency-divided clock CLK1 output from the terminal Q1 is input to the terminal CLK of the digital circuit 3. On the other hand, a second frequency-divided clock CLK2 (see FIG. 2C) obtained by dividing the first frequency-divided clock CLK1 by １ ／ is output from the terminal Q2 of the frequency-divider circuit 2. The second frequency-divided clock CLK2 is input to the phase control circuit 4, which detects a rising edge of the second frequency-divided clock CLK2 as shown in FIG. The generated count enable signal enp is output to the terminal ENP of the frequency dividing circuit 2. This count enable signal enp is a negative count enable signal ENP at the rising portion of the second divided clock CLK2.
1, ENP2, and the negative count enable signals ENP1, ENP2 inhibit the counting of the reference clock CK in the frequency dividing circuit 2. Accordingly, while the negative count enable signals ENP1 and ENP2 are being generated, the reference clocks P1 and P2 (see FIG. 2A) are ignored, the frequency divider 2 is in a state where counting is stopped, and the first division is performed. The low period of the peripheral clock CLK1 becomes longer by one clock. Accordingly, the periodicity of the first frequency-divided clock CLK1 is lost, and the periodicity of the operation noise of the digital circuit is also lost.
Accordingly, the frequency spectrum of the operation noise is also dispersed, and the peak value decreases.

What should be considered here is the processing capability of the CPU. That is, the processing capability of the CPU may be determined by the clock frequency. In this case, if the clock frequency is low, the processing capability of the CPU is reduced. As shown in FIG. 2B, the first frequency-divided clock CLK1 changes to a low frequency, and at this time, the processing capability of the CPU is reduced. However, in general, high processing power is required of the CPU during a specific process, and usually, less processing power is required. If a slow clock is inserted only when the processing capability is not required, the operation noise of the digital circuit 3 including the CPU and the like can be reduced without any problem in the processing capability.

In the present embodiment, the frequency control signal is generated using the second frequency-divided clock CLK2 output from the frequency dividing circuit 2. However, the same applies to the case where the signal from the digital circuit 3 is used. And a random signal may be generated. Also, the first divided clock C
Although the frequency division ratio of LK1 is 1/4, it is 1/2, 1/3, 1
A division ratio such as / 5, 1/8, etc. can be handled by the same configuration.

As described above, according to the present embodiment, the first clock obtained by dividing the reference clock CK by the dividing ratio 1 / n (n = 4) is used.
Frequency division ratio 1 / (2n) of 1/2 of frequency-divided clock CLK1
The rising edge of the second frequency-divided clock CLK2 divided by the above is detected and the negative count enable signal ENP1,
By outputting ENP2 from phase control circuit 4 to frequency dividing circuit 2, negative count enable signal E is output.
When NP1 and ENP2 are generated, the frequency of the first frequency-divided clock CLK1 is reduced, that is, the frequency of the first frequency-divided clock CLK1 is reduced. CLK1
Frequency and phase can be changed. Therefore, it is possible to disperse the frequency spectrum of the operation noise of the digital circuit such as the CPU, suppress the generation of the standing wave in the pattern of the board, the cable, and the like, and reduce the radiation noise.

(Embodiment 2) FIG. 3 is a circuit diagram showing a clock generation circuit according to Embodiment 2 of the present invention. 3, the oscillation circuit 1, the frequency divider 2, the digital circuit 3, the CMOS inverter 11, and the crystal oscillator 12 are the same as those in FIG.
5 is disposed between the output terminal Q2 of the second frequency-divided clock CLK2 and the oscillation circuit 1, and the second frequency-divided clock CLK2
Is a frequency control resistor for feeding back to the oscillation circuit 1. In FIG. 3, the oscillation circuit 1, the frequency dividing circuit 2, and the frequency controlling resistor 5 constitute a clock generating circuit. That is, the portion excluding the digital circuit 3 is the clock generation circuit.

The operation of the clock generation circuit configured as described above will be described with reference to FIG. FIG.
4A is a timing chart showing an oscillation clock (reference clock) CK output from the oscillation circuit 1, and FIG. 4B is a timing showing a first frequency-divided clock CLK1, which is a quarter frequency clock of the reference clock. FIG. 4C is a timing chart showing a second frequency-divided clock CLK2 which is a half frequency-divided clock of the first frequency-divided clock CKL1.

The oscillation circuit 1 has a CMOS inverter 11 and a crystal oscillator 12, and receives a reference clock CK (FIG. 4A).
Output). The reference clock CK output from the oscillation circuit 1 is input to a terminal CK of the frequency divider 2 and
As shown in (b), the frequency-divided clock (first frequency-divided clock) CLK1 that has been frequency-divided by 1/4 is output from the terminal Q1. First frequency-divided clock C output from terminal Q1
LK1 is input to the terminal CLK of the digital circuit 3. On the other hand, from the terminal Q2 of the frequency dividing circuit 2, the second frequency-divided clock CLK2 obtained by dividing the first frequency-divided clock CLK1 by １ ／
(See FIG. 4C) is output. The second frequency-divided clock CLK2 repeats high and low levels. This level change is fed back to the oscillation circuit 1 through the frequency control resistor 5, and the oscillation circuit 1 generates a reference clock having a frequency corresponding to the fed-back level. Outputs CK. That is, as shown in FIG. 4A, the frequency of the reference clock CK changes between when the second frequency-divided clock CLK2 is low and when it is high, and the periods T1 and T2 shown in FIG.
As shown by 2, the frequency of the first divided clock CLK1 also changes. If the frequency of the first frequency-divided clock CLK1 changes, the periodicity of the operation noise of the digital circuit also breaks down,
The frequency spectrum of the operating noise is also dispersed, and the peak value decreases.

In the present embodiment, the frequency control signal is generated using the second frequency-divided clock CLK2 output from the frequency divider 2, but the frequency control signal is generated using the signal from the digital circuit 3. And a random signal may be generated. Also, the first divided clock C
Although the frequency division ratio of LK1 is 1/4, it is 1/2, 1/3, 1
A division ratio such as / 5, 1/8, etc. can be handled by the same configuration.

As described above, according to the present embodiment, the first divided clock CL divided by the division ratio 1 / n (n = 4) is used.
A frequency control resistor 5 is arranged between the output terminal Q2 of the second frequency-divided clock CLK2 divided by a frequency division ratio of 1/2 of K1 and 1 / (2n) and the oscillation circuit 1, and By feeding back the divided clock CLK2 to the oscillation circuit 1, the frequency of the reference clock CK changes between when the second divided clock CLK2 is low and when it is high,
The frequency of the first frequency-divided clock CLK1 also changes. First
If the frequency of the divided clock CLK1 changes, the CPU
And the like, the periodicity of the operation noise of the digital circuit is broken, the spectrum of the operation noise is also dispersed, and the peak value is reduced. That is, the frequency spectrum of the operation noise of the digital circuit such as the CPU is dispersed, the generation of the standing wave in the pattern of the substrate, the cable, or the like is suppressed, and the radiation noise can be reduced.

[0024]

As described above, according to the clock generation circuit of the first aspect of the present invention, the oscillation circuit for generating the reference clock and the reference clock generated by the oscillation circuit are divided by a predetermined dividing ratio of 1 / n. And outputs the first frequency-divided clock obtained by dividing the reference clock by the frequency division ratio 1 / (2n).
A frequency dividing circuit that outputs a divided clock of the second divided clock, and a phase control circuit that detects a rising edge of the second divided clock and outputs a negative count enable signal to the frequency dividing circuit, thereby providing a negative count. When the enable signal is generated, the frequency divider circuit can be configured not to count the reference clock, so that the frequency and phase of the first frequency-divided clock can be changed. An advantageous effect is obtained in that the frequency spectrum of the operation noise of the circuit is dispersed, the generation of standing waves in the pattern of the substrate, the cable, or the like is suppressed, and the radiation noise can be reduced.

According to the second aspect of the present invention, the oscillation circuit for generating the reference clock and the first frequency-divided clock obtained by dividing the reference clock generated by the oscillation circuit at a predetermined frequency division ratio of 1 / n are used. Is output and the reference clock is divided by the division ratio 1 / (2
a frequency divider for outputting the second frequency-divided clock divided in step n), and a frequency divider disposed between the output terminal of the second frequency-divided clock and the oscillator, and feeding back the second frequency-divided clock to the oscillator; A frequency control resistor for changing the frequency of the reference clock and changing the frequency of the first frequency-divided clock when the second frequency-divided clock is low and high. By changing the frequency of the first frequency-divided clock, the frequency spectrum of the operating noise of the digital circuit such as the CPU is dispersed, and the occurrence of standing waves in the pattern, cable, etc. of the board is suppressed. An advantageous effect that radiation noise can be reduced can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a clock generation circuit according to a first embodiment of the present invention.

2A is a timing chart showing a reference clock output from an oscillation circuit. FIG. 2B is a timing chart showing a first divided clock. FIG. 2C is a timing chart showing a second divided clock. Diagram showing a count enable signal obtained by detecting a rising edge of a divided clock signal of FIG.

FIG. 3 is a circuit diagram showing a clock generation circuit according to a second embodiment of the present invention.

4A is a timing chart showing a reference clock output from an oscillation circuit. FIG. 4B is a timing chart showing a first divided clock. FIG. 4C is a timing chart showing a second divided clock.

FIG. 5 is a circuit diagram showing a conventional clock generation circuit.

6A is a timing chart showing a reference clock output from an oscillation circuit. FIG. 6B is a timing chart showing a 1/4 frequency-divided clock of the reference clock output from a frequency dividing circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Oscillation circuit 2 Divider circuit 3 Digital circuit 4 Phase control circuit 5 Frequency control resistor 11 CMOS inverter 12 Crystal oscillator

Claims (2)

[Claims] An oscillation circuit for generating a reference clock, and a reference frequency generated by the oscillation circuit is divided by a predetermined dividing ratio of 1 / n.
A frequency divider that outputs a first frequency-divided clock obtained by dividing the frequency of the reference clock and a second frequency-divided clock obtained by dividing the reference clock by a frequency division ratio of 1 / (2n); A phase control circuit for detecting a rising edge of the clock and outputting a negative count enable signal to the frequency dividing circuit. 2. An oscillation circuit for generating a reference clock, and a reference frequency generated by the oscillation circuit is divided by a predetermined dividing ratio of 1 / n.
A frequency divider that outputs a first frequency-divided clock obtained by dividing the frequency of the reference clock and a second frequency-divided clock obtained by dividing the reference clock by a frequency division ratio of 1 / (2n); A clock generation circuit, comprising: a frequency control resistor disposed between a clock output terminal and the oscillation circuit for feeding back the second divided clock to the oscillation circuit.