JPH11148965A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily test an operation when being mounted on the circuit board of an integrated circuit without using any expensive LSI tester. SOLUTION: An integrated circuit device 1 based on a first embodiment is provided with an internal circuit 11, input signal control circuits A1, A2,..., An for controlling an input signal for the internal circuit 11, output signal control circuits B1, B2,..., Bn for controlling a signal being outputted from the internal circuit 11, and a multiplexer 12 for generating an operation mode control signal that controls operation by the input signal control circuits A1, A2,..., An and the output signal control circuits B1, B2,..., Bn. An input signal is inputted to the input signal control circuits A1, A2,..., An via an input terminal 6. Also, an output signal is outputted from the output signal control circuits B1, B2,..., and Bn via an output terminal 5. The multiplexer 12 multiplexes selected signals being inputted to an input terminal 13 and select one of transistors being connected to G1 and G2 terminals of the input signal control circuits A1, A2,..., An and the output signal control circuits B1, B2,..., Bn and generates an activated operation mode control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to an LSI (integrated circuit),
In particular, the present invention relates to an LSI incorporating a circuit that supports an operation test required when the LSI is mounted on an application circuit.

2. Description of the Related Art In recent years, LSI (Large Scale Integratio)
n), integrated circuits such as VLSI (Very Large Scale Integration) are becoming smaller and more highly integrated. As the scale of integration of an integrated circuit increases, the number of signal input / output terminals increases, and the distance between the terminals of the package decreases. An LSI tester is usually used to test the operation of the mounted integrated circuit on a printed wiring board or the like on which the integrated circuit is mounted in a product inspection stage. An operation test method for a conventional multi-pin integrated circuit device using an LSI tester will be described below. FIG. 1 shows a conventional test method of a device mounting an integrated circuit. In FIG. 1, reference numerals 41 and 42 denote input terminals of an integrated circuit;
44 is an output terminal. 45 is an LSI tester, L
The SI tester is connected to terminals of an integrated circuit to be tested by probes 47 and 48. The operation of a test method of an integrated circuit device using the LSI tester configured as described above will be described below. First, LSI
A test signal is generated by a test signal generator 45 a of the tester 45, and the generated test signal is output to the input terminal 41 of the integrated circuit 46 through the probe 41. Integrated circuit 4
In step 6, the output signal corresponding to the input test signal is input to the test result signal reference section 45b of the LSI tester 45 via the probe 48 provided on the output terminal 43 side. The LSI tester 45 refers to a test result prediction signal and a test result signal prepared for the test signal to determine whether the results match, and determines whether the integrated circuit is operating normally.

However, in the above-described test method using the LSI tester, the distance between pins is narrow due to the high integration of the integrated circuit, and the probe used for inputting / outputting signals from the LSI tester is installed on each pin of the LSI. Was difficult. In addition, there is a possibility that another pin may come into contact with the probe when the probe is installed, which causes a problem such as malfunction. Also, the LSI tester is very expensive, and the burden of purchasing the device maker is very large. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide an integrated circuit capable of easily testing the operation of the integrated circuit without using an expensive LSI tester.

In order to achieve the above object, an integrated circuit according to the present invention has the following arrangement. That is,
An integrated circuit comprising auxiliary means for assisting a test of a logic level of an input / output terminal of the integrated circuit, wherein said auxiliary means includes:
Driving means for driving the input / output terminal to a predetermined logical level by disabling driving from the other driving means, and specifying means for specifying a driving logical level of the driving means.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment An embodiment of the present invention will be described below in detail with reference to the drawings. In FIG. 2, 1 is an integrated circuit device of the present invention, 11 is an internal circuit in the integrated circuit device,
12 is a multiplexer, 13 is a control signal input terminal, A
1, A2,. . An is an input signal control circuit, B1, B
2,. . Bn is an output signal control circuit. The operation of the integrated circuit device configured as described above will be described with reference to FIGS. The integrated circuit device 1 according to the first embodiment includes an internal circuit 11, input signal control circuits A1, A2,. .
An, output signal control circuits B1, B2,. . Bn, input signal control circuits A1, A2,. . An and output signal control circuits B1, B
2,. . A multiplexer 12 for generating an operation mode control signal for controlling the operation in Bn is provided. The input signals are supplied to input signal control circuits A1, A2,. . A
n. The output signals are output via output terminals 5 to output signal control circuits B1, B2,. . Output from Bn. The multiplexer 12 multiplexes the selection signal input to the input terminal 13 to generate an input signal control circuit A
1, A2,. . An, output signal control circuits B1, B
2,. . An operation mode control signal for selecting and activating one of the transistors connected to the G1 and G2 terminals of Bn is generated. FIG. 3 shows these input signal control circuits A1,
A2,. . An example of a specific circuit configuration of An is shown.
Here, X1 is connected to the input terminal 6 of the integrated circuit device 1. Output Y1 of buffer B1 is connected to internal circuit 11 (FIG. 2). A pull-up / pull-down circuit P1 composed of current limiting resistors R1, R2 and MOS transistors TR1, TR2 controls the voltage level of input terminal X1 based on gate input signals G1, G2 input to the gates of transistors TR1, TR2. I do. Current limiting resistor R1
Is connected to a high-level power supply voltage line. When the transistor TR1 is turned on, a predetermined amount of current flows to the source / drain of the transistor TR1 via the current limiting resistor R1, and the input level of the buffer B1 is changed to a high-level voltage. Pull up. On the other hand, the source of the transistor TR2 is connected to a low-level power supply voltage line, and when the transistor TR2 is turned on, the input level of the buffer B1 is reduced to a low-level voltage. The transistors TR1 and TR2
Input the gate input signals G1 and G2 so as to operate exclusively. When any one of the transistors TR1 and TR2 is driven to be active, the input terminal X1 needs to be controlled to be in a high impedance state. An external circuit (not shown) connected to X1 needs to have a function of making input terminal X1 high impedance. Next, referring to FIG. 4, input signal control circuits A1, A2,. . Another circuit configuration example of An is shown. Here, the output Y41 of the buffer B41 is connected to the internal circuit 11 (FIG. 2). The input terminal X41 is connected to the input terminal 6 of the integrated circuit 1 in FIG. A dynamic memory is constituted by a combination of the transistor TR41 and the capacitor C41. When a signal for activating the transistor TR41 is input from the multiplexer 12 to the gate G1 of the transistor TR41, the capacitor C41 is charged or discharged via the current limiting resistor R41 and the transistor 41 in accordance with the voltage level of the input terminal X41. When a signal of a level for inactivating the transistor TR41 is input from the multiplexer 12 to the gate G1 of the transistor TR41, the transistor TR41 is inactivated, and the capacitor C41 has a memory function of maintaining the voltage level as a result of charging / discharging. Have.
Therefore, by activating the transistor TR41 and applying a high-level or low-level voltage to the input terminal X41 from an external circuit (not shown) connected to the input terminal X41, the charge having the corresponding voltage level is changed to the capacitor C41.
Charge / discharge. Thereafter, if the external circuit (not shown) controls the gate G1 via the multiplexer 12 so that the input terminal X41 becomes high impedance, the level of the input terminal X41 is controlled by turning on the transistor TR41. Potential. In the case of this configuration example, it goes without saying that the control signal from the multiplexer 12 may be one for the gate G1. In the example shown in FIG. 4, the dynamic memory is configured by charging and discharging the capacitor. However, it is needless to say that a static memory may be configured. Next, referring to FIG. 5, output signal control circuits B1, B2,. . Bn shows an example of a common circuit configuration. Input terminal X50 is connected to an output terminal from internal circuit 11. Output terminal Y50 is output terminal 5 of integrated circuit 1 (FIG. 2).
Connected to. The gate G3 of the transistor TR50 and the gate G4 of the transistor TR51 are connected to the output of the multiplexer 12, respectively. Tristate control terminal Z1 of tristate buffer B50 is connected to control terminal 100 of integrated circuit 1 (FIG. 2). Tristate buffer B50 controls whether to transmit a signal output from internal circuit 11 (FIG. 2) to output terminal Y50 according to a control signal input to tristate control terminal Z1. This allows the pull-up / down circuit P50
It is possible to select whether to give priority to the output from the input terminal or to give priority to the signal input from the input terminal 50. Current limiting resistors R50, R51, MOS transistors TR50, TR
51, the pull-up / pull-down circuit P50 changes the voltage level of the output terminal Y50 to the transistors TR50,
Control is performed based on signals G3 and G4 input to the gate of TR51 from the multiplexer 12 (FIG. 2). One end of the current limiting resistor R50 is connected to a high-level power supply voltage line. When the transistor TR50 is turned on, a predetermined amount of current flows to the source / drain of the transistor TR50 via the current limiting resistor R50, and the output terminal Y50 is set to a high level. Increase to voltage. On the other hand, the source of the transistor TR51 is connected to a low-level power supply voltage line, and when the transistor TR51 is turned on, the output terminal Y50 is lowered to a low-level voltage. The transistors TR50, TR5
The gate input signals G3 and G4 are input so that 1 is exclusively turned on or both are turned off. Needless to say, when one of the transistors TR50 and TR51 is driven to be turned on, the tristate buffer B50 needs to be controlled so as to cut off the input from the input terminal X50. Second Embodiment Next, FIG. 6 shows a second embodiment according to the present invention.
1 shows an integrated circuit device 2 according to the embodiment. The difference between the integrated circuit device 2 of FIG. 6 and the integrated circuit device 1 of the first embodiment is that the input signal control circuits A1, A2,. .
An and output signal control circuits B1, B2,. . Bn has a different circuit configuration, and further has input signal control circuits A1 and A1.
2,. . An and output signal control circuits B1, B2,. . Bn
In that the number of control inputs for controlling each of the above has increased. Hereinafter, with reference to FIG. 6, a description will be given of components different from those of FIG. The selection circuit 30 decodes the selection signal input from the input terminal 31 and outputs the selected signal to the input signal control circuit C.
1, C2,. . Cn and output signal control circuits D1, D
2,. . A signal for selecting one of Dn is generated.
According to the outputs from the multiplexer 12 and the selection circuit 30, the input signal control circuits C1, C2,. . Cn and the output signal control circuits D1, D2,. . The operation of Dn will be determined. Next, referring to FIG. 7, the input signal control circuit C
1, C2,. . An example of each circuit configuration of Cn will be described. Here, X7 is the input terminal 2 of the integrated circuit device 2 (FIG. 6).
00 is connected. Output terminal Y7 is connected to internal circuit 11 (FIG. 6). A pull-up comprising current limiting resistors R7, R8 and MOS transistors TR70, TR71
The pull-down circuit P70 controls the voltage level of the output terminal Y7 based on the gate input signals G5 and G6 input to the gates of the transistors TR70 and TR71. One end of the current limiting resistor R7 is connected to a high-level power supply voltage line, and when the transistor TR70 is turned on, a predetermined amount of current flows through the transistor TR70 via the current limiting resistor R7.
And the output terminal Y7 is pulled up to a high level voltage. On the other hand, the source of the transistor TR71 is connected to a low-level power supply voltage line, and when the transistor TR71 turns on, the output terminal Y7 is lowered to a low-level voltage. The transistors TR70 and TR71
Are turned on exclusively, or gate input signals G5 and G6 are input so that both are turned off. It is needless to say that the tri-state control input terminal Z3 of the buffer B70 needs to be controlled so as to cut off the output of the buffer B70 when any one of the transistors TR70 and TR71 is driven to be turned on. By arranging the buffer B70 on the input terminal X7 side, an output from a circuit connected to the outside of the integrated circuit 2 (FIG. 6) is cut off, and a signal of a specific level is given to the internal circuit 11. Testing can be facilitated. Third Embodiment In the third embodiment, another configuration example of the input signal control circuit shown in FIG. 3 will be described. The main difference from the configuration of FIG. 3 is that the flip-flop FF1 maintains the pull-up / pull-down level in the configuration of FIG. Therefore, this configuration eliminates the need for a circuit configuration that externally holds the level. Note that, in the circuit configuration of FIG. 3, similar components are denoted by the same reference numerals. FIG.
The circuit configuration will be described below with reference to FIG. X1 is connected to the input terminal 6 of the integrated circuit device 1. Output Y1 of buffer B1 is connected to internal circuit 11 (FIG. 2). The flip-flop FF1 latches the input logic level from the control terminal 100 (FIG. 2) at the timing when the selection signal G2 is input from the multiplexer 12. The latched output is output from the Q output terminal of the flip-flop FF1, and is input to the tri-state buffer B10. Then, when the selection signal from the multiplexer 12 is input, a logic level signal equal to the input logic level from the flip-flop FF1 is output to the line X1 via the current limiting resistor R50. Although FIG. 8 shows an example of the configuration of the input signal control circuit, it goes without saying that the flip-flop FF1 holding this logic level may be applied to the output signal control circuit. Although the transistors in the input signal control circuit and the output signal control circuit described above are field effect transistors, it goes without saying that they may be bipolar transistors. By using the integrated circuits of the embodiments described above, the operation when mounted on the circuit board of the integrated circuit can be easily tested without using an expensive LSI tester.

By using the integrated circuits of the embodiments described above, the operation when mounted on a circuit board of the integrated circuit can be easily tested without using an expensive LSI tester.

[Brief description of the drawings]

FIG. 1 is a diagram showing a test configuration of a conventional integrated circuit.

FIG. 2 is a diagram illustrating a configuration of an integrated circuit according to a first embodiment.

FIG. 3 is a diagram illustrating a configuration of an input control circuit according to the first embodiment.

FIG. 4 is a diagram illustrating a configuration of another input control circuit according to the first embodiment.

FIG. 5 is a diagram illustrating a configuration of an output control circuit according to the first embodiment.

FIG. 6 is a diagram illustrating a configuration of an integrated circuit according to a second embodiment;

FIG. 7 is a diagram illustrating a configuration of an input control circuit according to a second embodiment;

FIG. 8 is a diagram illustrating a configuration of an input control circuit according to a third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Integrated circuit device 11 Internal circuit 12 Multiplexer 13 Control signal input terminal 31 Integrated circuit device

Claims (6)

[Claims] 1. An integrated circuit comprising auxiliary means for assisting a test of a logic level of an input / output terminal of an integrated circuit. An integrated circuit, comprising: a driving unit that drives to a logical level of the following; and a specifying unit that specifies a driving logical level of the driving unit. 2. The device according to claim 1, wherein said driving means includes a first transistor for driving said input / output terminal to a high logic level and a second transistor for driving said input / output terminal to a low logic level. 2. The integrated circuit according to 1. 3. The integrated circuit according to claim 2, wherein a current limiting resistor is connected to one of a source and a drain of the first and second transistors. 4. The integrated circuit according to claim 2, wherein said driving means further comprises holding means for holding a desired driving level. 5. The integrated circuit according to claim 4, wherein said holding means comprises a dynamic memory cell. 6. The method according to claim 1, wherein the specifying unit is configured to perform the first or second
2. The integrated circuit according to claim 1, further comprising: a multiplexer that outputs a control signal for turning on said transistor.