JPH11150242A - Semiconductor integrated circuit device having DRAM and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a highly reliable DRAM which can be manufactured by a simple manufacturing process and a method of manufacturing the same. Kind Code: A1 A DRAM in which a voltage of a difference between a word line voltage and a bit line voltage (the lowest voltage of a bit line) in a memory array is equal to a voltage of a power supply line of a peripheral circuit of the memory array. . This DRAM does not have a circuit for changing a power supply voltage in a peripheral circuit area, and a MOSFET constituting a memory array is provided on a surface of a semiconductor substrate 1.
Of the gate insulating film 4 and the MOSF forming the peripheral circuit
The gate insulating film 4 of the MOSFET forming the memory array and the gate insulating film 4 of the MOSFET forming the peripheral circuit are formed by the same process with the same thickness of the gate insulating film 4 of the ET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynami
More particularly, the present invention relates to a semiconductor integrated circuit device having a highly reliable DRAM which can be manufactured by a simple manufacturing process and a method of manufacturing the same.

[0002]

2. Description of the Related Art The present inventors have studied a semiconductor integrated circuit device having a DRAM. The following is a technique studied by the present inventors, and the outline is as follows.

That is, in a method of manufacturing a semiconductor integrated circuit device having a DRAM, an M
After forming an OSFET and a MOSFET constituting a peripheral circuit thereof on a semiconductor substrate, a multilayer wiring layer is formed on the semiconductor substrate.

As a document describing a method of manufacturing a semiconductor integrated circuit device having a DRAM, there is a document described in, for example, Japanese Patent Application Laid-Open No. 3-214669.

[0005]

However, the aforementioned D
In a semiconductor integrated circuit device having a RAM, a word line in a memory array has a high voltage (a voltage of about 3.4 V).
Since the power supply line of the peripheral circuit uses a low voltage (a voltage of about 2.5 V) different from the voltage of the word line, the thickness of the gate insulating film of the MOSFET constituting the memory array is Since the thickness of the gate insulating film of the MOSFET constituting the peripheral circuit is larger (larger) than that of the MOSFET, the gate insulating film of the MOSFET constituting the memory array (for example, a two-layer gate insulating film made of a silicon oxide film or the like). The manufacturing process for forming a film (film) and the process for forming a gate insulating film (for example, a single-layered gate insulating film made of a silicon oxide film) of a MOSFET constituting a peripheral circuit are different from each other.

Therefore, the MO that constitutes the memory array
There is a problem that the manufacturing process for forming the gate insulating film of the SFET and the process for forming the gate insulating film of the MOSFET constituting the peripheral circuit are different from each other, which complicates the manufacturing process. .

Since the voltage of the word line in the memory array is different from the voltage of the power supply line of the peripheral circuit, a power supply generating the same voltage as the voltage of the word line in the memory array is used for the power supply line of the peripheral circuit. To do
It is necessary to form a circuit for changing the voltage to the voltage of the power supply line of the peripheral circuit by making the voltage the same as the voltage of the power supply line of the peripheral circuit, thereby complicating the circuit configuration of the peripheral circuit. There is a point.

Furthermore, a MOSF forming a memory array
When the gate insulating film of the ET is formed, the thickness of the gate insulating film is formed to be larger than the thickness of the gate insulating film of the MOSFET constituting the peripheral circuit, so that the gate insulating film of the MOSFET constituting the memory array is formed. There is a problem that reliability is reduced.

An object of the present invention is to provide a semiconductor integrated circuit device having a highly reliable DRAM which can be manufactured by a simple manufacturing process, and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device having the DRAM of the present invention, the voltage of the difference between the word line voltage and the bit line voltage in the memory array and the voltage of the power supply line of the peripheral circuit of the memory array are the same. Is what is being done.

Further, according to the method of manufacturing a semiconductor integrated circuit device having a DRAM of the present invention, the MO
In a semiconductor substrate having a region for forming an SFET and a region for forming a MOSFET forming a peripheral circuit of a memory array, and a multilayer wiring layer formed on the semiconductor substrate, a circuit for changing a power supply voltage is provided in a peripheral circuit region. The formation of the memory array is omitted by making the thickness of the gate insulating film of the MOSFET constituting the memory array and the thickness of the gate insulating film of the MOSFET constituting the peripheral circuit the same on the surface of the semiconductor substrate. And the step of forming the gate insulating film of the MOSFET constituting the peripheral circuit and the gate insulating film of the MOSFET constituting the peripheral circuit in the same step.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(First Embodiment) FIG. 1 is a circuit diagram showing a part of a semiconductor integrated circuit device having a DRAM according to a first embodiment of the present invention.

In FIG. 1, only one memory cell MC is shown in the DRAM memory array, but a plurality of memory cells MC are shown in the memory array in the semiconductor integrated circuit device having the DRAM of the present embodiment. Are arranged. Further, peripheral circuits including various circuits such as a logic circuit are arranged around the memory cell MC.
WL indicates a word line, and BL indicates a bit line.

FIG. 2 is a diagram showing a DR according to the first embodiment of the present invention.
FIG. 9 is an operation waveform diagram (timing chart) showing operation waveforms of circuits in a memory array of a semiconductor integrated circuit device having AM.

The voltage of the word line WL of the memory array in the semiconductor integrated circuit device having the DRAM of the present embodiment is 2.5 V, which is a low voltage. In this case, the voltage at the beginning of the operation time of the word line WL is -0.9 V
And

The voltage of the bit line BL is 1.6 V, the voltage of the bit line / (bar) BL (the lowest voltage of the bit line BL) is 0 V, and the voltage of the bit line BL and the bit line / BL In contrast to the starting (average) voltage (0.8 V) with the voltage of the bit line BL, the voltage (1.6 V) of the bit line BL is higher than the starting voltage (0.8 V).
V), and the voltage (0 V) of the bit line / BL is 0.8 V lower than the starting voltage (0.8 V).

Therefore, the voltage of the bit line / BL of the memory array in the semiconductor integrated circuit device having the DRAM of this embodiment is set to 0 V, and a voltage higher than the voltage (0 V) by 0.8 V is applied to the bit line BL. Voltage (0.8
V). Also, the starting voltage of the bit line BL (0.8
V) higher than the voltage of the bit line BL (1.6
V). Further, the voltage of the bit line BL (1.6
V) higher than the voltage of the word line WL (2.5 V).
V), the voltage of the word line WL (2.5
V) is 1.V with respect to the starting voltage (0.8) of the bit line BL.
The voltage becomes as high as 7V, and M
The voltage applied to the OSFET (MOSFET of the memory cell) (that is, the voltage of the difference between the voltage of the word line WL and the voltage of the bit line / BL) can be set to a low voltage (2.5 V). Note that the semiconductor integrated circuit device having the DRAM of the present embodiment is of a negative word (boostless) type.

As a result, the MOS constituting the memory array
The voltage applied to the FET (MOSFET of the memory cell) (2.
5V) can be set to a low voltage, so that the power supply voltage can be the same as the power supply voltage of the peripheral circuit (the voltage of the power supply line of the peripheral circuit).

Further, the MOSFE forming the memory array
Since the voltage applied to T (2.5 V) can be made lower, the power supply voltage of the peripheral circuit can be made the same as the voltage (2.5 V) in the memory array.
The power supply voltage of the peripheral circuit is changed to the MOSF which forms the memory array.
A circuit for changing the power supply voltage to use the same power supply as the voltage applied to the ET (power supply voltage) is not required,
In the area of the peripheral circuit, an area where a circuit for changing the power supply voltage is arranged can be omitted.

Further, the MOSF constituting the memory array
Since the voltage (2.5 V) applied to the ET can be made lower, the power supply voltage of the peripheral circuit can be made the same as the voltage (2.5 V) in the memory array. Since the threshold voltage (Vth) and the threshold voltage of the MOSFET forming the peripheral circuit can be made the same, the gate insulating film of the MOSFET forming the memory array is made thinner, and the thickness and the thickness of the gate insulating film are reduced. MO that configures peripheral circuits
The thickness of the gate insulating film of the SFET can be made the same.

As a result, the semiconductor integrated circuit device having the DRAM according to the present embodiment can have high performance and high reliability and can have high integration.

FIG. 3 shows a DR according to the first embodiment of the present invention.
FIG. 2 is a schematic sectional view showing a part of a semiconductor integrated circuit device having an AM.

As described above, the voltage (2.5 V) applied to the MOSFET (the MOSFET of the memory cell) constituting the memory array can be made low, so that the power supply voltage of the peripheral circuit can be reduced by the voltage (power supply) in the memory array. The circuit for changing the power supply voltage to use the same power supply as the power supply voltage is omitted.

Further, the MOSFE forming the memory array
The gate insulating film 4 of T is thinned, and the gate insulating film 4
And the thickness of the gate insulating film 4 of the MOSFET constituting the peripheral circuit are the same.

Next, a method of manufacturing a semiconductor integrated circuit device having a DRAM according to the present embodiment will be described. In the method of manufacturing a semiconductor integrated circuit device having a DRAM according to the present embodiment, formation of a circuit for changing a power supply voltage of a peripheral circuit is omitted. Further, it is characterized in that the thickness of the gate insulating film of the MOSFET constituting the memory array and the thickness of the gate insulating film of the MOSFET constituting the peripheral circuit are the same, and the gate insulating film is a thin gate insulating film. Therefore, various prior arts can be applied to other manufacturing steps.

First, after a p-type well 2 and an n-type well (not shown) are formed on a p-type semiconductor substrate 1 made of, for example, single crystal silicon, the element isolation region is thermally oxidized to form a silicon oxide film. A field insulating film 3 for element isolation is formed.

Next, a gate insulating film 4 made of a single-layer silicon oxide film is formed on the semiconductor substrate 1. In this case, the thickness of the gate insulating film 4 of the MOSFET forming the memory array and the thickness of the gate insulating film 4 of the MOSFET forming the peripheral circuit are the same, and the thin gate insulating film 4 is used. The gate insulating film 4 of the MOSFET forming the array and the gate insulating film 4 of the MOSFET forming the peripheral circuit can be formed using the same manufacturing process. Also, the gate insulating film 4
In another embodiment, the gate insulating film 4 may have a two-layer structure including a silicon oxide film and a silicon nitride film according to design specifications.

After that, for example, a conductive polycrystalline silicon layer (conductive layer) serving as the gate electrode 5 is formed on the gate insulating film 4 by using a CVD (Chemical Vapor Deposition) method, and then, for example, oxidized thereon. An insulating film 6 made of a silicon film or the like is formed. Next, unnecessary regions of the insulating film 6, the conductive polycrystalline silicon layer and the gate insulating film 4 are removed by using a photolithography technique and a selective etching technique, and the gate region having the pattern of the gate electrode 5 is removed. Is formed.

In this case, the two gate electrodes 5 at the center of the memory array area are partially used as gate electrodes as first gates, and also serve as word lines WL of the DRAM. Gate electrode 5
Are used as wiring layers.

Next, after forming a sidewall spacer 7 on the side wall of the gate electrode 5, an n-type semiconductor region 8 serving as a source / drain of the MOSFET is formed.

In this case, after an insulating film such as a silicon oxide film is formed on the semiconductor substrate 1 including the side wall of the gate electrode 5 by using a CVD method, a photolithography technique and a selective etching technique are used. Then, by removing the insulating film in an unnecessary region, a sidewall spacer 7 made of an insulating film is formed on the side wall of the gate electrode 5.

After that, an n-type impurity such as phosphorus is ion-implanted from above the semiconductor substrate 1 into the p-type well 2 by ion implantation, and then an annealing process is performed to perform the source / source of the MOSFET. An n-type semiconductor region 8 serving as a drain is formed. Thereafter, although not shown, a p-type impurity such as boron is ion-implanted into the n-type well from above the semiconductor substrate 1 using an ion implantation method, and then an annealing process is performed. MOSFE
A p-type semiconductor region serving as a source / drain of T is formed.

Next, after an insulating film 9 is formed on the semiconductor substrate 1, a through hole (connection hole) is formed in the insulating film 9, and a plug 10 is formed in the through hole. In this case, for example, a silicon oxide film is formed as the insulating film 9 by CVD.
After being formed by the method, the surface is polished and the surface thereof is flattened to form a flattened insulating film 9. In the planarization process, the surface of the insulating film 9 is, for example, CMP (Ch
An embodiment in which the surface is flattened by an emical mechanical polishing (chemical mechanical polishing) method or an etch-back method can be adopted.

Next, after a through hole is formed in a selective region of the insulating film 9 by using a photolithography technique and a selective etching technique, a conductive material such as a conductive polycrystalline silicon film is buried in the through hole. Thus, the plug 10 is formed.

Next, after an insulating film 11 such as a thin silicon oxide film is formed on the semiconductor substrate 1, a through hole is formed in the insulating film 11 on a specific plug 10, and then, for example, an aluminum layer or the like is formed. Is formed. In this case, the wiring layer 12 in the area of the memory array
This is the bit line BL of the RAM.

Next, an insulating film 13 is formed on the semiconductor substrate 1. The insulating film 13 is, for example, a silicon oxide film formed by CVD.
After being formed by the method, the surface is polished and the surface thereof is flattened to form the flattened insulating film 13. In this case, the insulating film 13 is, for example, a PSG (Phospho Silicate Glas) which is a silicon oxide film containing phosphorus.
s) A BPSG (Boro Phospho Silicate Glass) film, which is a silicon oxide film containing boron and phosphorus, or an SOG (Spin On) film that can be formed by a spin coating method.
Glass) film or the like can be applied.

After that, through holes are formed in the insulating film 13 and selective regions of the insulating film 11 therebelow by using photolithography technology and selective etching technology, and then, for example, conductive polycrystalline silicon or tungsten is formed in the through holes. Plug 14 by embedding a conductive material such as
To form

Next, COB (Capacitor) is placed on the semiconductor substrate 1.
A storage node (storage electrode) 15 which is an electrode of a capacitor of a tor over bitline type memory cell is formed.
The storage node 15 is formed by depositing a conductive polycrystalline silicon layer containing impurities such as phosphorus on the semiconductor substrate 1 by a CVD method, and then patterning the layer using a photolithography technique and a selective etching technique. Is formed. In this case, storage node 1
Reference numeral 5 designates a function as a lower electrode of a capacitor which is a capacitance element for storing information of a memory cell.

Next, a dielectric film 16 is deposited on the semiconductor substrate 1 including the storage node 15. Dielectric film 16
Are, for example, Si ₃ N ₄ (silicon nitride), Ta ₂
O ₅ (tantalum pentoxide) or PZT which is a ferroelectric film
(Lead zirconate titanate) or the like is deposited. Thereafter, a plate electrode 17 which is an electrode of a capacitor is formed on the semiconductor substrate 1. The plate electrode 17 is formed by depositing a conductive polycrystalline silicon layer containing impurities such as phosphorus on the semiconductor substrate 1 by a CVD method and then patterning the layer using a photolithography technique and a selective etching technique. Form. In this case, the plate electrode 17 has a function as an upper electrode in a capacitor that is an information storage capacitance element of a memory cell.

Next, an insulating film 18 as an interlayer insulating film is formed on the semiconductor substrate 1. Thereafter, the insulating film 18 is formed by using a photolithography technique and a selective etching technique.
Through holes (not shown) are formed as necessary in the selective region of (1). The insulating film 18 is formed by, for example, forming a silicon oxide film by a CVD method, polishing the surface, and performing a flattening process on the surface.
8 is formed. The flattening process may employ a mode in which the surface of the insulating film 18 is flattened by, for example, a CMP method or an etch-back method. The insulating film 18 is, for example, a PSG film which is a silicon oxide film containing phosphorus or a silicon oxide film which is a silicon oxide film containing boron and phosphorus.
A PSG film, an SOG film formed by a spin coating method, or the like can be used.

Thereafter, a wiring layer 19 made of, for example, an aluminum layer is formed on the semiconductor substrate 1. In this case, the wiring layer 19 is a power supply wiring layer. Next, by forming a passivation film (not shown) on the semiconductor substrate 1, the manufacturing process of the semiconductor integrated circuit device having the DRAM is completed.

According to the semiconductor integrated circuit device having the DRAM of the present embodiment and the method of manufacturing the same, the voltage (2.5) applied to the MOSFET forming the memory array
Since V) can be set to a low voltage, a circuit for changing the power supply voltage to use the same power supply voltage (power supply voltage) in the memory array as the power supply voltage of the peripheral circuit is omitted.

Further, the MOSFE forming the memory array
The gate insulating film 4 of T is thinned, and the gate insulating film 4
And the thickness of the gate insulating film 4 of the MOSFET constituting the peripheral circuit are the same. Further, the gate insulating film 4 of the MOSFET forming the memory array and the gate insulating film 4 of the MOSFET forming the peripheral circuit are formed as a single-layer silicon oxide film by using the same manufacturing process. Therefore, the MOS constituting the memory array
MOSF constituting the gate insulating film 4 of the FET and the peripheral circuit
The ET gate insulating film 4 can be formed by the same manufacturing process using a highly reliable silicon oxide film having a one-layer structure.

Therefore, according to the semiconductor integrated circuit device having the DRAM of the present embodiment and the method of manufacturing the same,
Since the manufacturing process can be simplified, a high manufacturing yield can be achieved, and high performance, high reliability, and high integration can be achieved.

(Embodiment 2) FIG. 4 is an operation waveform diagram showing operation waveforms of circuits in a memory array of a semiconductor integrated circuit device having a DRAM according to Embodiment 2 of the present invention.

In the semiconductor integrated circuit device having the DRAM of the present embodiment, the voltage of the word line WL of the memory array is set to 3.3V. In this case, the voltage at the beginning of the operation time of the word line WL is 0V.

The voltage of the bit line BL is 2.4 V, the voltage of the bit line / (bar) BL is 0.8 V, and the start (average) of the voltage of the bit line BL and the voltage of the bit line / BL is started. ) With respect to the voltage (1.6 V), the voltage (2.
4V) is higher than the starting voltage (1.6 V) by 0.8 V, and the voltage of the bit line / BL (0.8 V) is higher than the starting voltage (1.6 V).
0.8 V lower than 6 V).

Therefore, in the semiconductor integrated circuit device having the DRAM of the present embodiment, the voltage of the bit line / BL of the memory array is set to 0.8V, and the voltage (0.8
A voltage that is 0.8 V higher than V) is set as the starting voltage (1.6 V) of the bit line BL. In addition, a voltage 0.8 V higher than the starting voltage (1.6 V) of the bit line BL is set as the voltage (2.4 V) of the bit line BL. Further, by setting the voltage 0.9 V higher than the voltage (2.4 V) of the bit line BL as the voltage (3.3 V) of the word line WL, the voltage (3.3 V) of the word line WL is reduced to the bit line BL. Of the word line WL (3.3 V) as a voltage applied to a MOSFET (a MOSFET of a memory cell) constituting a memory array and a bit higher than the starting voltage (1.6) of the memory cell. A voltage (2.5 V) that is different from the voltage of the line / BL (0.8 V) can be set to a low voltage. The DR of the present embodiment
A semiconductor integrated circuit device having an AM is a BSG (boothed
sense graund) system.

As a result, the MOS constituting the memory array
Since the voltage (2.5 V) applied to the FET can be reduced, the power supply voltage of the peripheral circuit can be made the same.

Further, the MOSFE forming the memory array
Voltage applied to T (MOSFET of memory cell) (2.5
Since V) can be set to a low voltage, the semiconductor integrated circuit device having the DRAM of the present embodiment and the method of manufacturing the same are the same as the semiconductor integrated circuit device having the DRAM of the first embodiment and the method of manufacturing the same. Can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, the present invention relates to a MOSFET, a CMO
D composed of SFET, BiCMOSFET, etc.
The present invention can be applied to a semiconductor integrated circuit device having a RAM and a method of manufacturing the same.

Further, the present invention relates to a MOSFET, a CMOS,
The present invention can be applied to a semiconductor integrated circuit device having a DRAM including a peripheral circuit in which various circuits such as a logic system including an FET, a BiCMOSFET, a bipolar transistor and the like are arranged, and a method of manufacturing the same.

[0057]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the semiconductor integrated circuit device having the DRAM of the present invention, the MOS constituting the memory array
Since the voltage applied to the FET (MOSFET of the memory cell) (that is, the voltage of the difference between the word line voltage and the lowest voltage on the bit line) can be as low as 2.5 V, the power supply voltage of the peripheral circuit can be reduced. Can be identical.

Also, the MOSFE forming the memory array
Since the voltage applied to T can be made lower, the power supply voltage of the peripheral circuit can be made the same as the voltage in the memory array. Therefore, the power supply voltage of the peripheral circuit is the same as the voltage (power supply voltage) in the memory array. A circuit for changing the power supply voltage for using the power supply is not required, and an area for arranging a circuit for changing the power supply voltage in the peripheral circuit area can be omitted.

Further, since the power supply voltage of the peripheral circuit can be made equal to the voltage in the memory array, the threshold voltage of the MOSFET forming the memory array and the threshold voltage of the MOSFET forming the peripheral circuit are made the same. MOS transistors that make up a memory array
By reducing the thickness of the gate insulating film of the FET, the thickness of the gate insulating film can be made equal to the thickness of the gate insulating film of the MOSFET forming the peripheral circuit.

As a result, the semiconductor integrated circuit device having the DRAM according to the present embodiment can achieve higher performance and higher reliability and higher integration.

(2). According to the semiconductor integrated circuit device having the DRAM and the method of manufacturing the same of the present invention, the voltage applied to the MOSFETs forming the memory array can be reduced, so that the power supply voltage of the peripheral circuit can be reduced to the voltage (power supply voltage) in the memory array. The circuit for changing the power supply voltage to use the same power supply as in ()) is omitted.

The MOSFE forming the memory array
The thickness of the gate insulating film of T is reduced, and the thickness of the gate insulating film is the same as the thickness of the gate insulating film of the MOSFET constituting the peripheral circuit. Further, the gate insulating film of the MOSFET forming the memory array and the gate insulating film of the MOSFET forming the peripheral circuit are formed as a single-layer silicon oxide film by using the same manufacturing process. Therefore, the gate insulating film of the MOSFET forming the memory array and the gate insulating film of the MOSFET forming the peripheral circuit can be formed by the same manufacturing process using a highly reliable single-layer silicon oxide film.

Therefore, according to the semiconductor integrated circuit device having the DRAM of the present invention and the method of manufacturing the same, the manufacturing process can be simplified, so that a high manufacturing yield can be achieved, and high performance and high reliability can be achieved. And high integration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of a semiconductor integrated circuit device having a DRAM according to a first embodiment of the present invention;

FIG. 2 is an operation waveform diagram showing operation waveforms of circuits in a memory array of the semiconductor integrated circuit device having the DRAM according to the first embodiment of the present invention;

FIG. 3 is a schematic sectional view showing a part of the semiconductor integrated circuit device having the DRAM according to the first embodiment of the present invention;

FIG. 4 is an operation waveform diagram showing operation waveforms of circuits in a memory array of a semiconductor integrated circuit device having a DRAM according to a second embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 well 3 field insulating film 4 gate insulating film 5 gate electrode 6 insulating film 7 sidewall spacer 8 semiconductor region 9 insulating film 10 plug 11 insulating film 12 wiring layer 13 insulating film 14 plug 15 storage node 16 dielectric film 17 plate electrode 18 insulating film 19 wiring layer BL bit line MC memory cell WL word line

Claims (7)

[Claims] 1. A DRAM characterized in that a voltage of a difference between a voltage of a word line and a voltage of a bit line in a memory array is equal to a voltage of a power supply line of a peripheral circuit of the memory array. Semiconductor integrated circuit device. 2. A semiconductor integrated circuit device having a DRAM according to claim 1, wherein said memory array comprises
A semiconductor integrated circuit device having a DRAM, wherein the thickness of the gate insulating film of the OSFET is the same as the thickness of the gate insulating film of the MOSFET constituting the peripheral circuit. 3. The semiconductor integrated circuit device having a DRAM according to claim 1, wherein a voltage of a word line in said memory array is 2.5 V, and a voltage of a word line in said memory array is 2.5 V. DRA characterized in that the difference voltage from the bit line voltage is 2.5V.
A semiconductor integrated circuit device having M. 4. The semiconductor integrated circuit device having a DRAM according to claim 1, wherein a voltage of a word line in said memory array is 3.3 V, and a voltage of said word line in said memory array is less than 3.3 V. DRA characterized in that the difference voltage from the bit line voltage is 2.5V.
A semiconductor integrated circuit device having M. 5. A semiconductor substrate having a region for forming a MOSFET forming a memory array, a region for forming a MOSFET forming a peripheral circuit of the memory array, and a multilayer wiring layer formed on the semiconductor substrate, A method for manufacturing a semiconductor integrated circuit device having a DRAM, wherein forming a circuit for changing a power supply voltage in a circuit region is omitted. 6. A method for manufacturing a semiconductor integrated circuit device having a DRAM according to claim 5, wherein a thickness of a gate insulating film of a MOSFET constituting the memory array and the peripheral circuit are formed on a surface of the semiconductor substrate. Constituting MOSFET
And forming the gate insulating film of the MOSFET forming the memory array and the gate insulating film of the MOSFET forming the peripheral circuit by the same process by making the film thickness of the gate insulating film the same. DRA to do
A method for manufacturing a semiconductor integrated circuit device having M. 7. A method of manufacturing a semiconductor integrated circuit device having a DRAM according to claim 5, wherein a gate insulating film of a MOSFET constituting the memory array and a gate insulating film of a MOSFET constituting the peripheral circuit are provided. Is 1
A method for manufacturing a semiconductor integrated circuit device having a DRAM, wherein a silicon oxide film having a layer structure is used.