JPH1079480A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Problem] To simultaneously form a connection hole for connecting upper and lower wiring and a connection hole for connecting between wiring and a semiconductor element, a connection hole having a small aspect ratio for connecting between upper and lower wiring. To prevent the bottom of the substrate from being over-etched. SOLUTION: A silicon oxide film 37 deposited on an information storage capacitive element C of a DRAM is etched to form an upper portion of a plate electrode 34 and a MISFET (an n-channel MISFET Qn and a p-channel MISFE) of a peripheral circuit.
When the connection holes 38 to 42 are simultaneously formed above the TQp), the plugs 29 are formed beforehand under the connection holes 39 to 42 of the peripheral circuit, so that the plugs 29 are formed above the information storage capacitive element C. The aspect ratio of the connection hole 38,
Connection hole 39 formed above MISFET of the peripheral circuit
A large difference is not caused in the aspect ratio of ~ 42.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly, to a semiconductor integrated circuit device having a multi-layer wiring structure, in which a connection hole for connecting upper and lower wiring and between a wiring and a semiconductor element is opened. The present invention relates to technology that is effective when applied to a drilling process.

[0002]

2. Description of the Related Art In recent years, large-capacity DRAMs have been proposed in which an information storage capacitor is replaced with a memory cell selection MISFET in order to compensate for a decrease in the amount of stored charge (Cs) of the information storage capacitor accompanying the miniaturization of memory cells. It employs a stacked capacitor structure located at the top.

An information storage capacitor having a stacked capacitor structure is formed by sequentially stacking a storage electrode (lower electrode), a capacitor insulating film, and a plate electrode (upper electrode). The storage electrode of this information storage capacitor is a memory cell selection M
ISFET semiconductor region (source region, drain region)
Connected to one of the The plate electrode is configured as an electrode common to a plurality of memory cells, and is supplied with a predetermined fixed potential (plate potential).

A bit line for writing and reading data is connected to the other of the semiconductor regions (source region and drain region) of the memory cell selecting MISFET. The bit line is disposed between the memory cell selection MISFET and the information storage capacitor, or above the information storage capacitor. The structure in which the information storage capacitor is placed above the bit line is a capacitor over bit line (Cap
It is called an acitor over bitline (COB) structure.

A DRAM having the above-mentioned COB structure is described in Japanese Patent Application Laid-Open No. 7-122654.

The DRAM described in the above publication is for selecting a memory cell in which a gate electrode (word line) is formed of a polycrystalline silicon film or a laminated film (polycide film) of a polycrystalline silicon film and a tungsten silicide (WSix) film. MI
A bit line formed of a polycrystalline silicon film (or a polycide film) is disposed above the SFET, and a storage electrode formed of a polycrystalline silicon film is formed above the bit line, and a stacked film of a silicon oxide film and a silicon nitride film is formed. An information storage capacitor composed of a formed capacitor insulating film and a plate electrode formed of a polycrystalline silicon film is arranged.

A low-resistance Al (aluminum) wiring is arranged above the information storage capacitor. Al
A part of the wiring is used as a wiring for supplying a plate potential to the plate electrode of the information storage capacitor, and another part is used as a wiring connecting MISFETs in the peripheral circuit.

[0008]

The above-mentioned DRAM has the following problems.
A part of the Al wiring formed on the information storage capacitor is electrically connected to a plate electrode of the information storage capacitor,
The other part is electrically connected to the MISFET of the peripheral circuit.

In this case, the Al wiring connected to the plate electrode of the information storage capacitor element is connected to the plate electrode through a connection hole having a small aspect ratio formed in an insulating film covering the plate electrode, while the peripheral circuit is connected to the peripheral circuit. MISFE
The Al wiring connected to T is formed through a connection hole having a large aspect ratio formed in the insulating film covering the MISFET, the insulating film covering the bit line, and the insulating film covering the plate electrode.
Connected to ISFET. That is, the MISF of the peripheral circuit
There is a large difference in the aspect ratio between the connection hole formed above the ET and the connection hole formed above the plate electrode.

Therefore, the MISFET of the peripheral circuit and the Al
If the connection hole for connecting the wiring and the connection hole for connecting the plate electrode and the Al wiring are simultaneously formed in the same process, the bottom of the connection hole having a small aspect ratio formed on the top of the plate electrode becomes excessive. The plate electrode is etched away and the connection hole may penetrate the plate electrode in some cases.

An object of the present invention is to form a connection hole having a small aspect ratio for connecting the upper and lower wirings when simultaneously forming a connection hole for connecting the upper and lower wirings and a connection hole for connecting the wiring and the semiconductor element. It is an object of the present invention to provide a technique for preventing a bottom portion of the semiconductor device from being excessively etched.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of (a) forming a semiconductor element on a semiconductor substrate and then forming one layer via one or more insulating films covering the semiconductor element; Or a step of forming a plurality of layers of wirings, (b)
A step of forming a first connection hole reaching the semiconductor element by etching the one or more layers of insulating film, and then burying a plug in the first connection hole; (c) an upper part of the wiring and the plug Depositing an insulating film on the substrate, etching the insulating film, and simultaneously forming a second connection hole reaching the wiring and a third connection hole reaching the plug;
Contains.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: (a) providing a MIS for selecting a memory cell on a semiconductor substrate;
Forming a first insulating film on the memory cell selecting MISFET and the peripheral circuit MISFET after forming the FET and the peripheral circuit MISFET;
(B) etching the first insulating film to form a connection hole reaching a source region and a drain region of the memory cell selection MISFET, and then burying a first plug in the connection hole; After forming a bit line on the first insulating film and then forming a second insulating film on the bit line, the second insulating film is etched to form a source region and a drain region of the memory cell selecting MISFET. Forming a connection hole reaching the connection hole in which the first plug is embedded on one of the upper portions, and then a second hole is formed inside the connection hole.
A step of embedding a plug, (d) forming an information storage capacitor on the second insulating film, etching the second insulating film and the first insulating film, and forming an M on the peripheral circuit.
Forming a connection hole reaching a source region, a drain region or a gate electrode of the ISFET, and then embedding a third plug in the connection hole; (e) forming a third insulating film on the information storage capacitor element Then, the third insulating film is etched to simultaneously form a connection hole reaching the plate electrode of the information storage capacitor and a connection hole reaching the connection hole of the peripheral circuit in which the third plug is embedded. And (f) patterning the conductive film formed on the third insulating film to form a wiring that is electrically connected to a plate electrode of the information storage capacitor and the peripheral via the third plug. Forming a source region, a drain region, or a gate electrode of a MISFET of a circuit and a wiring electrically connected to the MISFET at the same time.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a DRAM according to an embodiment of the present invention will be described below in detail with reference to FIGS. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

First, as shown in FIG. 1, a field oxide film 4 is formed on the surface of a semiconductor substrate 1 by selective oxidation (LOCOS).
Is formed, a p-type impurity (boron (B)) is ion-implanted into the semiconductor substrate 1 in a region where a memory array is formed and a region where an n-channel MISFET of a peripheral circuit is formed, thereby forming a p-type well 2. Peripheral circuit p-channel MISFE
An n-type well 3 is formed by ion-implanting an n-type impurity (phosphorus (P)) into the semiconductor substrate 1 in a region where T is formed. Subsequently, a p-type impurity (B) is ion-implanted into the p-type well 2 to form a p-type channel stopper layer 5.
The n-type channel stopper layer 6 is formed by ion-implanting a type impurity (P). Thereafter, a gate oxide film 7 is formed on the surface of each active region of the p-type well 2 and the n-type well 3 surrounded by the field oxide film 4 by a thermal oxidation method.

Next, as shown in FIG. 2, the gate electrode 8A (word line W) of the memory cell selecting MISFET Qt is
L), gate electrode 8B of n-channel type MISFET Qn
And gate electrode 8C of p-channel type MISFET Qp
To form The gate electrode 8A (word line WL) and the gate electrodes 8B and 8C are formed by depositing a polycrystalline silicon film and a tungsten (W) film or a W silicide (WSix) film by a CVD method and then etching using a photoresist as a mask. These films are formed simultaneously by patterning.
The polycrystalline silicon film is doped with an n-type impurity (P).

Next, as shown in FIG. 3, an n-type impurity (P) is ion-implanted into the p-type well 2 to form a memory cell selecting M.
The n-type semiconductor regions 9 and 9 (source regions,
Drain region) and n ^{− of the} n-channel type MISFET Qn.
And a p-type MISFET Q by ion-implanting a p-type impurity (B) into the n-type well 3.
A p ^- type semiconductor region 14 of p is formed.

Next, as shown in FIG. 4, the gate electrode 8A of the memory cell selecting MISFET Qt (word line W
L), gate electrode 8 of n-channel type MISFET Qn
B, A sidewall spacer 11 is formed on each side wall of the gate electrode 8C of the p-channel type MISFET Qp. The sidewall spacer 11 is formed by anisotropically etching a silicon nitride film deposited by a CVD method. Next, an n-type impurity (P) is ion-implanted into the p-type well 2 of the peripheral circuit to form the n ⁺ -type semiconductor region 13 of the n-channel MISFET Qn, and a p-type impurity (B) is ion-implanted into the n-type well 3. And the p-channel type MISFET Qp
Forming a p ⁺ -type semiconductor region 15.

Next, as shown in FIG. 5, the gate electrode 8A of the memory cell selecting MISFET Qt (word line W
L), gate electrode 8 of n-channel type MISFET Qn
The silicon oxide film 17 and the BP are formed on the respective gate electrodes 8C of the B and p channel type MISFETs Qp by CVD.
After depositing the SG film 18, a chemical mechanical polishing method (Chemica
l BPSG film 18 by mechanical polishing (CMP)
Is polished and its surface is flattened.

Next, as shown in FIG.
After depositing a polycrystalline silicon film 28 thereon by a CVD method, the polycrystalline silicon film 28 is etched using a photoresist as a mask, and then the photoresist is removed. Then, the BPSG film 18 is formed using the polycrystalline silicon film 28 as a mask. , The silicon oxide film 17 and the gate oxide film 7 are etched to form a connection hole 21 above one of the source region and the drain region (n-type semiconductor region 9) of the memory cell selecting MISFET Qt, and to form the other (n-type). A connection hole 22 is formed above the semiconductor region 9). At this time, the gate electrode 8A of the memory cell selecting MISFET Qt (word line W
L) Silicon nitride film 10 formed on the upper part and silicon nitride sidewall spacer 11 formed on the side wall
Are left almost unetched, so that the connection holes 21 and 22 having a diameter smaller than the resolution of the exposure light used to form the photoresist mask can be formed by self-alignment (self-alignment).

Next, as shown in FIG.
2, a polycrystalline silicon plug 20 is formed. This plug 20 is formed on the polycrystalline silicon film 28 by CVD.
After depositing a polycrystalline silicon film by the method, the polycrystalline silicon film and the polycrystalline silicon film 28 on the BPSG film 18 are removed by etch-back. The polycrystalline silicon film forming the plug 20 is doped with an n-type impurity (P). The plug 20 may be formed of a metal film such as a W film other than the polycrystalline silicon film.

Next, as shown in FIG.
A silicon oxide film 19 is deposited on the top of the substrate by a CVD method, and then the contact hole 2 is etched by using a photoresist as a mask.
After removing the silicon oxide film 19 on the upper part of FIG. 1, as shown in FIG. 9, the silicon oxide film 19, the BPSG film 18, and the silicon oxide film 1 of the peripheral circuit are formed using a photoresist as a mask.
By etching the gate oxide film 7 and the gate oxide film 7,
A connection hole 23 is formed above one of the source region and the drain region of the n-channel MISFET Qn.

Next, as shown in FIG. 10, bit lines BL ₁ and BL ₂ are formed on the silicon oxide film 19. The bit lines BL ₁ and BL ₂ are connected to a polycrystalline silicon film and W by CVD.
After depositing a film or a W silicide (WSix) film, these films are patterned and formed by etching using a photoresist as a mask. The polycrystalline silicon film is doped with an n-type impurity (P).

Next, as shown in FIG.
₁ , silicon oxide film 3 deposited on top of BL ₂ by CVD
1 is polished by a chemical mechanical polishing method to planarize the surface thereof, and then, using a photoresist as a mask, a silicon oxide film 31 is formed.
By etching the silicon oxide film 19 and the source region of the memory cell selecting MISFET Qt,
A connection hole is formed above the connection hole 22 formed above the other of the drain regions (the n-type semiconductor region 9).

Next, as shown in FIG. 12, after a polycrystalline silicon plug 35 is formed inside the connection hole 36, a storage electrode (lower electrode) 32 of the information storage capacitor is formed above the connection hole 36. Form. The polycrystalline silicon plug 35
A polycrystalline silicon film deposited by a CVD method on the silicon oxide film 31 is formed by etching back. Storage electrode 32
Is formed by patterning a polycrystalline silicon film deposited on the silicon oxide film 31 by a CVD method by etching using a photoresist as a mask. The plug 35 and the storage electrode 32 may be formed of a metal film such as a W film in addition to a polycrystalline silicon film.

Next, as shown in FIG.
A silicon nitride film is deposited on the silicon nitride film by a CVD method, a polycrystalline silicon film is deposited on the silicon nitride film by a CVD method, and then these films are patterned by etching using a photoresist as a mask. An information storage capacitor C composed of a storage electrode 32 made of a crystalline silicon film, a capacitance insulating film 33 made of a silicon nitride film, and a plate electrode (upper electrode) made of polycrystalline silicon
To form The capacitor insulating film 33 may be formed of a stacked film of a silicon nitride film and a silicon oxide film, a tantalum oxide (Ta ₂ O ₅ ) film, or the like, in addition to the silicon nitride film. Also,
The plate electrode 34 may be formed of a TiN film, a metal film, or the like.

Next, as shown in FIG. 14, using the photoresist as a mask, the silicon oxide films 31, 19, BPSG
By sequentially etching the film 18, the silicon oxide film 17, and the gate oxide film 7, the n-channel MISFE
A connection hole 24 is formed on one of the source and drain regions of TQn, a connection hole 25 is formed on one of the source region and drain region of the p-channel MISFET Qp, and a connection hole 26 is formed on the other. I do. At the same time,
By sequentially etching the silicon oxide films 31, 19, the BPSG film 18, the silicon oxide film 17, and the silicon nitride film 10, a connection hole 27 is formed above the gate electrode 8C of the p-channel MISFET Qp.

Next, as shown in FIG. 15, the surface of the n ⁺ -type semiconductor region 13 of the n-channel MISFET Qn exposed at the bottom of the connection hole 24 and the p-channel MISFET Qp exposed at the bottom of the connection holes 25 and 26 are formed. After the Ti silicide layer 16 is formed on the surface of the p ⁺ type semiconductor region 15, plugs 29 are formed inside the connection holes 24 to 27. After the Ti film deposited by the sputtering method is annealed to react with the Si substrate (the n ⁺ -type semiconductor region 13 and the p ⁺ -type semiconductor region 15), the unreacted Ti film is removed by etching. Formed. Plug 2
9 is formed by depositing a TiN film and a W film on the silicon oxide film 31 by a CVD method and a sputtering method, and then etching back these films.

Next, as shown in FIG. 16, a silicon oxide film 37 is deposited on the information storage capacitor C by a CVD method, and the surface thereof is flattened by a chemical mechanical polishing method. By etching the silicon oxide film 37 as a mask, a connection hole 38 is formed above the plate electrode 34 of the information storage capacitor C, and at the same time, the connection holes 24 to 27 of the peripheral circuit in which the plug 29 is embedded are formed. Connection holes 39 to 42 are formed in the upper part.

Next, as shown in FIG. 17, wirings 43A to 43D are formed on the silicon oxide film 37. Wiring 4
3A is used to supply a plate potential to the plate electrode 34 of the information storage capacitor C, and the wirings 43B to 43B
3D is used to connect between MISFETs of a peripheral circuit. The wirings 43A to 43D are made of the silicon oxide film 37.
A TiN film, an Al alloy film, and a TiN film are deposited on the upper surface of the substrate by a sputtering method, and these films are patterned and formed simultaneously by etching using a photoresist as a mask.

The D of the present embodiment configured as described above
According to the RAM manufacturing method, the silicon oxide film 37 on the information storage capacitor C is etched to etch the upper part of the plate electrode 34 of the information storage capacitor C and the MI of the peripheral circuit.
At the same time, the connection holes 38 are formed above the SFETs (the n-channel MISFET Qn and the p-channel MISFET Qp).
To 42, the connection holes 39 of the peripheral circuit are formed in advance.
By forming the plug 29 in the lower part of ~ 42,
A large difference does not occur between the aspect ratio of the connection hole 38 formed above the information storage capacitive element C and the aspect ratio of the connection holes 39 to 42 formed above the MISFET of the peripheral circuit. Accordingly, when the connection hole 38 is formed by etching the silicon oxide film 37 on the upper part of the information storage capacitor C, the plate electrode 34 of the information storage capacitor C is excessively shaved or the bottom of the connection hole 38 is formed. Is the plate electrode 3
4 can be reliably prevented.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

In the above embodiment, the memory cell selecting M
A case has been described in which the present invention is applied to a method of manufacturing a DRAM having a memory cell having a stacked capacitor structure in which a bit line is arranged above an ISFET and an information storage capacitor is arranged above the bit line. By applying the present invention when simultaneously forming a connection hole having a small aspect ratio connecting the upper and lower wirings and a connection hole having a large aspect ratio connecting the wiring and the semiconductor element, It is possible to reliably prevent the bottom of the connection hole having a small aspect ratio for connecting the wirings from being excessively etched.

[0036]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the manufacturing method of the present invention, when simultaneously forming a connection hole having a small aspect ratio for connecting upper and lower wirings and a connection hole having a large aspect ratio for connecting a wiring and a semiconductor element, the aspect ratio is previously determined. By embedding a plug in the lower part of the connection hole having a large ratio, it is possible to reliably prevent the bottom of the connection hole having a small aspect ratio connecting the upper and lower wirings from being excessively etched.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to an embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 p-type well 3 n-type well 4 field oxide film 5 p-type channel stopper layer 6 n-type channel stopper layer 7 gate oxide film 8A, 8B, 8C gate electrode 9 n-type semiconductor region 10 silicon nitride film 11 sidewall Spacer 12 n ⁻ type semiconductor region 13 n ⁺ type semiconductor region 14 p ⁻ type semiconductor region 15 p ⁺ type semiconductor region 16 Ti silicide layer 17 silicon oxide film 18 BPSG film 19 silicon oxide film 20 plug 21 connection hole 22 connection hole 23 connection Hole 24 Connection hole 25 Connection hole 26 Connection hole 27 Connection hole 28 Polycrystalline silicon film 29 Plug 31 Silicon oxide film 32 Storage electrode (lower electrode) 33 Capacitive insulating film 34 Plate electrode (upper electrode) 35 Plug 36 Connection hole 37 Silicon oxide Membrane 38 Connection hole 39 Connection hole 40 Connection hole 4 Connection hole 42 connecting hole C information storage capacitor BL _1, BL ₂ bit line Qn n-channel type MISFET Qp p-channel type MISFET Qt memory cell selecting MISFET WL the word line

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having a multi-layer wiring, comprising: (a) forming a semiconductor element on a semiconductor substrate and then interposing one or more insulating films covering the semiconductor element; Forming one or more layers of wiring, (b) etching the one or more layers of insulating film to form a first connection hole reaching the semiconductor element;
Embedding a plug in the first connection hole; (c)
Depositing an insulating film on the wiring and the plug, and then etching the insulating film to simultaneously form a second connection hole reaching the wiring and a third connection hole reaching the plug. A method for manufacturing a semiconductor integrated circuit device, comprising: 2. A semiconductor integrated circuit device having a DRAM having a memory cell of a stacked capacitor structure in which a bit line is arranged above a memory cell selecting MISFET and an information storage capacitance element is arranged above the bit line. (A) forming a memory cell selecting MISFET and a peripheral circuit MISFET on a semiconductor substrate, and then forming a first insulating film on the memory cell selecting MISFET and the peripheral circuit MISFET. (B) forming a connection hole reaching the source region and the drain region of the memory cell selecting MISFET by etching the first insulating film, and then burying a first plug in the connection hole; c) forming a bit line on the first insulating film, and then forming a second insulating film on the bit line; The second insulating film is etched to form a connection hole reaching the connection hole in which the first plug is embedded in one of the source region and the drain region of the memory cell selection MISFET, and then the inside of the connection hole is formed. (D) forming an information storage capacitor on the second insulating film, and then etching the second insulating film and the first insulating film to form a MISFET of the peripheral circuit. Forming a connection hole reaching the source region, the drain region or the gate electrode, and then burying a third plug in the connection hole; (e) forming a third insulating film on the information storage capacitor element Thereafter, the third insulating film is etched to connect to a connection hole reaching the plate electrode of the information storage capacitor, and a connection reaching the connection hole of the peripheral circuit in which the third plug is embedded. And (f) patterning a conductive film formed on the third insulating film to form a wiring electrically connected to a plate electrode of the information storage capacitor, and a third plug. Forming a source region, a drain region, or a gate electrode of the MISFET of the peripheral circuit via a wiring simultaneously with a wiring electrically connected to the MISFET of the peripheral circuit. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein said first plug is made of polycrystalline silicon or metal. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said bit line is formed of a laminated film of polycrystalline silicon and a refractory metal or a silicide thereof. A method for manufacturing an integrated circuit device. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the second plug is made of polycrystalline silicon or metal. . 6. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the third plug is made of a metal. . 7. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said wiring is made of metal.