JPH1117016A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the area of a fuse used for redundancy relief and greatly improve redundancy efficiency. SOLUTION: A window is opened in a passivation film for protecting a semiconductor element or the like in a redundant circuit for replacing a defective bit of a DRAM with a redundant bit and rescuing, and an opening fuse for relieving after forming the passivation film, and an uppermost wiring layer. Two types of non-opening fuses are formed to perform relief before forming the passivation film. Then, a probe test is performed to detect a defective bit in the memory, and the defective bit is relieved by using a non-opening fuse. After that, a passivation film, which is a protective film formed on the uppermost layer, is formed, a probe test is performed again, a defective bit that has deteriorated due to heat treatment during the formation of the passivation film is detected, and an open fuse is cut. Do the relief.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a technique effective when applied to an improvement in the yield of a redundant circuit.

[0002]

2. Description of the Related Art According to studies made by the present inventor, D
2. Description of the Related Art A memory such as a RAM (Dynamic Random Access Memory) is provided with a redundant circuit for relieving a defect created in a manufacturing process in a memory element.

When a defective row or column or a memory cell is present in a memory array, this redundant circuit prepares some spare rows or columns and prepares an address signal corresponding to the defective portion. Alternatively, a spare row or column can be selected and used as a good product while containing defects.

[0004] The redundant circuit is selected by cutting a fuse using, for example, a laser or the like, and allocating an address corresponding to a defective portion randomly generated by the semiconductor chip to a spare portion.

Further, the fuse used for selecting the redundant circuit is formed in the uppermost wiring layer to reduce the fuse area, and to form a passivation film for protecting the semiconductor element and the like from the external atmosphere and mechanical shock. Either a so-called non-opening fuse that performs relief before, or a so-called non-opening fuse that opens a window in the above-described passivation film and performs relief after forming the passivation film is used.

[0006] As an example describing this type of semiconductor device in detail, refer to Susumu Kayama (ed.), Published by Baifukan Co., Ltd. on February 10, 1987, "Ultra High Speed Digital Device Series, Ultra High Speed MOS Device". "P329 ~
P331, which describes a redundant circuit technology of a MOS memory.

[0007]

However, the present inventors have found that the fuses used in the above-described redundant circuit technology have the following problems.

That is, in the case of a non-opening fuse, if a defective bit appears due to the influence of heat treatment in the passivation film forming step, the defective bit cannot be remedied even if the defective bit is detected in a subsequent probe test. There is.

In the open fuse, since the window is opened in the passivation film, the fuse is isolated by a wiring layer and its contact layer in order to prevent mobile ionic contaminants and moisture from entering the active region. There is a problem that the guard ring is formed, the layout area becomes large, and the relief efficiency is reduced.

An object of the present invention is to provide a semiconductor integrated circuit device capable of reducing the area of a fuse used for redundancy repair and greatly improving redundancy efficiency, and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device according to the present invention, the fuse for replacing the defective bit with the redundant bit by cutting is formed by the first fuse which is cut after the formation of the final passivation film, and the formation of the final passivation film. And a second fuse which is cut before.

Further, in the semiconductor integrated circuit device according to the present invention, the first fuse comprises an open fuse having an opening formed in a part of a final passivation film where the first fuse is located, and The fuse consists of a non-open fuse coated with a final passivation film.

By providing an open fuse used for relief before the formation of the final passivation film and a non-open fuse used for relief before the formation of the final passivation film in the semiconductor integrated circuit device, the layout area of these fuses is increased. The relief efficiency can be improved without increasing the cost.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, a first test step of performing a memory cell test for inspecting electrical characteristics of a memory cell before forming a final passivation film, and the first test A first bit rescue step of replacing a defective bit detected in the step with a redundant bit by cutting an open fuse and performing bit rescue;
A step of forming a final passivation film after the first bit rescue step, a second test step of performing a memory cell test for inspecting electrical characteristics of the memory cell after the final passivation film is formed, and a second test step The defective bit detected in the test step is replaced with the redundant bit by cutting the non-open fuse, and the second bit relief is performed.
Bit relief process.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the opening fuse and the non-opening fuse are cut by irradiating a laser beam or a focused ion beam.

Thus, the defective bit can be relieved both before and after the formation of the final passivation film, so that the relieving efficiency by the redundant circuit can be improved.

As described above, the yield of the semiconductor integrated circuit device as a product can be greatly improved.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a memory according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a layout in a semiconductor chip of the memory according to an embodiment of the present invention, and FIG. FIG. 4 is an explanatory view of an open fuse provided in the memory according to the embodiment, FIG. 4 is an explanatory view of a cross section taken along line AA ′ of FIG. 3, and FIG. FIG. 6 is an explanatory view of a cross section taken along line AA ′ of FIG. 5, and FIG. 7 is a flowchart of a defective bit relieving process according to one embodiment of the present invention.

In this embodiment, a memory (semiconductor integrated circuit device) 1 which is a DRAM is provided with a memory mat 2 in which memory cells, which are the minimum units of storage, are regularly arranged in an array.

The memory 1 also includes a row decoder 3 for selecting a word line in a row (row) direction in the memory mat 2 and a row driver for receiving the output of the row decoder 3 and applying a selection pulse voltage to the word line. 4 are provided.

The memory 1 further includes a column decoder 5 for selecting a bit line in a column (column) direction in the memory mat 2 and a column driver 6 for receiving the output of the column decoder 5 and applying a selection pulse voltage to the bit line. Is provided. Further, the memory 1 is provided with a sense amplifier 7 for amplifying a cell read signal of the memory mat 2.

Next, the memory 1 is provided with a row address buffer 8 to which a row direction address signal is input, generates respective internal address signals, and outputs the generated internal address signals to the row decoder 3.

The memory 1 is provided with a column address buffer 9 for receiving an address signal in the column direction, generating an internal address signal, and outputting the generated internal address signal to the column decoder 5.

Further, the memory 1 is provided with a data input buffer 10 for receiving input data at a predetermined timing and a data output buffer 11 for outputting output data at a predetermined timing.

The memory 1 is provided with an input / output control circuit 12 for controlling data input / output by the data input buffer 10 and the data output buffer 11.
Data is exchanged between the sense amplifier 7 and the data input buffer 10 and the data output buffer 11 via the input / output control circuit 12.

Further, the memory 1 selects a memory cell or a memory line as a spare row or column, that is, a redundant word line and a redundant bit line by cutting arbitrary fuses, and replaces the redundant word line and the redundant bit line with redundant bits to replace the redundant circuit. 13 are provided. Further, the fuses of the redundant circuit 13 in the memory 1 are provided with two types of an open fuse and a non-open fuse described later.

The row decoder 3, row driver 4, column decoder 5, column driver 6, sense amplifier 7, row address buffer 8, column address buffer 9, data input buffer 10, data output buffer 11, input / output control circuit Peripheral circuit SC is configured by 12 and redundant circuit 13.

Next, a layout of the memory 1 in the semiconductor chip CH will be described.

First, a semiconductor chip CH in which semiconductor elements are formed on a semiconductor wafer of single crystal silicon or the like is shown in FIG.
As shown in FIG. 7, a memory mat 2 is provided in a peripheral portion of a semiconductor chip CH in a divided manner.

A peripheral circuit SC (portion indicated by a dotted line) is formed at a vertical position in the center of the memory array 2. A redundant circuit 13 (hatched portion) is formed near the center of the area where the peripheral circuit SC is formed. The hatching in FIG. 2 indicates an area where the redundant circuit 13 is formed, and does not indicate a cross section.

Further, in the area where the redundant circuit 13 is formed, an open fuse which is restricted in layout in the area of the redundant circuit 13 in terms of reliability such as movable ion contaminants and moisture resistance is provided. . On the other hand, the non-opening fuse is protected by the passivation film formed on the uppermost layer of the semiconductor chip CH, so that there is no restriction on the layout, and it can be arranged, for example, in the memory mat 2 or the like.

Next, the opening fuse (first fuse) KF formed in the memory 1 will be described with reference to FIGS.

In FIG. 4, an insulating film other than the uppermost passivation film is not shown.

First, in the open fuse KF, a fuse element F1 to be cut at the time of bit rescue is formed by a wiring M2 such as an aluminum wiring of a second layer, and the fuse element F1 is also formed through a through hole TH1 made of tungsten. Is electrically connected to the wiring M3, which is the aluminum wiring layer.

The opening fuse KF is connected to the wiring M3, the wiring M2, and the wiring M so as to surround the fuse element F1.
3 and wiring M2, for example, through-hole TH2 and wiring M2 made of tungsten, wiring M1 made of tungsten wiring in the first layer, and wiring M
2 and a guard ring GR electrically connecting the wiring M1 and also formed of a through hole TH3 made of tungsten.

The guard ring GR is electrically connected via a contact hole C to a semiconductor region SR which is a ground potential formed on a semiconductor substrate.

The uppermost passivation film (final passivation film) PC is formed above the uppermost wiring layer on which the wiring M3 is formed. In the region where the fuse element F1 is located, a window, that is, a window is formed. , The fuse opening where the passivation film PC is not formed (FIG. 4,
A region indicated by a dotted line) is provided.

Therefore, even after the final probe test in which the passivation film PC is formed, the fuse can be cut, and defective bits can be relieved.

In the fuse opening, the insulating film on the fuse element F1 is formed thinner than the other part, so that the fuse element F1 can be easily cut by the laser.

Next, the non-opening fuse (second fuse) NF similarly formed in the memory 1 will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 6 does not show any insulating film other than the uppermost passivation film.

In the non-opening fuse NF, a fuse element F2 to be cut at the time of bit rescue is formed by a wiring M3 made of a third layer aluminum wiring which is the uppermost wiring layer.

In the fuse element F2, in the region indicated by the dotted line in FIG. 6, the insulating film on the fuse element F2 is formed thinner than the other parts, similarly to the fuse element F1 described above. Fuse element F
2 can be easily cut.

Furthermore, since the uppermost passivation film PC is formed above the fuse element F2 as shown in FIG. 6, the fuse element F2 cannot be cut after the passivation film PC is formed. However, the guard ring GR described above becomes unnecessary, and the fuse element F
Since the arrangement interval of 2 only needs to be the spot diameter of laser irradiation, the layout area can be significantly reduced by using the non-open fuse NF.

Next, a bit rescue process in the memory 1 will be described with reference to a flowchart of FIG.

First, when a semiconductor element and a wiring layer are formed on a semiconductor wafer and an insulating film for protecting the wiring layer is formed above the uppermost wiring layer (step S101), an electronic circuit or a memory in each semiconductor chip is formed. A probe test for inspecting electrical characteristics of a cell or the like is performed (step S10).
2). Then, by this probe inspection, a read / write test and a refresh characteristic test on the memory cell are performed to detect a defective bit.

Next, in order to rescue the defective bit of the defect detected in the step S102, the non-open fuse NK (FIGS. 5 and 6) is used, that is, the non-open fuse corresponding to the bit to be relieved is used. Fuse NK, for example,
Cutting is performed by irradiating a laser beam, and a defective bit is relieved (step S103).

Here, the non-opening fuse NK does not require the guard ring GR as described above and can reduce the interval between the fuse elements F2.
The number of reliefs of about 00 bits are formed in the memory mat 2 or the like.

After the step S103, a passivation film PC, which is a protective film formed on the uppermost layer, is formed (step S104), and a probe test is performed again (step S105).

In this probe inspection, a refresh characteristic test is performed again to detect a bit whose refresh characteristic has been degraded by heat treatment or the like performed in the step S104, that is, a so-called drop-out bit, and as described above, the passivation film PC is removed. After the formation, the opening fuse KF (FIGS. 3 and 4) is cut by, for example, irradiating a laser beam to remedy a defective bit (step S106).

Here, since the number of bits rescued in the process of step S106 is small, for example, the number of open fuses KF capable of relieving about 20 bits is reduced in terms of reliability such as movable ion contamination and moisture resistance. Redundant circuit 13
Area.

Thus, in the present embodiment, the opening fuse KF and the non-opening fuse NF are provided in the memory 1, and the non-opening fuse NF is used in the probe inspection before the formation of the passivation film PC, which has many relief bits. In the case of a probe test after forming a passivation film type PC having a small number of bits, the redundancy efficiency can be greatly improved with a small area by performing the bit rescue using the open fuse KF.

Further, since the relieved bit can be relieved after the formation of the passivation film PC, the refresh performance of the memory 1 can be improved.

Furthermore, both the bit before the formation of the passivation film PC and the drop-out bit after the formation of the passivation film PC can be relieved, so that the yield of the memory 1 as a product can be improved.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, the non-open fuse and the open fuse are cut by irradiating a laser beam. However, the cutting of these fuses may be performed by means other than laser beam irradiation, such as by using a focused ion beam. Alternatively, the fuse may be blown.

The fuse may be blown in the normal wiring, and the fuse may be patterned by using a convergent ion beam device at the time of bit rescue, and the fuse may be electrically connected.

[0061]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, an open fuse used for bit rescue before forming a final passivation film and a non-opening fuse used for bit rescue before forming a final passivation film are provided in a semiconductor integrated circuit device. Thus, the relief efficiency can be improved without increasing the layout area of those fuses.

(2) According to the present invention, the defective bit can be relieved both before and after the formation of the final passivation film, so that the relieving efficiency by the redundant circuit can be improved.

(3) Further, in the present invention, the yield of the semiconductor integrated circuit device as a product can be greatly improved by the above (1) and (2).

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a layout in a semiconductor chip of a memory according to one embodiment of the present invention;

FIG. 3 is an explanatory diagram of an opening fuse provided in a memory according to one embodiment of the present invention;

FIG. 4 is an explanatory diagram of a cross section taken along line A-A ′ of FIG. 3;

FIG. 5 is an explanatory diagram of a non-open fuse provided in the memory according to the embodiment of the present invention;

FIG. 6 is an explanatory diagram of a cross section taken along line A-A ′ of FIG. 5;

FIG. 7 is a flowchart of a repair process of a defective bit according to the embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 memory (semiconductor integrated circuit device) 2 memory mat 3 row decoder 4 row driver 5 column decoder 6 column driver 7 sense amplifier 8 row address buffer 9 column address buffer 10 data input buffer 11 data output buffer 12 input / output control circuit 13 redundancy circuit SC Peripheral Circuit CH Semiconductor Chip KF Open Fuse (First Fuse) F1 Fuse Element GR Guard Ring NF Non-Aperture Fuse (Second Fuse) F2 Fuse Element M1 Wiring M2 Wiring M3 Wiring TH1-TH3 Through Hole C Contact Hole SR Semiconductor Area PC Passivation film (final passivation film)

Claims (4)

[Claims] 1. A semiconductor integrated circuit device provided with a redundant circuit having a redundant bit and replacing a defective bit with the redundant bit by cutting a fuse, wherein the fuse is formed after a final passivation film is formed. A semiconductor integrated circuit device comprising: a first fuse to be cut; and a second fuse to be cut before forming a final passivation film. 2. The semiconductor integrated circuit device according to claim 1, wherein said first fuse comprises an open fuse in which an opening is formed in a part of a final passivation film in which said first fuse is located. 2. The semiconductor integrated circuit device according to claim 1, wherein the second fuse is a non-opening fuse coated with a final passivation film. 3. A first test step of performing a memory cell test for inspecting electrical characteristics of a memory cell before forming a final passivation film, and cutting a defective bit detected in the first test step into an open fuse. A first bit rescue step of replacing the bit with a redundant bit to perform bit rescue, a step of forming a final passivation film after the first bit rescue step, and a step of forming a memory cell after the final passivation film is formed. A second test step of performing a memory cell test for inspecting electrical characteristics; and a second step of replacing a defective bit detected in the second test step with a redundant bit by cutting a non-opening fuse to perform bit relief. 2. A method for manufacturing a semiconductor integrated circuit device, comprising: 4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein said opening fuse and said non-opening fuse are cut by irradiating a laser beam or a focused ion beam. A method for manufacturing a circuit device.