JPH1117026A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] PROBLEM TO BE SOLVED: To reduce the cell area and to provide a P-type diffusion layer and a gate.
Device that can be connected to the gate electrode without forming a PN junction.
An SRAM excellent in chair characteristics and productivity is realized. SOLUTION: An SRAM 1 has a half of a memory cell 200.
From the first and second inverters 101 and 102 to the conductive board 3
Is provided, and the first and
2 Each of the inverters 101 and 102 has NMOS and P
MOS and gate voltage of NMOS
The poles 41 and 42 and the PMOS gate electrodes 51 and 52 are connected.
Formed by successive N-type gate electrode wirings 4, 5
Extends from the gate electrode wiring 4 of the first inverter 101
Drawn out wiring 13 and PM of second inverter 102
The second load Tr. The P-type diffusion layer 9 of Q4 is
⁺Connected via the mold embedded contact portion 15.
You. This lead-out wiring 13 is ⁺Type embedded contact
The upper part 15 is formed of a P-type conductive film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a static RAM in which a memory cell is composed of six field effect transistors (hereinafter, referred to as MOS).
(Hereinafter, referred to as SRAM).

[0002]

2. Description of the Related Art Conventionally, an SRAM in which a memory cell is constituted by six MOSs has four N-channel MOSs (hereinafter, referred to as "N" MOSs).
NMOS) and two P-channel MOSs (hereinafter, P
MOS) (complementary MO)
The S) type is known. FIG. 6 is a circuit diagram of a general full CMOS type SRAM. FIG. 7 is a plan view showing an example of the structure of a memory cell of a full CMOS type SRAM, which includes an element isolation region (a portion surrounded by a broken line and a two-dot chain line),
Only the first polysilicon (hereinafter, referred to as first Poly-Si) layer (dot portion) and the formation position of each contact portion are shown. FIG. 8 shows YY ₁ in FIG.
FIG. 3 is a cross-sectional view taken along a line, omitting illustration of a diffusion layer.

As shown in FIGS. 6 to 8, in this SRAM, a semiconductor substrate 71 in a region of a memory cell 70 has a first substrate.
An inverter 101 and a second inverter 102 are provided. The first inverter 101 is a first driver transistor (hereinafter referred to as T
r. First load T composed of Q1 and PMOS
r. Q2 and the first driver Tr. Q1 and the first load Tr. Each of the gate electrodes 721 and 722 of Q2 is formed by a part of the continuous gate electrode wiring 72. Similarly, the second inverter 102 is also a second driver Tr. Q3 and a second load Tr. Q4 and the second driver Tr. Q3 and the second load Tr. Each gate electrode 731 and 732 of Q4
Are formed in a part of the continuous gate electrode wiring 73.

[0004] The first and second inverters 101 and 102 are:
These one inputs are connected to form a so-called flip-flop 100 which becomes the other output.
That is, the gate electrode wiring 72 of the first inverter 101
And the second load Tr. Q4
Is connected to the P-type diffusion layer 75 of the second inverter 10.
Lead wiring 7 extended from the second gate electrode wiring 73
6 and the first driver Tr. The N-type diffusion layer 77 of Q1 is connected. Also, in the flip-flop 100,
The first word Tr. Q5 and the second
Word Tr. Q6 is connected. The first and second words Tr. The gate electrodes 121 and 122 of Q5 and Q6 are each formed by a part of the word line 120.

Here, each gate electrode wiring 72, 73, each lead wiring 74, 76 and the word line 120 are shown in FIG.
The first Poly-Si layer 78 and the second Poly-Si
And layer 79, tungsten silicide (WSi _x) layer 80
Are made of tungsten polycide (hereinafter referred to as W-polycide) laminated in this order. A silicon oxide film 81 is formed to cover the W-polycide, and a planarizing film 8 is formed on the silicon oxide film 81 with a silicon nitride film 82 interposed therebetween.
3 are formed.

Incidentally, generally, an N-type doped Po is used as a gate electrode wiring constituting a gate electrode.
A ly-Si layer or a refractory metal silicide layer obtained by silicidizing the Poly-Si layer and the refractory metal film is used. Therefore, when the gate electrode wiring is directly connected to the P-type diffusion layer, a PN junction is formed, and it is not possible to directly contact the P-type diffusion layer from the gate electrode wiring.

Conventionally, as shown in FIGS. 7 and 8, the planarizing film 83, the silicon nitride film 82, and the silicon oxide film 81 are opened to reach the lead wirings 74 and 75, and further, the lead wirings 74 and 75 are formed. One divided contact hole 84a that opens and reaches the P-type diffusion layer is formed. Then, the contact hole 84a is buried with a conductive film such as aluminum (Al) or buried tungsten (blanket tungsten; Blk W) to form the divided contact portion 84 and to form the local wiring 85 on the flattening film 83. Thus, the connection between the gate electrode wiring 72 and the P-type diffusion layer 75 is established.

[0008]

However, the method of connecting the gate electrode forming the above-mentioned divided contact portion to the P-type diffusion layer is simple in process, but the gate electrode is formed by the same divided contact hole. And the P-type diffusion layer must face outward, so that the diameter of the contact hole needs to be increased. Therefore, this connection method tends to increase the cell area.

On the other hand, in order to directly contact the P-type diffusion layer from the gate electrode, it is essential to use a gate electrode provided with a P-type conductivity. This is because if the gate electrode is N-type, a PN junction is formed at the junction between the gate electrode and the diffusion layer, which causes problems such as an increase in contact resistance and an unstable memory operation. Because. Therefore, conventionally, N-type Po
Along with the NMOS using the ly-Si electrode as the gate electrode,
A surface channel type PMOS using a P-type Poly-Si electrode as a gate electrode is formed, and a part of the P-type gate electrode is
(IEDM Tech.Dig. "A New Full CMOS Cell Structure")
(1984) O. Kudoh, et.al pp67-70). In this method,
A P-type buried contact portion is interposed between the P-type diffusion layer and the P-type gate electrode connected thereto.

However, although the surface channel type PMOS is superior in characteristics to the buried channel type, it is difficult to process a P-type Poly-Si film into a gate electrode pattern with high precision by etching. There are difficulties. Also, due to thermal stress due to high-temperature heat treatment in the SRAM manufacturing process, penetration of boron, which is a P-type impurity, into the channel portion occurs, and the MOS threshold (V
th) fluctuates. As described above, the adoption of the surface channel type PMOS presents a high wall in terms of manufacturing at present. Therefore, development of an SRAM that can solve the above-mentioned problems has been desired.

[0011]

In order to solve the above-mentioned problems, the present invention provides a flip-flop comprising a pair of inverters on a semiconductor substrate in a memory cell, each of which is an N-channel field effect transistor. . (N
MOS) and P-channel field effect Tr. (PMOS) and the NMOS gate electrode and PM
The gate electrode of the OS is formed of a continuous N-type gate electrode wiring, and a lead wiring extending from a gate electrode wiring of a MOS constituting one of the inverters and the other inverter of the pair of inverters. Constituting MOS
Is formed on a semiconductor substrate and connected via a buried contact portion having the same conductivity type as the diffusion layer, the P-type diffusion layer of the diffusion layer The lead wiring connected via the buried contact portion has a configuration in which a P-type conductive film is formed on the P-type buried contact portion.

In the present invention, since the lead-out wiring on the P-type buried contact portion is formed of a P-type conductive film, no PN junction is formed at the connection between the lead-out wiring and the P-type diffusion layer. Also, M which constitutes one inverter
M that constitutes the gate electrode wiring of the OS and the other inverter
Since the connection between the OS and the diffusion layer is made through the buried contact portion, a large-diameter divided contact hole as in the related art is not required. Further, the gate electrode wiring is N
The gate electrode wiring is formed by etching the N-type conductive film. Therefore, the gate electrode wiring is processed with high precision. In addition, since a lead wiring made of a P-type conductive film is not used for a gate electrode wiring, high processing accuracy is not required. Further, since the extraction wiring is not used for the gate electrode wiring, the characteristics of the semiconductor storage device are not affected even if boron, which is a P-type impurity, enters the semiconductor substrate by the high-temperature heat treatment in the manufacturing process of the semiconductor storage device.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. The semiconductor memory device according to the embodiment is formed of a full CMOS type SRAM and has the above-described general circuit configuration shown in FIG. That is, in the memory cell 200, the first inverter 1
01 and a second inverter 102, and a first flip-flop 100 connected to the flip-flop 100.
Word Tr. Q5 and the second word Tr. Q6. The first inverter 101 is a first inverter made of NMOS.
Driver Tr. First load T composed of Q1 and PMOS
r. Q2 and the first driver Tr. Q1 and the first load Tr. Q2 and the diffusion layer are connected. In addition, the second inverter 102
The second driver Tr. Q3 and a second load Tr. Q4 and CMOS.
Driver Tr. Q3 diffusion layer and the second load Tr. The diffusion layer of Q4 is connected.

The first driver Tr. Q1 and the first load Tr.
Q2 and the gate electrode wiring connecting each gate electrode are connected to the second load Tr. It is connected to the diffusion layer of Q4. The second driver Tr. Q3 and the second load Tr. Q4 and the gate electrode wiring connecting each gate electrode are connected to the first driver Tr. Q
1 diffusion layer. In addition, the first driver T
r. Q1 diffusion layer and the second driver Tr. Q3 is connected to the Vss line (ground line), and the first load Tr. Q2 and the second load Tr. The diffusion layer of Q4 is connected to a Vdd line (power supply line).

On the other hand, the first word Tr. Q5 includes one of the diffusion layers and the first driver Tr. Q1 is connected to the diffusion layer of the second word Tr. Q6 is one of the diffusion layers and the second
Driver Tr. The diffusion layer of Q3 is connected. The first word Tr. Q5, second word Tr. Q6 is connected to the bit line 110, and the first word Tr. Q5, second word Tr. Each gate electrode of Q6 is connected to word line 120.

The full CM of the present embodiment having the above circuit configuration
The memory cell of the OS type SRAM has a structure shown in FIG. 2 which is a plan view of FIG. 1 and a cross-sectional view taken along line XX _{1 of} FIG. Here, for convenience of explanation, in FIG. 1, the element isolation region (portion surrounded by a broken line and a two-dot chain line) and the first layer Poly-
Only the formation positions of the Si layer (dot portion) and the contact portion are shown, and FIG. 2 omits the illustration of the diffusion layer other than the buried contact portion described later. The two-dot chain line in FIG. 1 indicates the outline of the memory cell.

As shown in FIGS. 1 and 2, the basic layout of the SRAM 1 of the present embodiment is substantially the same as that of the conventional example shown in FIG. That is, the semiconductor substrate 3 on which the element isolation film 24 is formed in the region of the memory cell 200 is provided with the first driver Tr. Q1, the first load Tr. Q2,
Second driver Tr. Q3, the second load Tr. Q4 is point O
Are provided at the four corners of a rectangle centered at. First driver Tr. Q1, the first load Tr. Each gate electrode 4 of Q2
1 and 42 are formed by a part of the continuous linear gate electrode wiring 4, and the second driver Tr. Q3, the second load Tr. The gate electrodes 51 and 52 of Q4 are also formed by a part of the continuous linear gate electrode wiring 5. These gate electrode wirings 4 and 5 are connected to the semiconductor substrate 3 around the point O.
It is arranged symmetrically above.

The semiconductor substrate 3 has a first driver T
r. Q1 of the first load Tr. The first word T on the opposite side to Q2
r. Q5 is formed and the second driver T
r. Q3, the second load Tr. The second word T on the opposite side to Q4
r. Q6 is formed. And these first and second
Word Tr. Gate electrodes 12 of Q5 and Q6
Reference numerals 1 and 122 each include a part of a word line 120 provided substantially at right angles to the length direction of each of the gate electrode wirings 4 and 5.

The semiconductor substrate 3 has a first driver T
r. An N-type diffusion layer 6 serving as a source / drain is formed on both sides of the gate electrode 41 of the first load Tr. Q
On both sides of the gate electrode 42 of the semiconductor substrate 3 in the formation region 2, a P-type diffusion layer 7 serving as a source / drain is formed. Similarly, the second driver Tr. The N-type diffusion layers 8 are provided on both sides of the gate electrode 51 of the second load Tr. P-type diffusion layers 9 are formed on both sides of the gate electrode 52 of Q4. Further, the first word Tr. Q
5, both sides of the gate electrode 121 of the second word Tr. Q
N-type diffusion layers 10 and 11 are formed on both sides of the gate electrode 122 of No. 6, respectively.

In this case, the first driver Tr. Q1 and the second driver Tr. Q3 side diffusion layer 6 and the first word Tr. Q5, the first driver Tr. The diffusion layer 10 on the Q1 side is formed so as to be connected to each other.
In addition, the second driver Tr. Q3, the first driver Tr. Q1 side diffusion layer 8 and the second word Tr. Q6, the second driver Tr. The diffusion layer 11 on the Q3 side is formed so as to be connected to each other.

From the gate electrode wiring 4, the second load Tr.
Q4, the first load Tr. The lead wiring 13 extends toward the diffusion layer 9 formed on the Q2 side. In addition, the first driver Tr. Q1's second driver Tr. The extraction wiring 14 extends toward the diffusion layer 6 formed on the Q3 side. These lead wirings 13 and 14 are formed, for example, to extend substantially in an L-shape in plan view, and are symmetrically arranged on the semiconductor substrate 3 with the point O as the center.

In the present embodiment, the extraction wiring 13
Is a P type diffusion layer 9 and a P ⁺ type buried contact portion (Bu
ried Contact) connected via 15
The lead wiring 14 is connected to the N-type diffusion layer 6 via the N ⁺ -type buried contact portion 16. At this time, the P ⁺ type buried contact portion 1
5 is formed of a P ⁺ type conductive film.

Here, each of the gate electrode wirings 4 and 5, each of the lead wirings 13 and 14, and the word line 120 are formed, for example, on a first poly-electrode formed on the semiconductor substrate 3 as shown in FIG.
The Si layer 17, and the 2Poly-Si layer 18 formed on the upper layer, WSi _x formed on the first 2Poly-Si layer 18
The layer 19 is formed of W-polycide. Therefore, the lead wires 13 in the P ⁺ -type buried contact portion 15 upper position, P-type impurity is composed of W- polycide became doped P ⁺ -type second 1poly-Si layer 17 and the 2Poly-Si layer 18 ing. In addition, each gate electrode 41, 42, 51, 52, 121, 122
A gate oxide film 23 is interposed between the first Poly-Si layer 17 and the semiconductor substrate 3 at the formation position.

On the other hand, the lead wiring 13, the lead wiring 14, the gate electrode wirings 4, 5 and the word line 120 other than the position on the P ⁺ type buried contact portion 15 are the first Poly.
-Si layer 17 and second Poly-Si layer 18 are made of N ⁺ -type W-polycide by doping N-type impurities. Therefore, the memory cell 200 of the SRAM 1
Of the first and second drivers Tr. Q1, Q3, the first and second loads Tr. Q2, Q4, first and second word T
r. Q5 and Q6 are all gate electrodes 41, 42 and 5
1, 52, 121 and 122 are of the N ⁺ type, and therefore the first and second drivers Tr. Q1, Q3 and the first and second words Tr. Q5 and Q6 are surface channel type NMO
S, the first and second loads Tr. Is a buried channel type PM
OS.

As shown in FIG. 2, this W-polycide is formed on the semiconductor substrate 3 on which the W-polycide is formed as in the prior art.
A silicon oxide film 20 is formed so as to cover polycide. Further, a silicon nitride film 21 is formed to cover the silicon oxide film 20, and a flattening film 22 made of, for example, a boron-phosphorus glass (BPSG) film is formed thereon. Then, a plurality of contact holes (not shown) are formed in the planarizing film 22, the silicon nitride film 21, and the silicon oxide film 20, and inside each contact hole, for example, Al or W for a local wiring 40 described later is formed. The conductive film is embedded, and the first and second contact portions 30 and 31 for the Vss line, the third and fourth contact portions 32 and 33 for the Vdd line, and the fifth and sixth contact portions 34 for the bit line 110 are provided. , 35, and seventh, eighth, ninth, and tenth contact portions 36, 37, and 3 for forming a flip-flop.
8, 39 are formed.

The first to sixth contact portions 30 to 35 are provided at positions corresponding to the outline of the memory cell 200. The first contact portion 30 is provided with the first driver Tr. Q1
Is provided so as to be connected to the diffusion layer 6. The second contact portion 31 is provided symmetrically with the first contact portion 30 with the gate electrode wirings 4 and 5 interposed therebetween, and the second driver Tr. It is formed so as to be connected to the diffusion layer 8 of Q2. Further, the third contact portion 32 is connected to the first load Tr.
The fourth contact portion 33 is connected to the diffusion layer 7 of Q2,
Load Tr. It is formed so as to be connected to the diffusion layer 9 of Q4. The third and fourth contact portions 32 and 33 are respectively
The first and second contact portions 30 and 31 are provided symmetrically with respect to the point O.

Fifth contact portion 34 for bit line 110
Is the first word Tr. The sixth contact portion 35 is formed so as to be connected to the diffusion layer 10 of Q5.
r. It is formed so as to be connected to the diffusion layer 11 of Q6. These fifth and sixth contact portions 34 and 35 are juxtaposed at intervals.

The seventh contact portion 36 is provided near the P ⁺ -type lead-out wiring 13 connected to the P-type diffusion layer 9 via the P ⁺ -type buried contact portion 15. That is, the seventh contact portion 36 is provided at a position surrounded by the gate electrode wiring 4 of the first inverter 101 and the lead-out wiring 13, and the first load T
r. It is formed so as to be connected to the diffusion layer 7 of Q2.
Similarly, the eighth contact portion 37 is connected to the second inverter 102
Is provided at a position surrounded by the gate electrode wiring 5 of the first driver Tr. It is formed so as to be connected to the diffusion layer 6 of Q3. The seventh and eighth contact portions 36 and 37 are arranged symmetrically about the point O.

On the other hand, the ninth contact portion 38 is connected to the extraction electrode 13 and the first driver Tr. It is provided at a position where the diffusion layer 6 of Q <b> 1 overlaps, and is formed so as to be connected to the extraction electrode 13. Similarly, the tenth contact portion 39 also includes the extraction electrode 14 and the second load Tr. Q4 is provided at a position where the diffusion layer 9 overlaps, and the extraction electrode 1 is provided.
4 is formed.

In the present embodiment, the contact holes constituting the first to eighth contact portions 30 to 37 are formed in a self-aligned manner by etching using the silicon nitride film 21 as an etching stopper film. Consist of things. Therefore, the first to eighth contact portions 30 to 37 are self-aligned contact portions (Self-Aligned Contacts) connected to the diffusion layers 6 to 11, respectively. The ninth and tenth contact portions 38 and 39 are connected to the extraction electrode 1.
The contact portions (Poly Conact) are connected to the first and third Poly-Si layers 17 and 18.

On the flattening film 22, first to tenth contact portions 30 to 39 are formed, and the first to first contact portions 30 to 39 are formed.
A flip-flop 100 is formed by providing a local wiring 40 for connecting predetermined ones of the 0 contact portions 30 to 39. The local wiring 40 forms a Vss line and a Vdd line.

Further, a local wiring 40 is formed on the planarizing film 22.
Is formed to cover the substrate. The interlayer insulating film 41 includes fifth and sixth contact portions 34 and 35
Bit line contact holes (not shown) are formed directly above the contact holes, and bit line contact portions 42 and 43 are formed by filling these contact holes with a conductive film such as W or Al. At the same time, a bit line 110 is formed on the interlayer insulating film 41.

Next, an example of a method for manufacturing the SRAM 1 having the above structure will be described with reference to FIGS. First, as shown in FIGS. 1 and 2, the first driver Tr. Q1, the first load Tr. Q2,
The second doilber Tr. Q3, the second load Tr. Q4, 1st
Word Tr. Q5, sixth word Tr. An element isolation film 24 is formed on the semiconductor substrate 3 so as to surround the formation region of Q6. In FIG. 1, a portion surrounded by a two-dot chain line which is an outline of the memory cell 200 and a broken line indicating the diffusion layers 6 to 11 is a portion where the element isolation film 24 is formed. Also NMOS
In addition, ion implantation for forming various wells necessary for forming a PMOS, ion implantation for forming a channel stop, ion implantation for adjusting Vth, and the like are performed.

Next, a gate oxide film 23 is formed on the exposed surface of the semiconductor substrate 3 by a known method, and subsequently, the semiconductor substrate is formed by, for example, a chemical vapor deposition method (hereinafter, referred to as a CVD method). The first Poly-Si film 17 having a thickness of several tens of nm is deposited on the entire surface of the substrate 3. Next, lithography technology (resist coating, exposure, development, baking, etc.)
An opening (not shown) is formed in the first Poly-Si film 17 at a position where the P ⁺ -type buried contact portion 15 and the N ⁺ -type buried contact portion 16 are formed by etching. As a result, the semiconductor substrate 3 is exposed at the bottom of the opening.

Next, a second Poly-Si layer 18 having a thickness of several tens of nm is deposited in the opening and on the first Poly-Si layer 17 by, for example, a CVD method. Then, the first and second Poly-Si layers 17 in the portion A at the position where the lead wiring 13 is formed and the position where the P ⁺ type buried contact portion 15 is formed as shown in FIG.
In FIG. 18, a P-type impurity is doped into P ⁺ (indicated by hatching in the figure), and the lead-out wiring 1 in the other region is doped.
The first and second Poly-Si layers 17 and 18 at the formation position of 3, the formation position of the lead wiring 14, the formation position of the gate electrode wirings 4 and 5, and the formation position of the word line 120 are doped with N-type impurities to N ⁺ . (Indicated by dots in the figure).

Next, WSi is formed on the second Poly-Si layer 18.
depositing a _x layer 19, depositing a silicon oxide film 20 to form a self-aligned contact hole to form a silicon oxide film 20 with a W- polycide on the WSi _x layer 19. After that, heat treatment is performed, and the first and second Poly-Si
The impurities doped in the films 17 and 18 are activated. The heat treatment is performed by, for example, RTA (Rapid Thermal Annealing) at 1000 ° C. for about 10 seconds. By this heat treatment, the second Po formed in the opening is formed.
N-type and P-type impurities diffuse from the ly-Si layer 18 into the semiconductor substrate 3, respectively.

Next, by patterning the W-polycide by etching, the gate electrode wirings 4 and 4 are formed.
5. Form the lead wirings 13 and 14 and the word line 120. Thus, in the same process, the gate electrode wirings 4 and
5 and lead wirings 13 and 14 are formed.

Note that the lead-out wiring 13 is connected to the P ⁺ -type buried contact portion 15 as shown in FIG. 3 by separately performing P-type impurities and N-type impurities in the previous ion implantation step.
The first and second Poly-Si layers 17 and 18 in the upper portion A are P ⁺
It is a mold region (indicated by hatching in FIG. 3). In addition, the lead wiring 13, the lead wiring 14, the gate electrode wirings 4 and 5, and the word line 120 in other portions are N
^{It is a +} type region (indicated by a dot in FIG. 3).

Thereafter, an N-type impurity is doped into the NMOS formation region of the semiconductor substrate 3 by ion implantation to form an N-type LDD (Lightly Doped Drain) region (not shown), and the P-type region is formed in the PMOS formation region. A P-type LDD region is formed by doping a type impurity. Then
After a Poly-Si film, for example, is formed on the entire surface of the semiconductor substrate 3, the Poly-Si film is etched to form side walls (not shown in the drawings) on the side walls of the gate electrode wires 4 and 5, the lead wires 13 and 14, and the word lines 120. ) Is formed.

Subsequently, N-type impurities are doped into the NMOS formation region of the semiconductor substrate 3 by ion implantation to form N ⁺ -type high-concentration diffusion layers 6, 8, 10, and 11. Also, the PMO of the semiconductor substrate 3 is formed by ion implantation.
By doping P-type impurity S formation region for forming a high-concentration diffusion layers 7 and 9 of the P ⁺ -type. And heat treatment,
The impurity doped in the semiconductor substrate 3 is activated.
By this heat treatment, the second poly of the gate electrode wirings 4, 5 is formed.
N-type and P-type impurities in the Si 18 further diffuse into the semiconductor substrate 3 through the opening, and the first driver Tr. Q
The N ⁺ -type buried contact layer 16 connected to the N-type diffusion layer 6 of the second load Tr. A P ⁺ type buried contact layer 15 connected to the P type diffusion layer 9 of Q4 is formed.

Next, the sidewalls are removed, and a silicon nitride film 21 is formed on the entire surface of the semiconductor substrate 3. Further, a flattening film 22 is formed on the silicon nitride film 21. Subsequently, contact holes for the first to tenth contact portions 30 to 39 are opened in the planarizing film 22, the silicon nitride film 21, and the silicon oxide film 20. At this time, the contact holes for the first to eighth contact portions 30 to 37 are formed in this embodiment in a self-aligned manner by etching the silicon nitride film 21 as an etching stopper film.

Next, as shown in FIGS. 2 and 4, Al, W
The first to tenth contact portions 30 to 39 are formed by filling each contact hole with a conductive film such as
Local wiring 40 connecting predetermined ones of 0 to 39
To form the flip-flop 100. At the same time, a Vdd line and a Vss line are formed by the local wiring 40. 2 and 5, an interlayer insulating film 41 is formed on the planarizing film 22 so as to cover the local wiring 40.
Is formed, a contact hole for the bit line 110 connected to the fifth and sixth contact portions 34 and 35 is formed in the interlayer insulating film 41. Then, the inside of the contact hole is buried with a conductive film such as Al to form a bit line contact portion 4.
2 and 43 are formed, and a bit line 110 is formed on the interlayer insulating film 41. Through the above steps, the SRAM 1
Is completed.

In the SRAM 1 manufactured as described above, P
^Since the lead wiring 13 on the ⁺ type embedded contact portion 15 is formed in a P-type, the lead wiring 13 and the second load Tr. The P-type diffusion layer 9 of Q4 can be connected via the P ⁺ -type buried contact portion 15 without forming a PN junction therebetween. Therefore, an increase in contact resistance due to the formation of the PN junction can be suppressed, and the operation of the SRAM 1 can be stabilized.

Since the connection between the lead-out wiring 13 and the diffusion layer 9 and the connection between the lead-out wiring 14 and the diffusion layer 6 are made via the P ⁺ type buried contact portion 13 and the N ⁺ type buried contact portion 16, respectively. In addition, it is possible to eliminate the need for a large-diameter divided contact hole as in the related art. As a result, the area of the memory cell 200 can be reduced. Moreover, the first load Tr. Q1 and the second load Tr. Since Q4 is formed of a buried channel type PMOS and the gate electrode wirings 4 and 5 in the memory cell 200 are all formed as N-type, the N-type first Poly-Si film 1 is formed.
7. By etching the second Poly-Si film 18, gate electrode wirings 4 and 5 can be formed. Therefore,
Since the gate electrode wirings 4 and 5 can be etched with high precision, the SRAM 1 of the present embodiment has extremely high productivity.

The portion A formed in the lead wiring 13 in the P ⁺ type is not used for the gate electrode wiring 5, so that no processing accuracy is required. Furthermore, since the lead-out wiring 13 is not used for the gate electrode wiring 5, boron is used as a P-type impurity.
There is no effect on the characteristics of AM1. For this reason, Vth can be prevented from fluctuating due to the penetration of the semiconductor substrate 3 by boron, and the process conditions restricted for measures such as thermal stress can be relaxed, so that the degree of freedom for the process conditions can be increased. According to the present embodiment, the SRAM 1 having very excellent device characteristics and productivity
Can be realized.

In the above embodiment, the gate electrode wiring,
Although the case where the lead wiring and the word line are formed of W-polycide has been described, it is needless to say that the present invention is not limited to this example. The deposition of a silicon oxide film on the WSi _x layer, but it is also possible to omit this step.

[0047]

As described above, in the semiconductor memory device of the present invention, the lead wiring on the P-type buried contact portion is formed of a P-type conductive film, and the lead wiring and the P wiring are formed without forming a PN junction. Since the configuration is such that the diffusion layer of the mold is connected via the P-type buried contact portion, the operation can be stabilized and the cell area can be reduced. Further, since all the gate electrode wirings are N-type, processing can be performed with high accuracy, and since a P-type lead-out wiring is not used for the gate electrode wiring, high processing accuracy is not required for this portion. Further, since the lead-out wiring is not used for the gate electrode wiring, even if boron which is a P-type impurity enters the semiconductor substrate due to the high-temperature heat treatment, there is no change in Vth, so that the degree of freedom for process conditions can be increased. . Therefore, according to the present invention, an SRAM excellent in device characteristics and productivity can be realized.

[Brief description of the drawings]

FIG. 1 is a plan view showing one embodiment of a semiconductor memory device according to the present invention.

2 is a X-X ₁ sectional view taken along the line in FIG.

FIG. 3 is a plan view for explaining an ion implantation region.

FIG. 4 is a plan view for explaining a local wiring forming step.

FIG. 5 is a plan view for explaining a step of forming a bit line.

FIG. 6 is a circuit diagram of a general SRAM.

FIG. 7 is a plan view showing an example of a conventional SRAM.

8 is a Y-Y ₁ a sectional view taken along line in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... SRAM, 3 ... Semiconductor substrate, 4,5 ... Gate electrode wiring, 6,9 ... Diffusion layer, 13,14 ... Extraction wiring, 15
... P ⁺ type buried contact part, 16 ... N ⁺ type buried contact part, 17 ... first Poly-Si layer, 18 ... second Po
ly-Si layer, 41, 42, 51, 52 ... gate electrode, 1
00: flip-flop, 101: first inverter, 1
02: second inverter, 200: memory cell, Q1: first driver Tr. , Q2... First load Tr. , Q3 ... Third
Driver Tr. , Q4... Second load Tr.

Claims (2)

[Claims] 1. A flip-flop comprising a pair of inverters is provided on a semiconductor substrate in a memory cell. Each of the inverters comprises an N-channel field-effect transistor and a P-channel field-effect transistor. Wherein the gate electrode of the field effect transistor and the gate electrode of the P channel field effect transistor are formed by a continuous N-type gate electrode wiring, and the field effect transistor constituting one of the pair of inverters A lead wiring extending from the gate electrode wiring of the transistor and a diffusion layer of the field effect transistor forming the other inverter are formed on the semiconductor substrate via a buried contact portion having the same conductivity type as the diffusion layer. In the semiconductor memory device connected, the diffusion layer The lead wiring connected to the N-type diffusion layer through the N-type buried contact portion is formed of an N-type conductive film, and the P-type buried contact portion is formed in the P-type diffusion layer of the diffusion layer. A lead wiring connected via a P-type buried contact portion is formed of a P-type conductive film. 2. The method according to claim 1, wherein the gate electrode wiring and the lead wiring are formed of a conductive film including at least a polysilicon layer, and a P-type impurity is introduced into the polysilicon layer in the lead wiring on the P-type buried contact portion. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed.