JPH1117596A - In-phase combination space diversity receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid effect at an inverse phase point of a dead band provided to improve noise improvement and improve a control speed for in-phase combination control in the in-phase combination space diversity receiver where a lead/ lag is discriminated based on a phase difference of two reception input signals so as to control the phase difference when both input signals are put together. SOLUTION: When a phase relation of two reception input signals S1, S2 is discriminated to be in an inverted phase range (90 deg.<Δθ<270 deg.) by a 2nd phase difference discrimination means 24, a phase shift amount control means 25 receiving the discrimination signal controls a phase shift means 21 to change the phase shift amount of the phase shift means by 180 deg. at that point of time. The phase control based on the discrimination result of the 1st phase difference discrimination means 23 is conducted always within an in-phase range (-90 deg.<Δθ<90 deg.), the effect of a dead band in an inverse phase point is not received and even in the case of phase control near an inverted phase with a high phase difference is converted to the in phase point at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-phase combining space diversity receiving apparatus, and more particularly to a phase comparator for detecting a phase difference between two received input signals and determining a leading or lagging phase between the received input signals to combine the signals. The present invention relates to an in-phase combined space diversity receiver for controlling a phase difference between received input signals at the time.

[0002]

2. Description of the Related Art Conventionally, a phase difference between two received input signals is detected by a phase comparator, a lead or a delay of the phase between the received signals is determined, and the phase of the received input signal is changed by a phase shifter. In the in-phase combined space diversity receiver, in order to improve the noise characteristics caused by controlling the phase of the received input signal, when determining the lead or lag of the phase by detecting the phase difference, the phase difference near the in-phase is determined. A dead zone in which it is not determined whether the phase shift is advanced or delayed is provided. In this range, the control of the phase shifter is stopped. Therefore, it is not possible to distinguish the phase difference between two received input signals between the time near the same phase and the time near the opposite phase only by the phase difference detection information by one phase comparator. A dead zone provided so as not to perform control causes a dead zone near the reverse phase, and control may be stopped by the dead zone near the reverse phase.

Conventionally, various proposals have been made to avoid such a control stop in a dead zone near the reverse phase. As an example of such an in-phase combined space diversity receiving apparatus, a block diagram of the apparatus described in Japanese Patent Application Laid-Open No. 2-237324 is shown in FIG. In the figure, the phase of a second received input signal S2 is controlled by an infinite phase shifter (EPS) 2, and the first received input signal S1 is an absolute delay amount from the respective inputs of the present receiver to the synthesis. Through a delay line 1 for matching the signals, the power combiner 3 controls and combines the received input signal S2 through the infinite phase shifter 2 so that it is always in phase, and the combined signal is shown in the figure. Is sent to a demodulator and demodulated to a baseband signal. On the other hand, the two input signals to the power combiner 3 are branched together, and each of them is divided into a band-pass filter (BPF) 4.
a, 4b and automatic gain control (AGC) amplifiers 5a, 5b
After that, one is branched and the other is directly input to the phase comparator 6b, and the other is 90 ° only on one input signal side.
The phase is changed by 90 ° by the phase shifter 7 and the phase comparator 6
is input to a.

Here, the phase comparison characteristics of the phase comparators 6a and 6b are as shown in FIG. 5 (a). In the phase comparator 6a, when two signals to be compared are in-phase and out-of-phase, the output becomes 0. Become. In the phase comparator 6b, the output of the two signals to be compared becomes positive near the same phase and becomes negative near the opposite phase. The output voltage Vo of the phase comparator 6a is compared with respective threshold voltages by two voltage comparators 8a and 8b. In the voltage comparator 8a, the first reception input signal Sl
Of the second reception input signal S2 with respect to the phase delay, and the voltage comparator 8b similarly obtains the detection signal with respect to the advance of the phase (FIGS. 5B and 5C). ). Based on the two control signals having the phase information, the EPS control circuit 20 controls the infinite phase shifter (EPS) 2
And the phase of the second received input signal is changed to perform in-phase synthesis.

By the way, when the output voltage Vo of the phase comparator 6a satisfies + Vth>Vo> -Vth, FIG.
As shown in (b), there is a range in which no phase advance or delay is detected in the two voltage comparators 8a and 8b, that is, a range in which no phase difference is detected, which is a dead zone in which phase control is not performed. This is because, if the phase control of the received input signal is performed by the infinite phase shifter 2, the combined wave becomes a factor of noise, and the fluctuation of the phase deteriorates the error rate characteristic of the entire receiving apparatus. is there.
Therefore, the phase comparator 6b has a phase comparison characteristic that is 90 ° out of phase with the phase comparison characteristic of the phase comparator 6a, and its output voltage Vo is determined to be positive or negative by the voltage comparator 8c.
As a result, an in-phase / negative-phase determination signal indicating whether it is close to the in-phase point or the anti-phase point is obtained (FIG. 5D). This same phase /
The two voltage comparators 8 a and 8 b
To the threshold voltages + Vth and -Vth.

That is, when the phase difference Δθ between two received input signals is in the vicinity of the same phase (−90 ° <Δθ <90 °), the respective threshold voltages + Vth and −Vth
Is applied with a constant voltage having the opposite polarity, and the phase difference Δθ between the two received input signals is close to the opposite phase (90 ° <Δθ <
By setting the respective threshold voltages to + Vth = −Vth = 0 in the range of (270 °), the dead zone disappears near the reverse phase, and the stop of the phase control near the reverse phase is prevented. . Here, the inversion buffer 18 has the same magnitude as the output voltage + Vth of the voltage comparator 8c, and has a threshold voltage −Vt obtained by inverting only the polarity.
h is supplied to the voltage comparator 8b.

As an example of the configuration of the EPS control circuit 20, a clock generator 10 for generating a clock signal defining a control speed for controlling the phase shift amount of the infinite phase shifter 2, Voltage comparators 8a, 8b
The two A's for outputting a clock pulse at the time of phase advance and at the time of phase delay, respectively, by taking the logical product of the phase advance detection signal and the phase delay detection signal from
ND gates 9a and 9b and an n-bit UP that counts up when a phase leading clock pulse is input and counts down when a phase delayed clock pulse is input.
/ DOWN counter 11, two ROMs 12 a and 12 b for reading m-bit data already stored using n-bit output data of the UP / DOWN counter 11 as an address input, and read from each ROM. enter the m-bit data, by the digital / analog converter, respectively, the infinite phase shifter 2 for two analog voltages, orthogonal to the in-phase vector control voltage V _X vector control voltage V _Y and D / a conversion to give Table 13
a and 13b.

[0008]

In this conventional device,
Since the control speed of the phase shift amount of the infinite phase shifter 2 for phase control is always constant irrespective of the detected phase difference, the phase difference between the fixed received input signals is shifted to the in-phase state. A time proportional to the phase difference is required to control the phase difference. Therefore, in the phase control from the vicinity of the opposite phase where the phase difference is large, there is a problem that it is difficult to quickly converge to the in-phase point.

It is an object of the present invention to set a dead zone for improving noise characteristics when the phase difference between two reception inputs is near the in-phase, and to set the phase shift amount of the infinite phase shifter when the phase difference is near the opposite phase. It is an object of the present invention to provide an in-phase combined space diversity receiver capable of performing a phase control with higher speed follow-up performance by changing the speed from a constant speed.

[0010]

An in-phase combined space diversity receiver according to the present invention detects a phase difference between received signals input from two antennas and determines a phase lead / lag by a first phase difference determination. Means, phase shifting means for changing the phase of one of the received signals, synthesizing means for synthesizing the one received signal and the other received signal whose phase is controlled by the phase shifting means, Second phase difference determining means for determining whether the phase difference between the received signals is near the in-phase or near the opposite phase, and the phase difference between the received signals is made in-phase based on the output of the first phase difference determining means. And a phase shift amount control means for controlling the phase shift means and correcting the phase shift amount of the phase shift means based on the determination result of the second phase shift difference determination means.

Here, the phase shift amount control means changes the phase difference obtained by the first phase difference determination means by 180 ° when the second phase difference determination means determines the reverse phase. It is configured to control the phase shifting means. For example,
The phase shift amount control means counts based on a phase lead / lag determination result from the first phase shift difference determination means.
A P / DOWN counter; and a storage circuit that outputs a phase shift amount signal for controlling the phase shift means based on an output of the UP / DOWN counter. When the judgment signal is input, the U
There is provided changing means for changing the output of the P / DOWN counter and changing the output from the recording circuit to an output for shifting the phase by 180 °.

In this configuration, when the second phase difference determination means determines that the phase relationship between the two received input signals is in the opposite phase range (90 ° <△ θ <270 °), the current phase difference is determined. Since the phase shift amount of the phase shifting means is changed by 180 °, the phase control is always performed in the in-phase range (−90 ° △ θ <90 °), and the influence of the dead zone at the opposite phase point is eliminated. Further, it is possible to converge to the in-phase point at high speed even in the phase control from near the reverse phase where the phase difference is large.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a conceptual configuration of an in-phase combined space diversity receiver according to the present invention. In the figure, the phase difference between the received signals S1 and S2 input from the two antennas is detected, and the phase advance /
A first phase difference determining means 23 for determining a delay, a phase shifting means 21 for changing one phase of the received signals, and two received signals of which one phase difference is controlled by the phase shifting means 21 Combining means 22 for combining, second phase difference determining means 24 for determining whether the phase difference between the received signals is near the in-phase or near the opposite phase, and receiving based on the output of the first phase difference determining means 23 Control the phase difference between the signals so that they are in phase,
And a phase shift amount changing means 25 for changing the phase shift amount of the phase shift means 21 by 180 ° based on the judgment result of the second phase difference judging means 24.

According to this configuration, the second reception input signal S2 whose phase has been changed through the phase means 21 is power-combined with the first reception input signal S1 by the combination means 22 and output. Further, the two received input signals S1 and S2 input to the synthesizing unit 22 are branched and input to the first phase difference determining unit 23 and the second phase difference determining unit 24, respectively. The first phase difference determination means 23 detects the lead / lag of the phase difference between the two received input signals S1 and S2, and outputs a phase lead detection signal and a phase delay detection signal. Further, the second phase difference judging means 24 detects whether the phase difference between the two received input signals is near the in-phase or near the opposite phase, and outputs it as an in-phase / out-of-phase judgment signal. And
In the phase shift amount control means 25, the first phase difference determination means 2
3, the phase advance detection signal and the phase delay detection signal are input, and the amount of phase shift in the phase shift means 21 is controlled so that the two reception input signals S1 and S2 are in-phase synthesized by the synthesis means 22. The phase shifter 21 outputs a phase amount control signal and outputs the phase shifter 21 based on the in-phase / out-phase determiner signal from the second phase difference determiner 24.
Is changed by 180 ° from the current phase shift amount.

FIG. 2 is a block diagram of a first embodiment of the in-phase combined space diversity receiver according to the present invention, which embodies the configuration of FIG. Parts equivalent to those in the conventional configuration shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 2, two received input signals S1, S2
Is detected in the in-phase range (−90 ° <△ θ <90 °) or the out-of-phase range (90 ° <＜ θ <270 °),
A phase comparator 6a for detecting the advance or delay of the phase as the first phase shift difference judging means, and a 90 ° phase comparison characteristic difference with respect to the phase difference between the received input signals as the second phase shift difference judging means. A phase comparator 6b is provided, and the polarity of the output voltage is determined by a voltage comparator 8c to obtain an in-phase / negative-phase determination signal. In the conventional example, the threshold voltages + Vth and -Vth of the two voltage comparators 8a and 8b for determining the lead / lag of the phase based on the in-phase / out-phase determination signal are controlled to reduce the dead zone near the reverse phase. In the present invention, the ROM 12 determines the phase shift amount of the infinite phase shifter 2 based on the in-phase / out-phase determination signal.
By manipulating the address signals to a and 12b, the amount of phase shift at the time of reverse phase is changed.

A toggle inversion circuit 14 is used as a means for changing the amount of phase shift at the time of reverse phase. That is, the amount of phase shift in the infinite phase shifter 2 is determined by the output of the n-bit UP / DOWN counter 11, and the amount of phase shift from 0 ° to 360 ° is equally divided into 2n operating points. The output of the / DOWN counter 11 is designated as an address. At each operating point, mutually orthogonal vectors to the infinite phase shifter 2 are controlled. ROM for two control voltages
The data stored in 12a and 12b is read out and generated by D / A converters 13a and 13b. Then, in order to change the phase shift amount in the infinite phase shifter 2 by 180 ° in the reverse phase range (90 ° <△ θ <270 °), here, in order to increase the phase shift amount by 180 °, the infinite phase shifter is used. UP / DOWN counter 1 which is an address for specifying the phase shift amount 2
The toggle inversion circuit 14 inverts the most significant bit (MSB) of the output of "1". That is, when the phase difference of the received input signal is in the opposite phase range, the phase difference is changed by 180 ° and moved to the in-phase range.

Here, the toggle inverting circuit 14 logically inverts the address input once during the in-phase range of the in-phase / out-phase determination signal, and maintains this inverted state until the next in-phase range is entered. FIG. 3 shows an example of this configuration. In FIG. 3, an exclusive OR gate 15 for inverting the address signal from the UP / DOWN counter 11 in the opposite phase is used.
And an inverter 17 and a D flip-flop 16 for inverting and holding the output only once during the in-phase range time of the in-phase / out-phase determination signal. That is, the exclusive OR gate 15 toggles whether the input address signal is inverted or non-inverted by the output of the D flip-flop 16 which performs the toggle operation in which the state is inverted every time an input is made. Is changing.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing the configuration of a second embodiment of the in-phase combined space diversity receiving apparatus according to the present invention. In FIG. 4, parts equivalent to those in FIG. 4 differs from the first embodiment shown in FIG. 2 only in the configuration of the EPS control circuit 19 having the phase shift amount changing function. First,
In order to change the amount of phase shift in the reverse phase range, in this embodiment, a monostable multipipelator for supplying a load pulse signal to the UP / DOWN counter 11 based on an in-phase / out-phase determination signal from the voltage comparator 8c. 26. Also, bits other than the most significant bit in the output of the UP / DOWN counter 11 are the same UP / DOWN as they are.
The input data is fed back as the load data input of the N counter 11, and the most significant bit is fed back as the load data input of the UP / DOWN counter 11 like the other bits after being inverted by the inverter 17.

That is, when the in-phase / negative-phase determination signal has a reverse phase range, in this case, when it is at the L level according to FIG.
By supplying a single load pulse to the UP / DOWN counter 11 by the monostable
The load data input to the P / DOWN counter 11 is taken in, and the counter value is preset. UP / D immediately before the preset counter value enters the reverse phase range
By setting only the most significant bit of the output of the OWN counter to an inverted value, it is possible to change the phase shift amount by 180 °.

[0020]

As described above, according to the present invention, when it is determined that the phase difference between two received input signals is in the reverse phase range, the phase shift amount control means controls the phase shift means to control the phase difference. Is changed by 180 °, the phase difference is always shifted to the in-phase range. As a result, the phase control is always performed within the in-phase range, the influence of the dead zone at the opposite phase point is eliminated, and the reliable phase control can be always performed. Also, by being moved from the opposite phase range where the phase difference between the two received input signals is large to the in-phase range where the phase difference is small,
Even when the phase shifter control speed is the same as that of the related art, it is possible to exhibit higher tracking performance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conceptual configuration of the present invention.

FIG. 2 is a block circuit diagram according to the first embodiment of the present invention.

FIG. 3 is a block circuit diagram illustrating an example of a toggle inversion circuit;

FIG. 4 is a block circuit diagram according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating output characteristics of a phase shift comparator and a voltage comparison.

FIG. 6 is a block circuit diagram of an example of a conventional receiving device.

[Explanation of symbols]

 Reference Signs List 1 delay line 2 infinite phase shifter (EPS) 3 power combiner 5a, 5b AGC amplifier 6a, 6b phase comparator 7 90 ° phase shifter 8a, 8b, 8c voltage comparator 11 UP / DOWN counter 12a, 12b ROM 14 Toggle inversion circuit 15 Exclusive OR gate 20 EPS control circuit 21 Phase shift means 22 Combining means 23 First phase difference determination means 24 Second phase difference determination means 25 Phase shift amount control means 26 Monostable multivibrator

Claims (5)

[Claims] A first phase difference judging means for detecting a phase difference between received signals inputted from two antennas and judging a lead / lag of a phase, and determining a phase of one of the received signals among the received signals. Phase shifting means for changing, the synthesizing means for synthesizing the one received signal and the other received signal whose phases are controlled by the phase shifting means, and determining whether the phase difference between the received signals is near the same phase or near the opposite phase. A second phase difference judging means for judging the first phase difference;
Controlling the phase shifting means so that the phase difference between the received signals becomes the same phase based on the output of the phase difference determining means, and based on the determination result by the second phase difference determining means. And a phase shift amount control means for correcting the phase shift amount. 2. The method according to claim 1, wherein the phase shift amount control means changes the phase shift obtained by the first phase shift difference determining means by 180 ° when the second phase difference determining means determines the reverse phase. 2. The in-phase combined space diversity receiver of claim 1, wherein the receiver is configured to control the phase shifting means. 3. The UP / DOWN counter which counts according to a phase lead / lag determination result from the first phase shift difference determining means, and an UP / D counter.
A storage circuit for outputting a phase shift amount signal for controlling the phase shift means in accordance with an output of the OWN counter, wherein when the reverse phase determination signal is input from the second phase shift difference determination means, The output of the UP / DOWN counter is changed, and the output from the recording circuit is changed by 180 °
3. The in-phase combined space diversity receiving apparatus according to claim 2, further comprising a change unit that outputs an output for shifting the phase. 4. The in-phase combined space diversity receiving apparatus according to claim 3, wherein said changing means comprises a toggle determination circuit for inverting a part of a bit signal output from said UP / DOWN counter. 5. The in-phase combining space according to claim 3, wherein said changing means is a load pulse signal generation circuit for presetting a bit signal output from said UP / DOWN counter to a value obtained by inverting a part of the bit signal. Diversity receiver.