JPH11203104A - Memory controller - Google Patents

Abstract

[PROBLEMS] To control data input / output to / from a buffer memory with a small-capacity buffer memory and a small hardware scale even when the number of input / output data to / from the buffer memory is not periodic. SOLUTION: The number of input data is counted by a write counter 4, the number of output data is counted by a write counter 5, and a memory control circuit 6 compares coincidence / mismatch of count values of both counters. Read counter 5
Generates a flag that is reset when the circuit makes one round, and based on the comparison result and the value of the flag, the buffer memory 2
If the state just before overflowing is detected, data input is restricted, and if the state just before underflow is detected, data output is restricted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for converting a data transfer rate using a memory.

[0002]

2. Description of the Related Art FIG. 10 is a block circuit diagram showing a conventional memory control device. The memory control device of FIG. 10 stores input data once in the memory and then reads the data from the memory at a timing different from that at the time of input. In FIG.
51 is an input terminal, 52 is a FIFO memory, 53 is an output terminal, 54 is a write data counter, and 55 is a read data counter.

Next, the operation will be described. FIG. 11 is an operation timing chart of a conventional memory control device, and is an example of a case where digital image data input in units of lines is handled. As shown in FIG. 11, data for one continuous line (720 data) is written to the FIFO memory 52 via the input terminal 1. The data written in the FIFO memory 52 on a line-by-line basis is read out divided into 16 data units.

The number of data written to the FIFO memory 52 is counted by a write data counter 54. In synchronization with a start pulse representing the head of one line,
The write data counter 54 controls the write operation so that 720 consecutive data are written to the FIFO memory 52.

On the other hand, the read data counter 55 controls the data in the FIFO memory 52 to be read in units of 16 data with a delay of 8 clocks from the start pulse. In reading data, a mask period for two clocks is provided for every 16 data.

As shown in FIG. 11, in the case of image data, data of 720 pixels per line is continuously input.
There is a blanking period of 858-720 = 138 clocks between each line. Therefore, even if data that is continuously input to 720 pixels is read out by providing a mask period for two clocks for every 16 data, the data can be absorbed in the blanking period between lines.

[0007]

However, the above conventional memory control device is configured on the assumption that the number of data written to the FIFO memory and the number of data read from the FIFO memory are the same within a certain period of time. Therefore, there is a problem that when data input / output to / from the FIFO memory is not periodic, control of data read / write to / from the FIFO memory cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described conventional problems. Even when the relationship between the number of input / output data with respect to the buffer memory is not periodic, a small-capacity buffer memory and a small hardware It is an object of the present invention to provide a memory control device capable of controlling data input / output to / from a buffer memory on a large scale.

[0009]

According to a first aspect of the present invention, there is provided a memory control device, comprising: an n-bit input counter for counting input data; an n-bit output counter for counting output data; Means for comparing the count values of the input counter and the output counter; and setting a flag to "1" when the input counter makes one cycle;
The flag is set to “0” when the output side counter makes one round.
Detecting that the count value of the input counter matches the count value of the output counter and that the flag has become “1” based on the comparison result by the comparing means and the flag value. Then, means for restricting the input of data to the buffer memory, based on the result of comparison by the comparing means and the value of the flag, the count values of the input counter and the output counter match,
Means for restricting the output of data from the buffer memory when detecting that the flag has become "0", and controls the input and output of data to and from the buffer memory.

According to a second aspect of the present invention, there is provided a memory control device comprising:
2. The memory control device according to claim 1, wherein the input-side counter counts an input data block composed of m (m is an integer of 2 or more) data, and the output-side counter is composed of m data. Blocks are counted, and input / output of data blocks to / from the buffer memory is controlled.

According to a third aspect of the present invention, there is provided a memory control device comprising:
2. The memory control device according to claim 1, wherein the buffer memory is a single-port memory, and includes means for switching a data input / output path to / from the buffer memory; Control the output.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Next, Embodiment 1 of the present invention will be described. FIG. 1 is a block circuit diagram of the memory control device according to the first embodiment. In the figure,
1 is a signal generation circuit, 2 is a buffer memory, 3 is a signal processing circuit, 4 is a write counter, 5 is a read counter, and 6 is a memory control circuit.

The signal generation circuit 1 sequentially inputs (writes) data subjected to digital signal processing internally to the buffer memory 2 and issues a data input signal to the write counter 4 when inputting data. Further, the signal processing circuit 3 performs signal processing on the data output (read) from the buffer memory 2 and issues a data output signal to the read counter 5 when outputting the data. The buffer memory 2
Is composed of a FIFO memory having a capacity of 2 ⁿ bits or more, temporarily stores data input from the signal generation circuit 1, and outputs the data to the signal processing circuit 3.
The above n is the number of bits of the write counter 4 and the read counter 5, and is a positive integer. Here, the capacity of the buffer memory 2 is assumed to be 2 ^8-bit (n =
8). Note that the signal generation circuit 1 may be a circuit that inputs data to the buffer memory 2, and the signal processing circuit 3 may be a circuit that inputs data output from the buffer memory 2. Further, the signal generation circuit 1 and the signal processing circuit 3 may be provided outside the memory control device.

The write counter 4 is composed of an n-bit counter, and counts up the number of data input to the buffer memory 2 by counting up a data input signal from the signal generation circuit 1, and counts the number of data input to the buffer memory 2. The count value WCUT and the carry bit WCY generated when the n-bit counter makes one cycle (from “0” to “1”) are output to the memory control circuit 6. The read counter 5 is composed of an n-bit counter, like the write counter 4, and counts up the number of data output from the buffer memory 2 by counting up the data output signal from the signal processing circuit 3. , And the carry bit RCY generated when the n-bit counter makes one cycle (changes from “0” to “1”) is output to the memory control circuit 6. Here, since the write counter 4 and the read counter 5 are 8-bit counters, the WCUT and the RCUT are issued when the count value returns from “FF” to “0”.

[0015] The memory control circuit 6 is based on WCUT and WCY output from the write counter 4 and RCUT and RCY output from the read counter 5.
When it is detected that the write counter 4 has caught up with the read counter 5 by making a round, an input wait signal W-WAIT is issued to the signal generation circuit 1 to stop data input to the buffer memory 2 by the signal generation circuit 1. .
When detecting that the read counter 5 has caught up with the write counter 4, it issues an output wait signal R-WAIT to the signal processing circuit 3 to stop the data processing circuit 3 from outputting data from the buffer memory 2.
In this case, the memory control circuit 6 stops the data input to the buffer memory 2 when the buffer memory 2 overflows when trying to input data to the buffer memory 2 any more, and outputs data from the buffer memory 2 any more. If an attempt is made to make the buffer memory 2 underflow, the data output from the buffer memory 2 is stopped.

FIG. 2 is a block circuit diagram showing a configuration of the memory control circuit 6. In FIG. 2, the memory control circuit 6
Is composed of a comparison circuit 11, a determination circuit 12, a write control circuit 13, and a read control circuit 14.

The comparison circuit 11 is an n-bit comparison circuit that compares the values of WCUT and RCUT bit by bit.
When UT = RCUT, “1” is set as the comparison result, and when WCUT ≠ RCUT, “0” is set as the comparison result. The comparison result is output to the write control circuit 13 and the read control circuit 14, respectively.

The discrimination circuit 12 includes an overtaking discrimination flag TF
A 1-bit register (referred to as a TFF register) for storing F is provided, and W is issued when the value of the WCUT makes one cycle.
When CY is input, TFF is set to “1” and RCU
When the RCY issued when the value of T makes one cycle is input, the TFF is reset to "0", and this TFF is output to the write control circuit 13 and the read control circuit 14, respectively. The discrimination circuit 12 sets TFF to "0" when the power is turned on or reset.

The write control circuit 13 calculates a comparison result from the comparison circuit 11 and a TFF from the discrimination circuit 12 based on the comparison result.
When WCUT = RCUT and TFF = 1, the write counter 4 makes a round and catches up with the read counter 5, so it is determined that an overflow will occur if more data is input to the buffer memory 2, and the signal generation circuit 1 Issue an input wait signal W-WAIT (W-WAIT
IT is set to “1”), and the data input to the buffer memory 2 by the signal generation circuit 1 is stopped. WCUT @ RCU
If T or TFF = 0, no W-WAIT is issued (W-WAIT is set to "0").

The read control circuit 14 calculates the comparison result from the comparison circuit 11 and the TFF from the discrimination circuit 12 based on the comparison result.
When WCUT = RCUT and TFF = 0, the read counter 5 has caught up with the write counter 4, and it is determined that an underflow will occur if data is read from the buffer memory 2 any more, and output to the signal processing circuit 3. A wait signal R-WAIT is issued (R-WAIT is set to "1"), and a buffer memory 2
Stop data output from. If WCUT @ RCUT or TFF = 1, no R-WAIT is issued (R-WAIT
-WAIT is set to "0").

Next, the operation will be described. FIG. 3 and FIG.
FIG. 3 is an operation timing chart of the memory control device according to the first embodiment. FIG. 3 shows a state in which a W-WAIT is issued, and FIG. 4 shows a state in which an R-WAIT is issued. 3 and 4, (a) is a basic clock for data input (data write) operation to the buffer memory 2 and data output (data read) operation from the buffer memory 2;
(B) is the input data to the buffer memory 2, (c) and (d) are the WCUT and WCY by the write counter 4,
(E) is output data from the buffer memory 2, (f) and (g) are RCUT and RCY by the read counter 5.
It is. (H) is a TFF by the discrimination circuit 12,
(I) is a comparison result by the comparison circuit 11, (j) is a W-WAIT by the write control circuit 13, and (k) is an R-WAIT by the read control circuit 14.

In FIG. 3, data D0 to D201 are successively input from the signal generation circuit 1 to the buffer memory 2. In the next two clock periods after the input period of the data D201, the write control circuit 13 issues the input wait signal W-WAIT (W-WAIT =
1), and data input by the signal generation circuit 1 is restricted, so that no data is input to the buffer memory 2 (see (b)). The count value WCUT of the number of input data by the write counter 4 is sequentially incremented from “0” to “FF” in the input period of the data D0 to DFF, and returns to “0” when the data D100 is input. , During the input period of the data D100 to D1FF, and when the data D200 is input, the data D100 goes around once again to return to “0” and return to the data 201.
Is input, the value is incremented to “1” and data 2
It is held at "1" in the next two clock periods after the input period of 01 (see (c)). The carry bit WCY of the input data count by the write counter 4 is WCUT
Becomes "1" in the input period of the data DFF and D1FF in which "1" becomes "FF" (see (d)).

In the input period of the data D0, D1, D104 to D201, the signal processing circuit 3
Is not requested to output data, and therefore no data is output from the buffer memory 2. In the input period of the data D2 to D103, the data D0 to D101 are continuously and sequentially output from the buffer memory 2 in response to a request from the signal processing circuit 3. The data D102 is output from the buffer memory 2 two clock periods after the input period of the data D201 (see (e)). The count value RCUT of the number of output data by the read counter 5 is data D0 to DFF
Are sequentially incremented from "0" to "FF" in the output period of "1", return to "0" once when the data D100 is output, and are incremented to "1" when the data D101 is output, and the data D102 are output. Is held at "1" until the data is output, and is incremented to "2" when the data D102 is output (see (f)). The carry bit RCY of the output data count by the read counter 5 becomes “1” during the output period (input period of the data D101) of the data DFF in which the RCUT is “FF” (see (g)).

Overtaking determination flag T by determination circuit 12
The FF is set to “1” when the data D100 is input by WCY during the input period of the data DFF, and the data DFF is set to “1”.
It is reset to “0” when data D100 is output by RCY in the output period of FF, and is “1” when data D200 is input by WCY in the input period of data D1FF.
(See (h)). The comparison result by the comparison circuit 11 is “0” because WCUT ≠ RCUT during the input period of the data D0 to D200, and the data D20
When 1 is input, the WCUT is incremented to "1" and WCUT = RCUT, so that the WCUT changes to "1" in the next clock period after the input period of the data D201, and the data D
When 102 is output, the RCUT is incremented to "2" and WCUT ≠ RCUT, so that the data D102
Returns to "0" in the clock period following the output period of (i).
reference).

The input weight signal W-WAIT from the write control circuit 13 is TFF = 1 and WCUT = RCUT
(The period when the comparison result is “1”), that is, the data D2
01 clock period and data D102
(1) during the output period (see (j)), thereby limiting the data input from the signal generation circuit 1.
The output wait signal R-
WAIT is always "0" since there is no period during which TFF = 0 and WCUT = RCUT (see (k)), so that the signal processing circuit 3 is not restricted.

In FIG. 4, data D0 to D102 are sequentially and sequentially input from the signal generation circuit 1 to the buffer memory 2. Further, the signal generation circuit 1 does not input data to the buffer memory 2 during three clock periods following the input period of the data D102. The data D is stored in the buffer memory 2 four clock periods after the input period of the data 102.
103 is input (see (b)). Data D0 to D1
The waveforms (c) to (k) in the input period 02 are the same as those in FIG.

The WCUT is held at "2" in the next three clock periods after the input period of the data D102, and is incremented to "3" when the data D103 is input (see (c)). WCY is held at “0” after the input period of the data D100 (see (d)).

In the next two clock periods after the output period of the data D100, the data D101 and D102 are sequentially and sequentially output from the buffer memory 2. Data D
In the next two clock periods after the output period of 102, the read control circuit 14 outputs the output wait signal R-WAIT.
Is issued (R-WAIT = 1), and the data output request by the signal processing circuit 3 is restricted, so that no data is output from the buffer memory 2 (see (e)).
RCUT is sequentially incremented from “0” to “FF” during the output period of the data D0 to DFF,
When data D101 is output, it is incremented to "1", data D102 is output and incremented to "2", and held at "2" in the next two clock periods after the output period of data D102 (see (f)). ). RCY
Is held at "0" after the output period of the data D100 (see (g)).

The overtaking determination flag TFF is set to the data D1
It is reset to "0" after the input period of 02 (the output period of the data D100) (see (h)). The comparison result by the comparison circuit 11 is “0” because WCUT ≠ RCUT during the input period of the data D0 to D200. When the data D102 is output, the RCUT is incremented to “2” and WCUT = RCUT. It changes to “1” in the clock period following the output period of D102, and when data D103 is input, the WCUT is incremented to “3” and WCUT ≠ RCUT, so in the clock period following the input period of data D201. It returns to "0" (see (i)).

R-WAIT is TFF = 0 and WCUT
= RCUT (the comparison result is “1”), that is, “1” in the clock period next to the output period of the data D102 and the input period of the data D201 (see (k)), whereby the signal processing circuit 3 Data output requests are limited. Note that W-WAIT is always “0” because there is no period in which TFF = 1 and WCUT = RCUT.
(See (j))), so that the signal generation circuit 1 is not restricted.

As described above, according to the first embodiment, the number of input data and the number of output data are counted by the write counter 4 and the read counter 5, respectively, and the count value WCUT of the write counter 4 and the count value RCUT of the read counter 5 are counted. The comparison circuit 11 compares the coincidence / non-coincidence, and the overtaking determination flag T is set by the determination circuit 12 to “1” when the write counter 4 makes one cycle and reset to “0” when the read counter 5 makes one cycle.
An FF is generated, the read control circuit 13 detects a state immediately before the buffer memory 2 overflows based on the comparison result by the comparison circuit 11 and the overtaking determination flag TFF, restricts data input, and the write control circuit 14 By detecting the state immediately before the memory 2 underflows and restricting the data output, asynchronous input / output data control for the buffer memory 2 can be realized with a small buffer memory capacity. Furthermore, since the state of the buffer memory 2 can be detected by a simple algorithm, control of asynchronous input / output data for the buffer memory 2 can be realized with a small hardware scale, and the time required for determination is short. A memory control device capable of high-speed operation can be realized.

Although the first embodiment uses a FIFO memory as the buffer memory 2, the FIFO memory is not necessarily used.
It does not need to be a memory, and a dual port memory may be used. In the first embodiment, input and output of data to and from the buffer memory 2 are performed by the same clock. However, it is not always necessary to use the same clock.
Different clocks having different speeds may be used for data writing and data reading.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described. In the first embodiment, data control is performed for each data. However, a data block including m (m is an integer of 2 or more) continuous data, for example, a data block in which data is continuous such as image data Is configured in units of lines, the algorithm can be simplified by managing the data in the buffer memory in units of lines. The memory control device according to the second embodiment handles data blocks in line units. Here, the number m of data for one line is 510
And Note that 510 consecutive data D0 to D1FE (data block) for one line are simply referred to as line data.

The block circuit diagram of the memory control device according to the second embodiment is basically the same as that of FIGS.
The following points are different. The signal generation circuit 1 inputs line data composed of m continuous data to the buffer memory 2 and issues a line data input end signal WEND to the write counter 4 when the last data of one line is input. The signal processing circuit 3 outputs the line data composed of m pieces of continuous data from the buffer memory 2, and when the last data of one line is output, the read counter 5
Issue a line data output end signal REND. The write counter 4 counts the number of line data input to the buffer memory 2 by counting up WEND. Read counter 5 is R
By counting up END, the number of line data output from the buffer memory 2 is counted. The write counter 4 and the read counter 5
Is a 2-bit counter, and the comparison circuit 11 is also a 2-bit comparison circuit (n = 2). Therefore, the capacity of the buffer memory 2 only needs to be equal to or more than the number of data of one line m × 22 ² bits.
× 2 ² bits. Further, the memory control circuit 6 outputs W signals from the write counter 4 and the read counter 5.
The line data in the buffer memory 2 is managed based on CUT, RCUT, WCY, and RCY.

Next, the operation will be described. FIGS. 5 and 6 are operation timing diagrams of the memory control device according to the second embodiment. FIG. 5 shows how a W-WAIT is issued.
Indicates that an R-WAIT is issued. 5 and 6
(A) is a basic clock, (b) is input data, (c) is a line data input end signal WEND,
(D) is a count value WCUT of the number of input line data,
(E) is the carry bit WCY of the WCUT, (f) is the output data, and (g) is the line data output end signal REN.
D, (h) are count values RCU of the number of output line data
T, (i) is carry bit RCY of RCUT, (j)
Is an overtaking determination flag TFF, (k) is a comparison result by the comparison circuit 11, and (l) is an input weight signal W-WAI.
T, (m) is an output weight signal R-WAIT.

In FIG. 5, line data D0 to D1FE for one line are sequentially input from the signal generation circuit 1 to the buffer memory 2 at intervals (see (b)). WE
ND becomes "1" in the input period of the last data D1FE of each line data (see (c)). W
The CUT is incremented from “2” to “3” when the input of the data D1FE on the 4N + 2 (N is a positive integer) line is completed, and goes to “0” once the input of the data D1FE on the 4N + 3 line is completed. When the input of the data D1FE of the 4N + 4th line is completed, the value is incremented to "1" (see (d)). WCY is the data D1 of the 4N + 3 line where the WCUT returns from “3” to “0”.
It becomes "1" during the FE input period (see (e)).

The line data for one line is sequentially output from the buffer memory 2 at intervals according to a request from the signal processing circuit 3. The output line data is data input to the buffer memory 2 before the line data input simultaneously. Also, during the line data input period of the 4N + 4th line, the signal processing circuit 3 does not request the buffer memory 2 to output data.
Therefore, no line data is output from the buffer memory 2 (see (f)). REND becomes "1" during the output period of the last data D1FE of each line data (see (g)). The RCUT loops from “3” to “0” when the output of the data D1FE of the 4N−1th line ends, and is incremented to “1” when the output of the data D1FE of the 4Nth line ends ((h )reference). RCY indicates that the RCUT returns from “3” to “0” 4
It becomes "1" during the output period of the data D1FE of the (N-1) th line (see (i)).

The overtaking determination flag TFF is reset from "1" to "0" when the output of the data D1FE is completed by the RCY in the output period of the 4N-1 line, and 4N +
When the input of the data D1FE is completed by the WCY in the input period of the third line, it is set to “1” (see (j)). The comparison result by the comparison circuit 11 is “0” because WCUT ≠ RCUT until the input period of the 4N + 4th line ends, and when the input period of the 4N + 4th line ends, the WCUT is incremented to “1” and WCUT =
Since it becomes RCUT, it changes to “1” (see (k)).

The input weight signal W-WAIT is TFF
= 1 and WCUT = RCUT (comparison result is “1”), that is, a period after the input period of the 4N + 4th line ends (refer to (1)). Data entry is restricted.
The output wait signal R-WAIT is always “0” because there is no period during which TFF = 0 and WCUT = RCUT.
(See (m)), so that the signal processing circuit 3 is not restricted.

In FIG. 6, line data for one line is sequentially input at intervals (see (b)). WE
ND becomes "1" in the input period of the last data D1FE of each line data (see (c)). W
When the input of the data D1FE on the 4N + 3 line is completed, the CUT loops from “3” to “0” and returns to 4N + 4.
When the input of the data D1FE of the line is completed, it is incremented to "1" (see (d)). WCY is WC
The UT becomes “1” during the input period of the data D1FE of the 4N + 3rd line where the UT returns from “3” to “0” (see (e)).

Further, line data for one line is sequentially output at intervals (see (f)). REND becomes "1" during the output period of the data D1FE of each line data (see (g)). RCUT is 4N +
When the output of the data D1FE of the second line is completed, “2” is output.
Is incremented from “3” to “3”, and when the output of the data D1FE of the 4N + 3 line is completed, the cycle returns to “0” from “3”, and the output is incremented to “1” when the output of the data D1FE of the 4N + 4 line is completed. ((H)
reference). RCY becomes “1” during the output period of the data D1FE of the 4N + 3rd line where the RCUT returns from “3” to “0” (see (i)).

The overtaking determination flag TFF is set from "0" to "1" when the input of the data D1FE is completed by WCY in the input period of the 4N + 3 line, and 4N + 3
When the output of the data D1FE is completed by the RCY in the output period of the line, it is reset to “0” (see (j)). The comparison result by the comparison circuit 11 is “0” because WCUT ≠ RCUT until the output period of the 4N + 4th line ends, and when the output period of the 4N + 4th line ends, the RCUT is incremented to “1” and WCUT =
Since it becomes RCUT, it changes to “1” (see (k)).

The output weight signal R-WAIT is a TFF
= 0 and WCUT = RCUT (the comparison result is "1"), that is, "1" during the period after the output period of the 4N + 4th line ends (see (m)). Data output requests are limited. Note that the input weight signal W-WAIT is a TFF
= 1 and there is no period in which WCUT = RCUT, so it is always "0" (see (l)), and therefore the signal generation circuit 1 is not restricted.

As described above, according to the second embodiment, similarly to the first embodiment, control of line data composed of m consecutive data input / output asynchronously can be realized with a small buffer memory capacity. And a memory controller capable of high-speed operation can be realized, and the number of input / output line data is counted by the read counter 4 and the write counter 5, so that the hardware scale can be reduced. It can be even smaller.

Embodiment 3 Next, a third embodiment of the present invention will be described. FIG. 7 is a block circuit diagram of the memory control device according to the second embodiment. In the figure, 1 is a signal generation circuit, 7 is a buffer memory, 8 is a selector circuit, 3
Is a signal processing circuit, 4 is a write counter, 5 is a read counter, and 9 is a memory control circuit. In FIG. 7, the same components as those in FIG. 1 are denoted by the same reference numerals. The memory control device of FIG. 7 differs from the memory control device of FIG. 1 in that the buffer memory 2 and the memory control circuit 6 are replaced by a buffer memory 7 and a memory control circuit 9, respectively.
Is provided.

The buffer memory 7 has a single-port D
It is composed of a RAM. Also, the selector circuit 8
Switches the data input / output port of the buffer memory 7 to the signal generation circuit 1 or the signal processing circuit 3 for connection. That is, the selector circuit 8 switches the data input / output path (read / write direction) of the buffer memory 7.

The memory control circuit 9, like the memory control circuit 6 of the first embodiment, is based on WCUT and WCY output from the write counter 4 and RCUT and RCY output from the read counter 5. The number of data that is input to the buffer memory 2 and not output from the buffer memory 2 is managed, and the input weight signal WW
The operations of the signal generation circuit 1 and the signal processing circuit 3 are restricted by the AIT and the output weight signal R-WAIT. Further, the memory control circuit 9 generates a write address and a read address of the buffer memory 7 for each data and outputs the generated write address and read address to the buffer memory 7 and controls the selector circuit 8 at the same time. That is, the write address is generated from the WCUT output from the write counter 4, the read address is generated from the RCUT output from the read counter 5, and the switching of the data read / write direction by the selector circuit 8 is input. This is performed in synchronization with a clock twice the sampling frequency of data and output data.

FIG. 8 is a block circuit diagram showing a configuration of the memory control circuit 9. In FIG. 8, the memory control circuit 9
Are a comparison circuit 11, a determination circuit 12, a write control circuit 13, a read control circuit 14, and an address generation circuit 25.
It consists of. In FIG. 8, the same components as those in FIG. 2 are denoted by the same reference numerals. Memory control circuit 9
Is obtained by providing an address generation circuit 25 in the memory control circuit of FIG. The address generation circuit 25 generates a clock W / R twice as high as the sampling frequency of the input data and the output data, and outputs the clock W / R to the selector circuit 8 and the buffer memory 7. A write address and a read address are generated based on the RCUT, and these addresses are output to the buffer memory. here,
The selector circuit 8 switches the data input / output port of the buffer memory 7 to the signal generation circuit 1 at the rise of the clock W / R, and switches the data input / output port to the signal processing circuit 3 at the fall of the clock W / R. I do. The buffer memory 7 performs a data write operation during a period when the clock W / R is at a high level,
It is assumed that the data read operation is performed at the falling edge during the period when / R is at the low level.

Next, the operation will be described. FIG. 9 is an operation timing chart of the memory control device according to the third embodiment. FIG.
(A) is write data (write timing of input data) of the buffer memory 7, (b) is a count value WCUT of the number of input data, (c) is a carry bit WCY of the WCUT, and (d) is an address generation circuit 25. (E) is output data (read timing of storage data) from the buffer memory 7, (f) is a count value RCUT of the number of output data, (g) is a carry bit RCY of the RCUT, (h) Is the passing flag T
FF, (i) is a comparison result by the comparison circuit 11, (j) is an input weight signal W-WAIT, and (k) is an output weight signal R-WAIT.

In FIG. 9, when data is input from the signal generation circuit 1 to the buffer memory 7, the clock W
Input data is written to the buffer memory 7 in synchronization with the rise of / R. When there is a data output request from the signal processing circuit 3, data is read from the buffer memory 7 in synchronization with the falling edge of the clock W / R (see (a), (d), and (e)). ).

Also, WCUT, RCUT, WCY, RC
Y, TFF, comparison result by comparison circuit 11, W-WAI
The actions of T and R-WAIT are the same as in the first embodiment. The WCUT and the RCUT are incremented according to the input and output of data, respectively, and when they become "FF", return to "0" at the next input and output of data (see (b) and (f)). WCY and RCY are "F" for WCUT and RCUT.
It becomes “1” during the period of “F” (see (c) and (g)). Overtaking determination flag TFF
Is set to “1” when WCY becomes “1” and RC
When Y becomes "0", it is reset to "0" (see (h)). The comparison result by the comparison circuit 11 is WCUT @ RC
It becomes "0" for UT and "1" for WCUT = RCUT (see (i)). Input weight signal WW
The AIT becomes “1” during the period when TFF = 1 and WCUT = RCUT (see (j)), thereby restricting data input from the signal generation circuit 1. The output wait signal R-WAIT is TFF = 0 and WCUT = R
It becomes “1” during the CUT period (see (k)), thereby limiting the data output request by the signal processing circuit 3.

As described above, according to the third embodiment, similarly to the first embodiment, control of data input / output asynchronously can be realized with a small buffer memory capacity and a small hardware scale. An operable memory control device can be realized, and an inexpensive memory control device can be realized by using a single-port memory.

In the third embodiment, a single-port DRAM is used as the buffer memory 7, but the buffer memory 7 is not necessarily a DRAM, and a memory such as an SRAM may be used. In the third embodiment, the read / write direction of the buffer memory 7 is switched in units of one data. However, the direction is not necessarily limited to one data unit, and may be switched in any data unit.

[0054]

According to the memory control device of the first aspect of the present invention, the number of input / output data is counted by the input side counter and the output side counter, and the count values of both counters are compared. A flag is set which is set to "1" when the circuit goes round and reset to "0" when the output side counter makes a circuit. Based on the comparison result of the count values and the flag value, the two count values match. When the flag is set to "1", the data input is restricted, and when the count values match and the flag is set to "0", the data output is restricted. There is an effect that control of data input / output asynchronously can be realized with a small buffer memory capacity. Further, since it is possible to determine whether to limit data input / output by a simple algorithm, control of data input / output asynchronously can be realized on a small hardware scale, and the time required for the determination can be reduced. However, there is an effect that a memory control device which is short and can operate at high speed can be realized.

According to the memory control device of the second aspect of the present invention, control of a data block composed of m pieces of data input / output asynchronously can be realized with a small buffer memory capacity. Since the number is counted by the input side counter and the output side counter, there is an effect that the hardware scale can be further reduced.

According to the memory control device of the third aspect of the present invention, control of data input / output asynchronously can be realized with a small buffer memory capacity and a small hardware scale, and a memory control capable of high-speed operation. In addition to the realization of the device, the use of a single-port memory has the effect that an inexpensive memory control device can be realized.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a configuration of a memory control device according to a first embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a configuration of a memory control circuit according to the first embodiment of the present invention.

FIG. 3 is an operation timing chart of the memory control device according to the first embodiment of the present invention;

FIG. 4 is an operation timing chart of the memory control device according to the first embodiment of the present invention;

FIG. 5 is an operation timing chart of the memory control device according to the second embodiment of the present invention;

FIG. 6 is an operation timing chart of the memory control device according to the second embodiment of the present invention;

FIG. 7 is a block circuit diagram showing a configuration of a memory control device according to a third embodiment of the present invention.

FIG. 8 is a block circuit diagram showing a configuration of a memory control circuit according to a third embodiment of the present invention.

FIG. 9 is an operation timing chart of the memory control device according to the third embodiment of the present invention.

FIG. 10 is a block circuit diagram showing a configuration of a conventional memory control device.

FIG. 11 is an operation timing chart of a conventional memory control device.

[Explanation of symbols]

2,7 buffer memory, 4 write counter, 5
Read counter, 6, 9 Memory control circuit, 10
Comparison circuit, 11 comparison circuit, 12 discrimination circuit, 1
3 Write control circuit, 14 Read control circuit.

Claims (3)

[Claims] 1. A memory control device for temporarily storing input data in a buffer memory and outputting data from the buffer memory at a timing different from that of the input data. An input counter having a positive integer) bit width, an output counter having an n-bit width for counting output data, a means for comparing the count values of the input counter and the output counter, Means for setting a flag to "1" when the output side counter makes a round, and resetting the flag to "0" when the output-side counter makes one cycle. Based on a comparison result by the comparing means and the flag value, When it is detected that the count values of the output side counter and the output side counter match and the flag is set to "1", the buffer memory Means for restricting the input of the data, and the count value of the input counter and the count value of the output counter match based on the comparison result by the comparing means and the flag value, and the flag becomes "0". Means for restricting the output of data from the buffer memory upon detecting that the data has been stored. 2. The memory control device according to claim 1, wherein a data block composed of m (m is an integer of 2 or more) input data blocks is temporarily stored in a buffer memory. A memory control device that outputs the data blocks from the buffer memory at different timings, wherein the input counter counts the input data blocks, and wherein the output counter counts the output data blocks. 3. The memory control device according to claim 1, wherein said buffer memory is a single-port memory, and further comprising means for switching a data input / output path to / from said buffer memory.