JPH11204657A - CMOS integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS optimal for reduction in circuit area and miniaturization.
An integrated circuit is provided. SOLUTION: This CMOS integrated circuit 10 has an nMOSFET formed in a p-well in a part of the circuit, and has an nMOSFET active region 12 in plan view.
And a trench element isolation region 14 surrounding the periphery. The active basin 12 has a gate electrode 16
Is provided. In the active region 12, an n ⁺ diffusion layer region 18 formed by ion implantation is formed as a source region having an upper layer 17 silicided, and p ⁺ for making a good electrical connection with the well.
A contact ion implantation (II) region 20 is formed adjacent to n ⁺ diffusion layer II region 18. The contact 22 is formed as a common contact, and is formed to penetrate the trench element isolation region 14 from the active region 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a CMOS integrated circuit, and more particularly, to a CM with a reduced circuit area.
The present invention relates to an OS integrated circuit.

[0002]

2. Description of the Related Art In a CMOS integrated circuit, a contact (hereinafter simply referred to as a well) for connecting a well region to a wiring.
As one method of forming a contact, there is a method called a butting contact. This method is mainly based on pMOSFE
It is applied to the case where the source region of T is connected to Vdd, the source region of nMOSFET and Vss, and the source region of MOSFET and the well are short-circuited. Conventional CM
Taking the nMOSFET 40 in the OS integrated circuit as an example, the batting contact is, as shown in FIG. 5, an n ⁺ diffusion layer formed as a source region of a MOSFET in a MOSFET active (Active) region 42. An ion implantation (II) region (hereinafter, referred to as an SD diffusion layer region) 44 and ap ⁺ diffusion layer ion implantation (II) region (hereinafter, body-side diffusion) for making contact with a well region. 46 (which may be referred to as a layer) are arranged adjacent to each other, and each region is connected to the same wiring via a first contact 48 and a second contact 50, respectively. In FIG. 1, reference numeral 52 denotes a gate electrode.

In the batting contact method, a source contact (a contact connecting a source region and a wiring) and a well contact are formed in a MOSFET active region, so that a well contact is formed separately in addition to the MOSFET active region. It is not necessary to provide an active region for the CMOS integrated circuit, so that the circuit area of the CMOS integrated circuit can be reduced.

[0004] In the conventional batting contact method shown in FIG. 4, the parameter that gives the length in the horizontal direction mainly includes (1) the distance Ls ₁ between the gate electrode 52 and the p ⁺ diffusion layer ion implantation region 46. (2) Distance Lo ₁ between contact 50 and p ⁺ diffusion layer ion implantation region 46 (3) Diameter Wc _{1 of} contact 50 (4) Four sum of fogging Lo ₂ with contact 20 of MOSFET active region 42 It is. The values of these parameters are limited by the following factors: 1) misalignment, 2) processing margin, 3) margin in consideration of flatness during photolithography, 4) contact and the like.

[0005]

By the way, the demand for miniaturization and high integration of semiconductor devices has been increasing more and more.
There is a demand for miniaturization of MOS integrated circuits, and it is extremely important to reduce the circuit area in order to advance the miniaturization. Accordingly, an object of the present invention is to provide a CMOS integrated circuit that is optimal for reducing the circuit area and miniaturizing.

[0006]

In order to achieve the above object, a CMOS integrated circuit according to the present invention is characterized in that a contact connecting a source region of a MOSFET to a wiring and a contact connecting a well region to a wiring have a common contact. Wherein the common contact is formed to extend from the active region into the trench isolation region. By making the trench element isolation region a part of the contact formation region, the MOS
The FET active area can be saved.

Further, the source region is silicided (Silici).
By using a diffusion layer that is de-formed), the conduction characteristics can be improved and the circuit area can be reduced. By performing ion implantation of the same conductivity type as that of the well region in a region where the contact makes electrical contact with the well region, the contact characteristics can be improved. In the trench isolation region of the preferred embodiment, the bottom of the contact is located at a position deeper than the depth of the diffusion layer in the source region. Thereby, contact with the well region can be ensured.

[0008]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment Example This embodiment is an example of an embodiment of a CMOS integrated circuit according to the present invention. FIG. 1 is a plan view of the CMOS integrated circuit of this embodiment, and FIG. 2 is a cross section taken along line II. FIG. As shown in FIG. 1, the CMOS integrated circuit 10 of this embodiment has an nMOSFET formed in a p-well as a part of the circuit. It should be noted that the present invention
The present invention can also be applied to a CMOS integrated circuit having a pMOSFET formed in an n-well as a part of the circuit. The CMOS integrated circuit 10 of the present embodiment is an nMOS
It comprises an FET active region 12 and a trench isolation region 14 surrounding the active region. nMOSF
A gate electrode 16 is provided in the ET / active basin 12. nMOSFET active area 12
Inside the n ⁺ diffusion layer ion formed as a source region
Implantation (II) region 18 is formed with upper layer 17 silicided, and p ⁺ contact ion implantation (II) region 20 for making good electrical connection with the well region is formed. As shown in FIG. 2, an n ⁺ diffusion layer is formed adjacent to the ion implantation region 18. Contact 22
As shown in FIG. 2, it is formed as a common contact,
It is formed so as to enter the trench element isolation region 14 from the nMOSFET active region 12. The contact 22 includes two contacts 22A, as shown in FIG.
B may be formed.

That is, the CMOS integrated circuit 10 is formed under the following conditions. (1) For element isolation, trench element isolation (STI) is used. (2) n ⁺ diffusion layer ion implantation region 1
6 is only the SD diffusion layer II area. (3) The contact 22 extends over the nMOSFET active region 12 and the trench isolation region. (4) The diffusion layer region is silicided. In addition,
Although it is not always necessary to use a silicide, this embodiment uses a silicide layer for ease of explanation. (5) The p ⁺ contact ion implantation region 20 is doped with impurities to have the same conductivity type as the well region. This structure is used in a dry etching process performed for forming a contact hole for the contact 22.
The fact that a slight over-etching is performed to form a contact hole portion in the element isolation region by digging a trench element isolation film having a small selectivity with respect to an interlayer insulating film is utilized.

The contact hole and the trench isolation film are designed so as to overlap each other, and the depth at which the trench isolation film is dug is the SD diffusion layer depth Xj (see FIG. 2).
If you over-etch to become deeper enough,
A well contact can be obtained by the contact buried in this portion. On the other hand, an n ⁺ diffusion layer region 18 formed by performing ion implantation is connected to a contact 22 via a silicide layer 17. The degree of overetching may be about 30%, with the thickness of the interlayer insulating film being 1 μm, the selectivity being 1 and Xj being 0.1 μm.

Here, a method of forming the p ⁺ contact ion implantation region 20 will be described with reference to FIGS. As shown in FIG. 3, an nMOSFET is formed in a p-well according to a conventional method, and a source / source is formed.
A drain diffusion layer is formed. Next, an interlayer insulating film 24 is formed on the substrate by a CVD method or the like. Subsequently, a mask having an opening pattern of the contact hole is manufactured by using photolithography, the interlayer insulating film 24 is etched using the obtained mask, the contact hole 26 is opened, and the mask is removed. To produce a p ⁺ contact ion implantation mask 28 with respect to the contact hole 26 corresponding to the butting contact of the opened contact holes for the contact hole opening 30 a p ⁺ ions by ion implantation Implant to form p ⁺ contact ion implantation region 20.

In this embodiment, compared to a conventional CMOS integrated circuit, it is not necessary to provide both the p ⁺ and n ⁺ diffusion layers in the nMOSFET active region, so that the cell element size can be reduced. . This will be described with an example. Here, a conventional CMOS integrated circuit 40 shown in FIG. 5 and a conventional CMOS integrated circuit 60 adopting the silicide technology shown in FIG. The parameters for determining the horizontal pitch of the CMOS integrated circuit 10 of the present embodiment are defined as follows, and the magnitudes are compared. Conventional CMOS integrated circuit (Fig. _{5) D 1 ≡Ls 1 + Lo} 1 + Wc 1 + Lo 2 diffusion layer conventional CMOS integrated circuit silicided (FIG. _{6) D 2 ≡Ls 1 + Wc} 1 + Lo 2 present embodiment CMOS of Table 1 shows the definitions of the constants of D ₃ ≡Ls ₂ + Wc ₂ + Wc ₃ , the conditions that are considered to be the limiting factors for the reduction, and the values used in this calculation example.

[Table 1] D ₃ from D ₁ calculated by using these values were as follows. D ₁ = 1.00 μm D ₂ = 0.85 μm D ₃ = 0.70 μm As a result, it was confirmed that the cell element size of the CMOS integrated circuit of the present invention could be significantly reduced.

[0013]

According to the present invention, the contact for connecting the source region of the MOSFET to the wiring and the contact for connecting the well region to the wiring are formed from the active region into the trench isolation region, thereby forming a lateral portion of the cell element. The pitch in the direction can be reduced. When forming a batting contact, n ⁺
Since it is not necessary to simultaneously form the diffusion region and the p ⁺ diffusion region, processes such as photolithography can be simplified.

[Brief description of the drawings]

FIG. 1 is a plan view of an embodiment of a CMOS integrated circuit according to the present invention.

FIG. 2 is a sectional view taken along line II of FIG. 1;

FIG. 3 is a diagram illustrating a method of forming a contact diffusion layer ion implantation region.

FIG. 4 is another diagram illustrating a method of forming a contact diffusion layer ion implantation region.

FIG. 5 is a plan view of a conventional CMOS integrated circuit.

FIG. 6 is a plan view of a conventional CMOS integrated circuit in which a diffusion layer is silicided.

[Explanation of symbols]

10. An embodiment of the CMOS integrated circuit according to the present invention,
12 ... nMOSFET active region, 14 ... trench element isolation region, 16 ... gate electrode, 18 ... n
⁺ Diffusion layer region, 20... P ⁺ contact ion implantation region, 22... Contact, 24.
Interlayer insulating film, 26 contact hole, 28 p ⁺
Mask for contact ion implantation,
30 contact hole opening, 40 conventional CM
OS integrated circuit, 42... MOSFET active region, 44... Diffusion layer ion implantation region, 46... P ⁺ diffusion layer ion implantation region, 48... First contact, 50. Contact, 52 ... Gate electrode.

Claims (4)

[Claims] 1. A contact for connecting a source region of a MOSFET to a wiring and a contact for connecting a well region to a wiring are formed as common contacts, and the common contact is formed from the active region into the trench isolation region. A CMOS integrated circuit characterized by: 2. The method according to claim 1, wherein the source region is silicided.
The CMOS integrated circuit according to claim 1, wherein the diffusion layer is a (diffused) diffusion layer. 3. The CMOS integrated circuit according to claim 1, wherein a contact area where the contact makes electrical contact with the well region is subjected to ion implantation of the same conductivity type as the well region. circuit. 4. The CMOS integrated circuit according to claim 1, wherein a bottom of the contact is located at a position deeper than a depth of the diffusion layer of the source region in the trench element isolation region.