JPH11204697A - Substrate mounting mechanism for semiconductor devices - Google Patents

Abstract

(57) [Problem] To provide a substrate mounting mechanism of a semiconductor device capable of preventing delamination of an interposer in a reinforcing terminal portion and improving bonding strength with a mounting substrate. SOLUTION: A plating through hole 15 is formed at a position where a reinforcing terminal 10 of an interposer 3 'is arranged, thereby connecting the layers of the interposer 3' at this portion and twisting or warping the mounting board 7 or the like. Even if stress occurs in the reinforcing terminal 10, delamination of the interposer 3 'is prevented. As a result, the bonding strength with the mounting substrate 7 is improved, and the reliability of the semiconductor device 1 'is increased. Further, a peeling test of a joint portion at the time of introduction of a new part or the like can be accurately performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a substrate mounting mechanism of a semiconductor device which is optimally used for, for example, a chip scale package (CSP) component.

[0002]

2. Description of the Related Art In recent years, a BGA (Ball Grid Arra) has been developed as a new package having excellent mountability, mounting cost and electrical characteristics.
y) / CSP (Chip Scale Package) is on the market,
It is becoming a major semiconductor package component. BGA /
Unlike a conventional semiconductor package component having legs (external leads) around the CSP, the CSP performs electrical wiring required at an antinode portion on the mounting board side, and has a certain position when mounted on the mounting board. It has a self-alignment function (automatic alignment function) that adjusts the component to a predetermined mounting position by the surface tension when the solder is melted even if there is a deviation. In addition, CSP has a narrow bump arrangement interval among BGAs,
The parts themselves are downsized and made into chips.

[0003] As shown in FIG.
(Hereinafter referred to as a semiconductor device) 1 includes a semiconductor chip 2,
The semiconductor chip 2 is mounted on a mounting substrate 7 via the interposer 3, comprising an interposer 3 as an interposer and a sealing resin 5 for integrating them. The interposer 3 has a multilayer structure made of an inorganic material such as ceramic or an organic material such as polyimide.
Protection function, a function of alleviating a stress caused by a difference in thermal expansion coefficient between the semiconductor chip 2 and the mounting substrate 7, a function of extending wiring between the electrodes of the semiconductor chip 2 to a land 7a of the mounting substrate 7, and the like. Have. Land part 7 of mounting substrate 7
The joint portion of the interposer 3 to be soldered to a is composed of a signal terminal 9 electrically connected to the electrode portion of the semiconductor chip 2 by the bonding wire 4 and reinforcing terminals 10 arranged at four corners of the interposer 3. You. The reinforcing terminal 10 is provided with the signal terminal 9 due to the twist or warp of the mounting substrate 7.
It is provided for the purpose of alleviating the stress acting on the solder joints.

[0004]

However, in the prior art configured as described above, there is a problem that the reinforcing terminal 10 cannot perform its original function and the bonding strength with the mounting substrate 7 cannot be improved. . This is because, during use, when the mounting substrate 7 is twisted or warped, the stress acts on the reinforcing terminals 10 of the interposer 3. At this time, the interposer 3 causes delamination (destruction) F as shown in FIG. For this reason, the stress directly acts on the inner signal terminal 9 because the reinforcing terminal 10 cannot achieve its original function. As a result, the reliability of the semiconductor device 1 itself is reduced.

In order to evaluate these models and components when introducing new models and registering new components, a peeling test is performed to measure the solder joint strength between the joint of the interposer 3 and the mounting board 7. However, while the signal terminal 9 is properly peeled off, the reinforcing terminal 10 is delaminated in the interposer 3 described above, so that correct measurement or confirmation cannot be performed as a whole. There's a problem.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described problems, and has as its object to provide a substrate mounting mechanism of a semiconductor device capable of preventing delamination of an interposer in a reinforcing terminal portion and improving bonding strength with a mounting substrate. And

[0007]

According to the present invention, a plated through hole is provided at a place where a reinforcing terminal of the interposed base is arranged, so that interlayer connection of the interposed base is performed. Thereby, delamination of the interposition base material of the reinforcing terminal portion is prevented, and the original function of the reinforcing terminal can be performed. In addition, it becomes possible to appropriately perform a peeling test of the semiconductor device.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A substrate mounting mechanism for a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.
Parts corresponding to those in FIG. 2 are denoted by the same reference numerals. The semiconductor device 1 'includes a semiconductor chip 2, an interposer 3' as an interposer, and a sealing resin 5 for integrating them. Semiconductor chip 2 and interposer 3 '
Although not shown, an insulator is interposed (not shown), and the semiconductor chip 2 is mounted on the mounting substrate 7 via the interposer 3 '. The interposer 3 ′ has a multilayer structure of aramid fiber in the present embodiment, and functions to protect the semiconductor chip 2 and relieve stress due to a difference in the coefficient of thermal expansion between the semiconductor chip 2 and the mounting board 7, as in the related art. It has a function and a function of extending the wiring between the electrodes of the semiconductor chip 2 to the distance between the lands 7a of the mounting substrate 7, and the like. The junction of the interposer 3 ′ soldered to the land 7 a of the mounting board 7 includes the signal terminal 9 electrically connected to the electrode of the semiconductor chip 2 by the bonding wire 4 and the interposer 3 ′, as in the related art. And reinforcement terminals 10 arranged at four corners.

Therefore, in the present embodiment, the signal terminal 9 is provided at a position where the reinforcing terminal 10 of the interposer 3 'is disposed.
Are formed in the same plated through hole 15 as the place where. The plated through hole 15 is electrically insulated from the semiconductor chip 2 and is formed as a dummy through hole. The through-hole plating is made of copper.

As described above, by forming the plated through hole 15 at the position where the reinforcing terminal 10 of the interposer 3 'is arranged, the interlayer of the interposer 3' at this portion is connected by copper plating, and the interposer 3 'at that position is formed. In this case, the interposer 3 ′ is prevented from delaminating even when stress is applied to the reinforcing terminal 10 due to the twisting or warping of the mounting board 7, whereby the solder joint of the signal terminal 9 is formed. It reduces the effects of direct stress.

Therefore, according to the present embodiment, the original function of the reinforcing terminal 10 that enhances the solder joint strength between the signal terminal 9 of the interposer 3 'and the mounting board 7 can be performed. It is possible to improve the bonding strength between the 3 ′ and the mounting board 7 as compared with the related art, and to reduce the stress acting on the solder bonding portion of the signal terminal 9 to improve the reliability of the semiconductor device 1 ′. it can.

In addition, when a peeling test is performed on a joint portion when a new model is introduced and a new part is registered, delamination of the interposer 3 'at a portion where the reinforcing terminal 10 is formed is prevented. A correct measurement or confirmation of the intensity can be made.

Although the embodiment of the present invention has been described above, the present invention is, of course, not limited to this, and various modifications can be made based on the technical concept of the present invention.

For example, in the above embodiment, the semiconductor chip 2 in the semiconductor device 1 ′ is of a face-up type in which the electrode portion is directed upward. On the contrary, the electrode portion is directed downward (to the interposer 3 ′). The present invention is also applicable to a face-down type semiconductor chip directed to the semiconductor chip. In this case, the connection with the interposer 3 ′
The mounting is performed in a flip-chip manner, while being extended to the wiring interval of the mounting board 7. In addition, the material of the interposer 3 ′ can be changed as appropriate, and is determined by, for example, the relationship with the material (thermal expansion coefficient) of the mounting substrate 7.

[0016]

As described above, according to the substrate mounting mechanism of the semiconductor device of the present invention, the plated through holes are provided at the positions where the reinforcing terminals of the interposed base are arranged, so that each layer of the interposed base is provided. Is connected, the interlayer can be prevented from delamination or destruction of the interposed base material of the reinforcing terminal portion, and the original function of the reinforcing terminal can be performed, thereby improving the bonding strength with the mounting board. Thus, the reliability of the semiconductor device can be improved. In addition, it becomes possible to appropriately perform a peeling test of a joint portion when introducing a new component and registering a new component.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part showing an embodiment of the present invention.

FIG. 2 is a sectional view of a main part showing a conventional example.

FIG. 3 is a side view showing the operation of FIG. 2;

[Explanation of symbols]

1 '... semiconductor device, 2 ... semiconductor chip, 3' ...
…… interposer, 4 …… bonding wire, 5
... sealing resin, 7 ... mounting board, 9 ... signal terminals, 10 ... reinforcing terminals, 12 ... solder, 15 ...
Plating through hole.

Claims (4)

[Claims] 1. A board mounting mechanism of a semiconductor device for mounting a semiconductor chip on a mounting board via an interposer, wherein an electrode portion of the semiconductor chip is provided on a surface of the interposer which is closer to the mounting board. A plurality of signal terminals connected to the mounting substrate, and a bonding portion comprising reinforcing terminals arranged at four corners of the interposition base material and reinforcing the bonding with the mounting substrate is provided. A substrate mounting mechanism for a semiconductor device, wherein a plated through hole is formed at a position of the interposition base where the reinforcing terminal is arranged. 2. The substrate mounting mechanism of a semiconductor device according to claim 1, wherein the semiconductor chip and the interposer are integrated with a sealing resin. 3. The semiconductor device according to claim 1, wherein the interposer has a multilayer structure, and a circuit for extending a wiring interval of the semiconductor chip to a wiring interval of the mounting board is formed. Board mounting mechanism. 4. The board mounting mechanism of a semiconductor device according to claim 1, wherein the plated through hole formed in the reinforcing terminal is electrically insulated from each electrode portion of the semiconductor chip.