JPH11214328A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: In a semiconductor having a diffusion depth of 0.1 μm or less and having a silicide film formed by a salicide process,
Suppresses diffusion of metal near the interface of the diffusion layer. A shallow n ⁺ diffusion layer of about 0.1 μm is formed on an exposed Si substrate by ion implantation of As (FIG. 1A). on the n ⁺ diffusion layer 15, the F ions or F ₂ ions are implanted, n ⁺ dopant profile peak concentration position and profile than the diffusion layer 15, forming a gettering region 16 having a F profile of a shallow position (FIG. 1C). After removing the SiO ₂ film 14, a Ti film 17 and a TiN film 18 are sequentially deposited on the entire surface to a thickness of about 15 nm and a TiN film 18 in order (FIG. 1D). Heat treatment is performed at 600 ° C. for 30 minutes in an N ₂ atmosphere to form Ti silicide 19 (FIG. 1E).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device in which a compound film of a high melting point transition metal such as Ti silicide is formed on a shallow impurity diffusion layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated, miniaturization of electronic circuits has been progressing, and miniaturization of basic elements such as field effect transistors (FETs) has become necessary.

As the gate electrode of the FET becomes narrower, the depth of the diffusion layer in the source / drain region is required to be reduced in order to suppress the occurrence of the short channel effect, and a low acceleration ion implantation method is widely used. ing. By using this method, a shallow diffusion layer of 0.1 μm or less can be formed, and it is possible to improve the performance as well as miniaturize the FET.

[0004] When the depth of the diffusion layer is reduced, the resistance of the diffusion layer becomes extremely high, resulting in a sheet resistance of 100 Ω / □ or more. In order to increase the speed of the semiconductor element, it is necessary to reduce the sheet resistance of the diffusion layer to make it easier for the drain current to flow. For this purpose, a method has been proposed in which the surface of the diffusion layer is metallized to reduce the resistance.

As one method of metallizing the surface of the diffusion layer, silicide is formed on the surface of the diffusion layer in a self-aligned manner.
There is a method called a salicide process. A general salicide process will be described with reference to FIG.

First, a gate insulating film 93 is formed in a device forming region surrounded by a field oxide film 92 on a p-type Si substrate 91.
(1) A gate region composed of a gate electrode 93 (2) made of polysilicon and a side wall insulating film 93 (5) is formed, and an n ⁺ type impurity diffusion layer 94 is formed by ion implantation. Subsequently, a titanium (Ti) film 97 is deposited to a thickness of 30 nm. (FIG. 8 (a)).

Next, the multilayer film is annealed in a nitrogen atmosphere to cause the Ti film 97 to react with the gate electrode 93 (2) and the diffusion layer 94 to form a titanium silicide (TiSi ₂ ) film 99 (FIG. 8). (B)). Next, the unreacted Ti film 97 is removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide. (FIG. 8 (c)). By the steps so far, the TiSi ₂ film 99 is formed only on the gate electrode 93 (2) and the impurity diffusion layer 94 in a self-aligned manner. Finally, an insulating film 95 is formed, a contact hole connected to the diffusion layer is formed, and an electrode wiring 96 is formed. (FIG. 8
(D)).

According to the salicide process described above, the sheet resistance can be reduced to about 5 Ω / □ by forming, for example, 60 nm silicide. However, recent studies on further miniaturization of MOSFETs have revealed the following problems.

[0009] Since silicide is formed directly on the diffusion layer, the formation of silicide consumes the substrate Si and reduces the effective thickness of the diffusion layer. For example, depth 1
When a titanium silicide (TiSi ₂ ) of 60 nm is formed after forming a diffusion layer of 00 nm, the remaining thickness of the diffusion layer is very small, 40 nm. As a result,
It was found that as the thickness of the effective diffusion layer was reduced, the junction leakage current of the diffusion layer was significantly increased.

[0010] In order to avoid these phenomena, the thickness of the silicide material is reduced. However, when the silicide film thickness of TiSi ₂ is reduced to 20 to 30 nm or less, the Ti silicide film is agglomerated, and as a result, the bonding surface is reduced. Penetration significantly increases junction leakage. Therefore, studies have been conducted to improve the cohesion resistance, and Ti
It has become possible to prevent aggregation of the Si ₂ film. However, as a result of further research, it has become clear that the following problems occur.

[0011] That is, in the case of forming the TiSi ₂ film on the shallow diffusion layer, even if the TiSi ₂ film does not cause aggregation,
It has been clarified that the junction leak occurs remarkably. Therefore, it has been found that when a silicide film is formed on a shallow diffusion layer, there is a problem that a junction leak occurs and the performance of the device is deteriorated.

[0012]

As described above,
Conventionally, T is formed on a shallow impurity diffusion layer
When iSi ₂ is formed in a self-aligned manner, there is a problem that a junction leak occurs due to a cause other than a junction leak due to aggregation of TiSi ₂ .

An object of the present invention is to provide a semiconductor device capable of suppressing junction leakage current and improving element performance even when a compound film of a refractory metal such as Ti is formed on a shallow diffusion layer, and a method of manufacturing the same. It is to provide.

[0014]

Means for Solving the Problems [Configuration] The present invention is configured as follows to achieve the above object. (1) The present invention (claim 1) is a semiconductor device in which a compound film of a constituent element of the semiconductor substrate and a high melting point transition metal is formed on an impurity diffusion layer formed on the semiconductor substrate, The surface layer of the impurity diffusion layer or the compound film contains an element whose reaction energy with the high melting point transition metal is lower than the reaction energy between the element constituting the semiconductor substrate and the metal. I do. (2) The present invention (Claim 2) provides a step of forming an impurity diffusion layer on an exposed surface of a semiconductor substrate having an insulating film formed in a predetermined region, and a step of forming a high melting point transition metal on the impurity diffusion layer and the insulating film. Forming a compound film of the high melting point transition metal and a constituent element of the semiconductor substrate on the impurity diffusion layer in a self-aligning manner. Forming a diffusion suppressing layer that forms a compound with the high melting point transition metal and that suppresses the metal from diffusing into the semiconductor substrate with a layer containing at least a substance other than the semiconductor substrate constituent element. And (3) The present invention (claim 3) provides a step of forming an impurity diffusion layer on a semiconductor substrate having an insulating film formed in a predetermined region;
Depositing a high melting point transition metal on the impurity diffusion layer and the insulating film; and forming a compound film of the high melting point transition metal and a constituent element of the semiconductor substrate on the impurity diffusion layer in a self-aligned manner. Before depositing the high melting point transition metal, the reaction energy with the high melting point transition metal forms the semiconductor substrate on the surface layer of the impurity diffusion layer or on the diffusion layer. A gettering region containing an element having a lower energy than the reaction energy between the element and the metal.

A preferred embodiment of the configuration (3) of the present invention will be described below. (3-1) The gettering region is formed by ion-implanting an element whose reaction energy with the high melting point transition metal is lower than that of the semiconductor substrate into the impurity diffusion layer. (3-2) The gettering region is, in particular, in the n ⁺ type diffusion layer,
Alternatively, it is formed by ion-implanting F or a substance containing F into the surface layer.

Preferred embodiments of the present invention are described below. (a) a step of forming an impurity diffusion layer, a first heat treatment step of activating the impurity diffusion layer, and ion implantation of an element having a lower reaction energy than a constituent element of the semiconductor substrate with respect to the high melting point transition metal. Forming a gettering region in a surface layer of the impurity diffusion layer; a second heat treatment step for activating the impurity diffusion layer in which the gettering region is formed; A step of depositing the high melting point transition metal; and a step of forming a compound film of the high melting point transition metal and an element constituting the semiconductor substrate. (b) a step of forming an impurity diffusion layer, a first heat treatment step of activating the impurity diffusion layer, and ion implantation of an element having a lower reaction energy than a constituent element of the semiconductor substrate into the high melting point transition metal. Forming a gettering region on the surface of the impurity diffusion layer, depositing the high-melting transition metal on the gettering region, heating the semiconductor substrate, and pre-amorphizing the impurity by ion implantation. Activating the gettering region of the diffusion layer and simultaneously forming a compound film of the high melting point transition metal and an element constituting the semiconductor substrate. (c) ion-implanting an element having a lower reaction energy than an element constituting the semiconductor substrate into a dopant and the high melting point transition metal to form an impurity diffusion layer having a gettering region on a surface; The method includes activating a diffusion layer, depositing the high melting point transition metal, and forming a compound film of the high melting point transition metal and an element constituting the semiconductor substrate.

Another preferred embodiment of the configuration (3) of the present invention will be described below. (3-2) The gettering region is, on the impurity diffusion layer, an element layer whose reaction energy with the high melting point transition metal is lower than that of the semiconductor substrate, or a compound of the element and a constituent element of the semiconductor substrate. It is characterized by being formed by forming a layer. (6) The present invention (claim 7) provides a step of forming an impurity diffusion layer on a semiconductor substrate having an insulating film formed in a predetermined region;
Depositing a high melting point transition metal on the impurity diffusion layer and the insulating film; and forming a compound film of the high melting point transition metal and a constituent element of the semiconductor substrate on the impurity diffusion layer in a self-aligned manner. In the method for manufacturing a semiconductor device including, before depositing the high melting point transition metal, forming a thin film containing a compound of the high melting point transition metal and an element constituting the semiconductor substrate on the impurity diffusion layer, The composition ratio of the compound is characterized in that the elements constituting the semiconductor substrate are the same or more.

[Operation] The present invention has the following operation and effects by the above configuration. When the inventors performed cross-sectional observation using a high-resolution TEM on a FET in which junction leakage occurred despite silicide not being aggregated, it was found that Ti-based metal impurities that should not be present in the diffusion layer were found. It was revealed that it existed. Furthermore, as for the FETs in which these metal impurities are not observed, the analysis of the junction leak current reveals that the increase in the generated current due to the existence of some defects near the junction interface and in the depletion layer is remarkable. became.

Junction leakage is caused by an increase in current generated due to generation of defects caused by Ti-based metal near the junction interface and in the depletion layer in the process of forming silicide. A significant increase in current was observed. Further, as shown in FIG. 9, it was found that the junction leak phenomenon was remarkable on the n ⁺ diffusion layer.

As a result of further studies by the inventors, it has been clarified whether a high melting point transition metal exists at the joint interface.
That is, in the reaction between Ti and Si, in the low-temperature reaction before the formation of TiSi ₂ , 1 × 10
¹⁸ is diffusing in to 10 ¹⁹ cm ^-3 order. The presence of Ti diffused into the Si substrate that does not contribute to the formation of Ti silicide in the diffusion layer junction region causes junction leakage.

Therefore, the present invention provides a gettering region of a refractory metal in a region including an impurity diffusion layer, thereby gettering the refractory metal element, and removing the refractory metal element in an initial process of forming a compound film. Diffusion into the substrate can be prevented. Therefore, it is possible to reduce the junction leakage caused by the diffusion of the metal.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a sectional view showing a manufacturing process of a MOSFET according to a first embodiment of the present invention.

First, as shown in FIG.
An 800 nm field oxide film 12 is formed in a p-type Si substrate 11 having a main surface of 1) by an embedding method. A gate oxide film 13 (1) having a thickness of 10 nm, a doped polycrystalline silicon 13 (2) having a thickness of 150 nm, and a tungsten silicide (WSi ₂ ) film having a thickness of 150 nm are formed in an element formation region surrounded by the oxide film 12. After sequentially depositing 13 (3) and a silicon nitride film (SiN film) 13 (4), a gate-shaped laminated film is formed by etching. Then, a 150 nm-thickness SiN film 13 (5) is deposited on the entire surface, and then processed by anisotropic etching to form a gate region 13.

Next, as shown in FIG. 1B, after a SiO ₂ film 14 having a thickness of 10 nm is formed on the exposed Si substrate 11, a dose of 5 × 10 ¹⁴ cm ^{−2,3 of} As ions is applied.
After implanted at an acceleration voltage of 0keV, 90 in an N ₂ atmosphere
By performing a heat treatment at 0 ° C. for 30 seconds, a heat treatment of about 0.1 μm
The n ⁺ diffusion layer 15 having a shallow depth is formed.

Then, as shown in FIG. 1C, F ions or F ₂ ions are implanted on the n ⁺ diffusion layer 15 at a dose of 1 × 10 ¹⁵ cm ^-2 , for example, at a low acceleration voltage, and n ⁺ The gettering region 16 having the F profile is formed at a position where the peak concentration position and the profile are shallower than the dopant profile of the diffusion layer 15. FIG. 2A shows the profile of the diffusion layer formed at this time. In order to perform the heat treatment for activating the dopant again, a heat treatment at 900 ° C. for 30 seconds may be performed in an N ₂ atmosphere, or the heat treatment for activating the dopant may be performed at a time after the formation of the gettering region 16. May be.

Next, after removing the SiO ₂ film 14, the surface of the sample is treated with a mixed solution of sulfuric acid and hydrogen peroxide to remove carbon (C) -based surface contamination, and to remove hydrochloric acid and hydrogen peroxide. Removal of metal-based surface contamination by treatment using the mixed solution is sequentially performed. Thereafter, the thin SiO ₂ film formed on the gettering region 16 at the time of the solution treatment is washed off with dilute hydrofluoric acid, and then washed with running ultrapure water having a dissolved oxygen concentration of 10 ppb. Then, as shown in FIG. 1D, a Ti film 17 is formed on the entire
0 nm is sequentially deposited.

Next, as shown in FIG. 1E, a heat treatment is performed at 600 ° C. for 30 minutes in an N ₂ atmosphere to form a Ti silicide (TiSi ₂ ) film 19. When the TiSi ₂ film 19 is formed, F of the gettering region is at least n.
⁺ Remains in the diffusion layer 15. In some cases, TiS
mixed into the i ₂ film 19. Then, the unreacted Ti film 17 and TiN film 1 are mixed using a mixed solution of sulfuric acid and hydrogen peroxide.
8 is removed by etching.

In the conventional FET, the junction leakage is increased more remarkably on the diffusion layer having a shallower diffusion layer depth, whereas the FET of the present embodiment has the same depth. It was found that the junction leakage was reduced even on a shallow diffusion layer.

Factors that realize the above effects are as follows. It is known that Ti is a silicidation refractory metal in which Si is the main diffusion species in the reaction with Si. However, recent studies have revealed that in the reaction between Ti and Si, Ti diffuses into the Si substrate on the order of 1 × 10 ¹⁸ to 10 ¹⁹ cm ⁻³ in a low-temperature reaction before TiSi ₂ formation. Have been. That is, the presence of Ti diffused into the Si substrate that does not contribute to the formation of Ti silicide in the diffusion layer junction region causes junction leakage.

In the present embodiment, in the initial reaction process between Ti and Si, Ti diffused into the substrate is formed in a very shallow region in the diffusion layer, and the reaction energy with titanium is reduced to Si.
By performing gettering in a gettering region including lower F, junction leakage caused by Ti diffusing into the substrate is reduced. Further, by forming a gettering region immediately below the Ti film, part or all of Ti diffused into the substrate at the beginning of the reaction can be reduced.
By the end of silicide reaction, Ti after silicide formation
It is also possible to take in the Si ₂ film.

In this embodiment, the case where the profile of As is deeper than the profile of F in both the peak concentration and the diffusion depth from the substrate surface and the concentration is higher is shown. It is essential to form a gettering region of Ti under the interface of Si,
For example, a similar effect can be obtained with a profile as shown in FIG. Desirably, the profile of the additive element (F) is closer to the substrate surface side than the peak concentration position of the profile of the dopant (As), and the tail concentration of the F profile is preferably much lower at the n ⁺ / p interface. .
In addition, heat treatment for forming TiSi _{2 is performed} by RTA (Rapid Thing).
ermal Anneal), the same effect can be obtained.

[Second Embodiment] FIG. 3 is a cross-sectional view showing a manufacturing process of a MOSFET according to a second embodiment of the present invention.

First, as in the first embodiment, p-type Si
After forming an element isolation region 12 in a substrate 11, a gate oxide film 13 (1), polycrystalline silicon 13 (2),
Tungsten silicide (WSi ₂ ) film 13 (3) and SiN
Gate region 13 composed of film 13 (4) and SiN film 13 (5)
Is formed (FIG. 3A).

Next, as shown in FIG. 3 (b), after forming a thin 5 nm SiO ₂ film 14 on the exposed surface of the Si substrate 11, As ions are doped at a dose of 5 × 10 ¹⁴ c, for example.
The injection is performed at an acceleration voltage of m ⁻² and 30 keV. Simultaneously with the implantation of As ions, F ions or F ₂ ions are implanted, for example, at a dose of 1 × 10 ¹⁵ cm ⁻² and at a low acceleration voltage. Thereafter, a heat treatment is performed in an N ₂ atmosphere at 900 ° C. for 30 seconds to form an n ⁺ diffusion layer 15 and a gettering region 16 having the same profile as that of the first embodiment.

Next, after removing the SiO ₂ film 14, the surface of the sample is sequentially treated with a mixed solution of sulfuric acid and hydrogen peroxide and with a mixed solution containing hydrochloric acid and hydrogen peroxide. Then, when the solution is processed, the gettering region 1
After the SiO ₂ film formed on 6 is washed away with diluted hydrofluoric acid, it is washed with running ultrapure water having a dissolved oxygen concentration of 10 ppb. Then, as shown in FIG. 3C, a Ti film 17 having a thickness of about 20 nm and a TiN film 18 having a thickness of 100 nm are sequentially deposited on the entire surface.

Then, as shown in FIG. 3D, the substrate temperature is rapidly increased to 700 ° C. in an N ₂ atmosphere to anneal to form TiSi ₂ 19, and then the unreacted Ti film 1 is formed.
7 and the TiN film 18 are removed by etching. After that, the temperature is further raised to 800 ° C. and TiSi ₂ is
Heat treatment for phase transition to 54 layers is performed.

As a result of evaluating the junction leak characteristics using the TiSi ₂ film 19 of this FET as an electrode, as in the first embodiment, an increase in the junction leak current due to an increase in the generated current observed in the conventional FET was observed. And good bonding characteristics could be realized.

In the above embodiment, the heat treatment method for silicide formation is not limited to this, and the same effect can be sufficiently obtained even in furnace annealing in which the heat treatment temperature is not sharply increased.

[Third Embodiment] FIG. 4 is a sectional view showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

First, as in the first embodiment, p-type Si
After forming an element isolation region 12 in a substrate 11, a gate oxide film 13 (1), polycrystalline silicon 13 (2),
Tungsten silicide (WSi ₂ ) film 13 (3) and SiN
Gate region 13 composed of film 13 (4) and SiN film 13 (5)
Is formed (FIG. 4A).

Next, as shown in FIG.
After forming a thin SiO ₂ film 14, As ions are implanted at an acceleration voltage of, for example, a dose of 5 × 10 ¹⁴ cm ⁻² and 30 keV. Next, heat treatment is performed at 900 ° C. for 30 seconds in an N ₂ atmosphere to form a shallow n ⁺ diffusion layer 15 of 0.1 μm.

Next, as shown in FIG. 4C, F ions or F ₂ ions are implanted at a dose of 1 × 10 ¹⁵ cm ⁻² and a very low accelerating voltage, and the gettering region 41 (1) is implanted.
To form Next, after the SiO ₂ film 14 is removed, the surface of the sample is treated with a mixed solution of sulfuric acid and hydrogen peroxide, and with a mixed solution containing hydrochloric acid and hydrogen peroxide. After removing the thin SiO ₂ film formed on the surface of the gettering region 41 (1) during the solution treatment, as shown in FIG. 4D, a Ti film 17 having a thickness of about 20 nm Thickness 100
nm of TiN film 18 is sequentially deposited.

Next, as shown in FIG. 4E, the substrate temperature is rapidly increased to 700 ° C. in an N ₂ atmosphere to anneal to form TiSi ₂ 19, and then the unreacted Ti film 1 is formed.
7 and the TiN film 18 are removed by etching. After that, the temperature is further raised to 800 ° C. and TiSi ₂ is
Heat treatment for phase transition to 54 layers is performed.

In this embodiment, after the shallow diffusion layer 15 is formed first, the surface of the diffusion layer 15 is pre-amorphized by F ions, and then TiSi ₂ 19 is formed. As a result, both the effect of forming a gettering region for preventing the diffusion of Ti into the Si substrate in the initial reaction of Ti and Si and the effect of promoting the phase transition of Ti silicide from the C49 structure to the C54 structure are simultaneously obtained. I can do it.

In the first to third embodiments, the example in which F ions are implanted into the gettering region is used.
Any element can be used as long as it is an element that easily reacts with. For example, F, Cl, Br, O or N
And other elements can be used. When these elements are introduced into the substrate, these single elements or molecules containing these elements are also effective. The number of these ions, the number of ionic molecules, particularly monovalent, divalent, as in the embodiment,
It is not limited to one atom or two atoms. Desirably, it is effective if the peak concentration of the element subjected to post-ion implantation is about 10 ¹⁸ to 10 ²⁰ cm ⁻³ or more. In addition, ion implantation methods include low-acceleration ion implantation, IC
Any method such as B (Ion Cluster Beam) may be used.

The gettering region desirably remains immediately below the silicide electrode or is incorporated into the silicide film after the reaction. In other words, it is needless to say that the gettering region is preferably shallow at the stage of initial formation.

[Fourth Embodiment] FIG. 5 is a process sectional view showing a manufacturing process of a MOSFET according to a fourth embodiment of the present invention.

First, similarly to the first embodiment, n-type Si
After forming the element isolation region 12 in the substrate 61, the gate oxide film 13 (1), the polycrystalline silicon 13 (2),
Tungsten silicide (WSi ₂ ) film 13 (3) and SiN
Gate region 13 composed of film 13 (4) and SiN film 13 (5)
To form

After forming a SiO ₂ film 14 having a thickness of 10 nm on the Si substrate 61 where the element formation region is exposed, BF ²⁺ ions are implanted at a dose of 5 × 10 ¹⁵ cm ⁻² and an accelerating voltage of 35 keV. By applying a heat treatment at 1000 ° C. for 20 seconds in a N ₂ atmosphere, a thin P ⁺
A diffusion layer 62 is formed (FIG. 5A).

Next, after removing the SiO ₂ film 14, the surface of the sample is sequentially treated with a mixed solution of sulfuric acid and hydrogen peroxide and with a mixed solution of hydrochloric acid and hydrogen peroxide solution. Then, the thin SiO ₂ film formed on the surface of the P ⁺ diffusion layer 62 at the time of the solution treatment is washed away with dilute hydrofluoric acid, and then washed with running ultrapure water having a dissolved oxygen concentration of 10 ppb. Then
As shown in FIG. 5B, a 2n SiC _x layer 63 is formed on the entire surface.
m and Ti films 64 are sequentially laminated to a thickness of 15 nm.

Next, as shown in FIG. 5C, the structure is annealed by rapidly increasing the substrate temperature to 800 ° C. in an N ₂ atmosphere, so that the structure is formed between the P ⁺ diffusion layer 62 and the Ti film 64. C in a certain SiC layer 63 and Ti react with each other. During the reaction, while diffusing to the Ti film 64 side while forming TiC,
i and Ti form Ti silicide, and T
An i-silicide (TiSi ₂ ) film 65 is formed. Thereafter, as shown in FIG. 5D, the unreacted SiC _x film 63 is formed.
The Ti film 64 was removed by etching.

FIG. 6 shows the T of the FET formed by the above method.
Using the iSi ₂ film 65 as an electrode, the junction leakage characteristics were evaluated and compared with the conventional method. Conventional FET
In this example, it was confirmed that the junction leakage current increased due to the increase in the generated current, whereas the FET of the present embodiment did not cause the deterioration of the junction characteristics.

Factors for realizing the above effects are the following two. In the interfacial reaction between Ti and Si, the diffusion rate of Si is higher than the diffusion rate of Ti. However, since the interfacial reaction is caused by mutual diffusion, diffusion of Ti to the Si substrate side also occurs. When the titanium diffused to the Si substrate side does not contribute to the formation of TiSi ₂ , the diffusion length of titanium reaches around 0.1 μm and reaches the bonding surface between the diffusion layer and the substrate. Therefore,
By forming a SiC between the Ti and silicon with increasing supply flux of Si to Ti film side, T by to consume the Ti by the formation of TiC _x
At the same time, the reaction rate between i and Si is suppressed, and at the same time, the diffusion of Ti to the Si substrate side is suppressed, thereby forming TiSi ₂ . This can prevent Ti from diffusing into the Si substrate and contributing as an electrical defect.

Another point is that when the temperature is sharply increased, the Ti / SiC _x / Si interface becomes TiS
By shortening the time of exposure to the temperature region before i formation, the time at which Ti diffuses into the Si substrate at a low temperature is shortened.

The diffusion of Ti into the Si substrate at a low temperature is based on S
By suppressing the reaction rate by the reaction between Ti and Si with the iC _x layer interposed therebetween, diffusion of Ti is prevented, and the formation of TiSi ₂ is allowed to react in a more stable temperature range. Is suppressed. With this combination, good bonding characteristics can be realized.

Although the above effects could be sufficiently obtained by heat-treating the laminated structure in the embodiment without abruptly increasing the heat-treating temperature, the temperature profile in which the temperature was sharply increased could further enhance the device performance. It became clear that reliability was improved.

[0057] Furthermore, although using the SiC _x for suppressing layer _{diffusion, SiO x, Si x F y} , TiO x, SiN x
Such a film can be applied. This film may be formed by oxidation or the like, may be formed by CVD or the like, and may be formed by subjecting the Si surface to chemical treatment with a mixed solution of sulfuric acid and hydrogen peroxide solution.
Similar effects can be obtained with al Oxide. Also, S
Not only the compound with i but also a single element may be used. Furthermore, if the film is taken into the silicide film with Ti after the heat treatment and the compound layer does not remain at the interface between the security silicide and the Si, the same effect as in the present embodiment can be obtained.

Further, as long as the layer contains an element which easily reacts with Ti, the same effects as those of the first to third embodiments are exhibited. [Fifth Embodiment] FIG. 7 is a process sectional view showing a manufacturing process of a semiconductor device according to a fifth embodiment of the present invention.

First, as shown in FIG.
1) An 800 nm field oxide film 12 is formed by thermal oxidation on an n-type Si substrate 61 whose main surface is a surface. BF ²⁺ ions are implanted into the element formation region surrounded by the oxide film 12 at a dose of 5 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 35 keV, and then heat-treated at 1000 ° C. for 20 seconds in an N ₂ atmosphere. Thereby, a shallow P ⁺ diffusion layer 62 of about 0.1 μm is formed.

Next, as the interlayer insulating film, a laminated film of the SiO ₂ film 81 and the BPSG film 82 formed by the CVD method is set to 1.0 μm.
After depositing over the entire surface with a thickness of m, a contact hole is formed on the diffusion layer 62. This substrate is treated with a mixed solution of sulfuric acid and hydrogen peroxide, further treated with a mixed solution of hydrochloric acid and hydrogen peroxide, and then the thin SiO ₂ film formed on the surface of the diffusion layer 62 is washed and removed with dilute hydrofluoric acid. Thereafter, washing with running water is carried out with ultrapure water having a dissolved oxygen concentration of 10 ppb.

Next, as shown in FIG.
i a _x film 83 was 5nm deposited to about 15nm deposited Ti film 84. At this time, TiSi _x film 83 is more preferably a x ≧ 1, it is not particularly limited.

Next, as shown in FIG. 7C, the sample was annealed in a N ₂ atmosphere by rapidly raising the substrate temperature to 800 ° C., and the Ti 84 / TiSi _x 83 / diffusion layer 62
Are allowed to react.

Thus, the Ti silicide (Si ₂ ) film 8
5 is formed. Thereafter, as shown in FIG. 7D, the unreacted Ti film 84 is removed by etching. TiSi ₂ film 8
As a result of evaluating the junction leak characteristics using No. 5 as an electrode,
There was no increase in junction leakage current due to an increase in generated current, and good junction characteristics could be realized.

In the interfacial reaction, the reaction rate is determined by the concentration gradient of the constituent substance in each reaction process. T
In the i / Si interface reaction, a Ti silicide is formed in advance at the interface to form a gradual concentration gradient at the Ti / Si interface. Thereby, the reaction speed at the interface can be reduced, and the diffusion of Ti to the Si substrate side can be prevented.

Further, the Ti silicide, ie, TiSi _x S
By making the i composition ratio equal to or more than that of Ti, Ti
The flux of Si supply to the side can be increased, and the diffusion of Ti to the substrate side can be further prevented.

[0066] Incidentally, in the fourth and fifth embodiments both, SiC layer is Ti diffusion suppression layer, when forming the TiSi _x layer of amorphous still be diffusion of Ti is suppressed to more Si substrate, a reliable bonding It has been confirmed that characteristics can be obtained.

Although Ti was used as the high melting point metal film,
Other than can be used. For example, in addition to _{TiSi 2, NiSi x, CoSi x} (x = 0.5,1,2),
_{ZrSi x, Pd x Si, VSi} x, HfSi x, Ta
Even when forming a silicide of a transition metal such as Si _x it can be applied.

The present invention is not limited to the above embodiment. For example, in the present embodiment, Ti is mainly described, but Ni, Co, Pd, V, Hf, Ta, N
It is also applicable to silicide materials such as b and Mo. Various modifications can be made without departing from the scope of the invention.

[0069]

As described above, according to the present invention, a gettering region which easily reacts with the transition metal having a high melting point is formed on the surface layer of the diffusion layer or on the diffusion layer. , The diffusion of the high melting point metal element into the substrate can be suppressed, and the junction leakage can be reduced.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a manufacturing process of a MOSFET according to a first embodiment.

FIG. 2 is a characteristic diagram showing profiles of a diffusion layer and a gettering region of the MOSFET according to the first embodiment.

FIG. 3 is a process cross-sectional view showing a manufacturing process of the MOSFET according to the second embodiment.

FIG. 4 is a process cross-sectional view showing a manufacturing process of the MOSFET according to the third embodiment.

FIG. 5 is a process cross-sectional view showing a manufacturing process of the MOSFET according to the fourth embodiment.

FIG. 6 is a characteristic diagram showing a leakage current of the MOSFET according to the fourth embodiment.

FIG. 7 is a process sectional view illustrating a manufacturing process of a semiconductor device according to a fifth embodiment.

FIG. 8 is a process cross-sectional view showing a manufacturing process of a conventional MOSFET.

FIG. 9 is a characteristic diagram showing leakage currents of p-type and n-type diffusion layers.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Si substrate 12 ... Field oxide film 13 ... Gate region 13 (1) ... Gate oxide film 13 (2) ... Polycrystalline silicon film 13 (3) ... Tungsten silicide film 13 (4) ... SiN film 13 (5) ... SiN film 14 ... SiO ₂ film 15 ... n ⁺ diffusion layer 16 ... gettering region 17 ... Ti film 18 ... TiN film 19 ... Ti silicide film 41 ... gettering region 51 ... n ⁺ diffusion layer 61 ... Si substrate 62 ... P ⁺ diffusion layer 63 ... SiC layer 64 ... Ti film 65 ... Ti silicide layer 81 ... SiO ₂ film 82 ... BPSG film 83 ... TiSi _x film 84 ... Ti film 85 ... Ti silicide film

Claims (7)

[Claims] 1. A semiconductor device in which a compound film of a constituent element of the semiconductor substrate and a transition metal having a high melting point is formed on an impurity diffusion layer formed in the semiconductor substrate, wherein a surface layer of the impurity diffusion layer is provided. Alternatively, in the compound film,
A semiconductor device comprising an element whose reaction energy with the high melting point transition metal is lower than the element constituting the semiconductor substrate and the reaction energy with the metal. A step of forming an impurity diffusion layer on an exposed surface of the semiconductor substrate having an insulating film formed in a predetermined region; a step of depositing a high melting point transition metal on the impurity diffusion layer and the insulating film; Forming a compound film of the high melting point transition metal and a constituent element of the semiconductor substrate in a self-alignment manner on the impurity diffusion layer, wherein the high melting point transition is formed on the impurity diffusion layer. A method of manufacturing a semiconductor device, comprising: forming a diffusion suppressing layer that suppresses the metal from diffusing into the semiconductor substrate in a layer that forms a compound with a metal and that includes at least a substance other than the semiconductor substrate constituent element. . A step of forming an impurity diffusion layer on a semiconductor substrate having an insulating film formed in a predetermined region; a step of depositing a high melting point transition metal on the impurity diffusion layer and the insulating film; Forming a compound film of the high-melting transition metal and a constituent element of the semiconductor substrate in a self-aligned manner, wherein the impurity diffusion layer is formed before the high-melting transition metal is deposited. Forming a gettering region on the surface layer or on the diffusion layer, the gettering region containing an element whose reaction energy with the high melting point transition metal is lower than the reaction energy between the element constituting the semiconductor substrate and the metal. Semiconductor device manufacturing method. 4. The semiconductor device according to claim 3, wherein the gettering region is formed by ion-implanting an element having a lower reaction energy with the high melting point transition metal than the semiconductor substrate into the impurity diffusion layer. 13. The method for manufacturing a semiconductor device according to item 5. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the gettering region is formed by ion-implanting F or a substance containing F into the n ⁺ -type diffusion layer or the surface layer. 6. The gettering region includes an element layer on the impurity diffusion layer, the reaction energy of the high melting point transition metal being lower than that of the semiconductor substrate, or a compound of the element and a constituent element of the semiconductor substrate. 4. The method according to claim 3, wherein the semiconductor device is formed by forming a layer. 7. A step of forming an impurity diffusion layer on a semiconductor substrate having an insulating film formed in a predetermined region; a step of depositing a high melting point transition metal on the impurity diffusion layer and the insulating film; Forming a compound film of the high-melting transition metal and a constituent element of the semiconductor substrate in a self-aligned manner, wherein the impurity diffusion layer is formed before the high-melting transition metal is deposited. A thin film containing a compound of the high melting point transition metal and the element constituting the semiconductor substrate is formed thereon, and the composition ratio of the compound is such that the element constituting the semiconductor substrate is equivalent or more. Manufacturing method of a semiconductor device.