JPH11214364A - Semiconductor wafer processing apparatus - Google Patents

Semiconductor wafer processing apparatus

Info

Publication number
JPH11214364A
JPH11214364A JP1546898A JP1546898A JPH11214364A JP H11214364 A JPH11214364 A JP H11214364A JP 1546898 A JP1546898 A JP 1546898A JP 1546898 A JP1546898 A JP 1546898A JP H11214364 A JPH11214364 A JP H11214364A
Authority
JP
Japan
Prior art keywords
fine particles
chamber
anode
semiconductor wafer
lock chamber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1546898A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Okuni
充弘 大國
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP1546898A priority Critical patent/JPH11214364A/en
Publication of JPH11214364A publication Critical patent/JPH11214364A/en
Pending legal-status Critical Current

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To enable fine particle to be efficiently removed by charging the fine particles positively to generate line of electric force and forming ion stream. SOLUTION: A cathode 21 and an anode 22 are applied with predetermined voltage through a power supply line 42 from a power supply 41, respectively. As a result, etching gas from a reaction chamber 12 is negatively charged with the cathode 21 positioned near the reaction chamber 12. By radiation of ultraviolet light in a load-lock chamber 11 by an ultraviolet light source 23, ionization of the fine particles is further accelerated. The negatively charged fine particles are directly electrically drawn to the direction of the anode 22 along the line of electric force 31 formed with the cathode 21 and the anode 22 by Coulomb force, and efficiently exhausted from a vacuum outlet 14 through a vacuum pump outside the load-lock chamber 11. Thereby, contamination hardly occurs in the load-lock chamber 11.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体ウェハの処
理装置において、放電を利用して微粒子を除去するため
の技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for removing fine particles by utilizing electric discharge in a semiconductor wafer processing apparatus.

【0002】[0002]

【従来の技術】図5は従来の半導体ウェハ処理装置を平
面的に見た概略構成図である。
2. Description of the Related Art FIG. 5 is a schematic structural view of a conventional semiconductor wafer processing apparatus as viewed in plan.

【0003】この半導体ウェハ処理装置は、半導体ウェ
ハをエッチングなどの各種の処理をする一対の処理室
(ここでは反応室)12、これらの反応室12に連設され
た予備排気室であるロードロック室11を備え、ロード
ロック室11内には半導体ウェハの搬送系13および一
対の真空排気口14が設けられている。なお、15は搬
送系13を構成する半導体ウェハ載置用の一対のアーム
である。
This semiconductor wafer processing apparatus includes a pair of processing chambers for performing various processes such as etching a semiconductor wafer.
(Here, a reaction chamber) 12, a load lock chamber 11 which is a preliminary exhaust chamber connected to the reaction chambers 12, and a semiconductor wafer transfer system 13 and a pair of vacuum exhaust ports 14 are provided in the load lock chamber 11. Is provided. Reference numeral 15 denotes a pair of arms for mounting the semiconductor wafer, which constitute the transfer system 13.

【0004】半導体ウェハについてエッチング等の各種
の処理を行う際には、反応室12から微粒子が発生す
る。すなわち、反応室12ではプロセスガスや反応生成
物によって微粒子が発生し、これがウェハ移載の時に反
応室12側からロードロック室11側に流入してダスト
の原因となる。
When various processes such as etching are performed on a semiconductor wafer, fine particles are generated from the reaction chamber 12. That is, in the reaction chamber 12, fine particles are generated by the process gas or the reaction product, and flow into the load lock chamber 11 from the reaction chamber 12 side when transferring the wafer, thereby causing dust.

【0005】そして、従来の微粒子除去装置では、例え
ば、ロードロック室11に設けた真空排気口14からガ
スの真空排気を行うとともに、反応室12で発生した微
粒子を同時に排気するようにしている。
In the conventional particle removing apparatus, for example, the gas is evacuated from the vacuum exhaust port 14 provided in the load lock chamber 11 and the particles generated in the reaction chamber 12 are simultaneously exhausted.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、上記の
ような構成では、ただ単にロードロック室11を真空排
気するだけであるため、ダストの原因となる微粒子(パ
ーティクル)の除去が不充分である。
However, in the above configuration, since the load lock chamber 11 is merely evacuated, the removal of fine particles (particles) causing dust is insufficient.

【0007】[0007]

【課題を解決するための手段】そこで、本発明は、上記
問題点を解決するために、微粒子を積極的に帯電させる
ことにより、電気力線を発生させてイオンの流れを形成
し、微粒子を効率的に除去するようにしたものである。
In order to solve the above-mentioned problems, the present invention solves the above-mentioned problems by positively charging the fine particles, thereby generating lines of electric force to form a flow of ions, thereby reducing the fine particles. It is designed to remove it efficiently.

【0008】すなわち、請求項1記載の発明では、真空
室を備えるとともに、この真空室内には真空排気口が開
設されている半導体ウェハ処理装置において、真空室
に、ガスまたは微粒子を帯電させる電極が設置されてい
ることを特徴としている。
That is, according to the first aspect of the present invention, in a semiconductor wafer processing apparatus provided with a vacuum chamber and having a vacuum exhaust port in the vacuum chamber, an electrode for charging gas or fine particles is provided in the vacuum chamber. It is characterized by being installed.

【0009】請求項2記載の発明では、請求項1記載の
構成において、真空室に対して、その内部のガスまたは
微粒子を帯電させる紫外光源が設置されている。
According to the second aspect of the present invention, in the configuration of the first aspect, an ultraviolet light source for charging gas or fine particles inside the vacuum chamber is installed in the vacuum chamber.

【0010】請求項3記載の発明では、請求項1または
請求項2記載の構成において、真空室は、半導体ウェハ
の処理室と、この処理室に接続されたロードロック室と
からなり、前記ロードロック室の処理室側に陰極が、前
記真空排気口側に陽極がそれぞれ配置されていることを
特徴としている。
According to a third aspect of the present invention, in the configuration of the first or second aspect, the vacuum chamber comprises a semiconductor wafer processing chamber and a load lock chamber connected to the processing chamber. A cathode is disposed on the processing chamber side of the lock chamber, and an anode is disposed on the vacuum exhaust port side.

【0011】請求項4記載の発明では、請求項3記載の
構成において、陽極の近傍に微粒子捕獲用のフィルタが
設置されていることを特徴としている。
According to a fourth aspect of the present invention, in the configuration of the third aspect, a filter for capturing fine particles is provided near the anode.

【0012】[0012]

【発明の実施の形態】図1は本発明の実施形態に係る半
導体ウェハ処理装置を平面的に見た概略構成図、図2は
同装置を側面から見た概略構成図である。
FIG. 1 is a schematic structural view of a semiconductor wafer processing apparatus according to an embodiment of the present invention as viewed in plan, and FIG. 2 is a schematic structural view of the same apparatus as viewed from the side.

【0013】図1において、11はロードロック室、1
2は一対の反応室、13は半導体ウェハの搬送系、14
は真空排気口、15は搬送系13を構成する半導体ウェ
ハ載置用の一対のアームであり、これらの構成は、図5
に示した従来技術の装置と同じであるから、詳しい説明
は省略する。
In FIG. 1, reference numeral 11 denotes a load lock chamber, 1
2 is a pair of reaction chambers, 13 is a semiconductor wafer transfer system, 14
Is a vacuum exhaust port, and 15 is a pair of arms for mounting a semiconductor wafer constituting the transfer system 13. These structures are shown in FIG.
Is the same as the prior art device shown in FIG.

【0014】この実施形態では、ロードロック室11に
対して、ガスまたは微粒子を帯電させる電極としての陰
極21および陽極22、さらに紫外光源23が設置され
ている。
In this embodiment, a cathode 21 and an anode 22, which are electrodes for charging gas or fine particles, and an ultraviolet light source 23 are installed in the load lock chamber 11.

【0015】すなわち、図2に示すように、ロードロッ
ク室11の各反応室12側に陰極21が、各真空排気口
14側に陽極22がそれぞれ配置され、陰極21と陽極
22には、それぞれ電源41が電源線42を介して接続
されており、電源41から電源線42を通じて陰極21
および陽極22にそれぞれ所定の電圧が印可されるよう
になっている。
That is, as shown in FIG. 2, a cathode 21 is arranged on each reaction chamber 12 side of the load lock chamber 11 and an anode 22 is arranged on each vacuum exhaust port 14 side. A power supply 41 is connected via a power supply line 42, and the cathode 21 is connected from the power supply 41 through a power supply line 42.
A predetermined voltage is applied to the anode 22 and the anode 22, respectively.

【0016】また、紫外光源23は、ロードロック室1
1の外側に配置され、ガラスやアクリル樹脂でできた窓
25を通して紫外光がロードロック室11内部に照射さ
れるようになっている。
The ultraviolet light source 23 is connected to the load lock chamber 1.
1 is arranged outside, and the inside of the load lock chamber 11 is irradiated with ultraviolet light through a window 25 made of glass or acrylic resin.

【0017】いま、反応室12でエッチングプロセスが
行われる場合、反応室12ではプロセスガスや反応生成
物によって微粒子が発生し、これがウェハ移載の時に反
応室12側からロードロック室11側に流入する。例え
ば、エッチングガスが塩素であれば、ロードロック室1
1に塩素がたまり、ロードロック室11内が汚染される
おそれがある。
When an etching process is performed in the reaction chamber 12, fine particles are generated in the reaction chamber 12 by a process gas or a reaction product, and flow into the load lock chamber 11 from the reaction chamber 12 when transferring a wafer. I do. For example, if the etching gas is chlorine, the load lock chamber 1
There is a possibility that chlorine accumulates in the first and the inside of the load lock chamber 11 is contaminated.

【0018】そこで、その場合には、電源41から電源
線42を通して陰極21および陽極22にそれぞれ所定
の電圧を印可する。すると、反応室12から出るエッチ
ングガスは、反応室12近傍に設置されている陰極21
により負に帯電する。その際、紫外光源23によって、
ロードロック室11内を紫外光で照射すると、さらに微
粒子のイオン化が促進される。
In this case, a predetermined voltage is applied to the cathode 21 and the anode 22 from the power supply 41 through the power supply line 42. Then, the etching gas exiting from the reaction chamber 12 is supplied to the cathode 21 provided near the reaction chamber 12.
To be negatively charged. At that time, by the ultraviolet light source 23,
When the inside of the load lock chamber 11 is irradiated with ultraviolet light, ionization of the fine particles is further promoted.

【0019】そして、負に帯電した微粒子は、クーロン
力によって直ちに陰極21と陽極22から形成される電
気力線31に沿って陽極22方向へ電気的に引き寄せら
れ、真空排気口14から真空ポンプ(図せず)を経由して
ロードロック室11の外部に効率良く排出されるため、
ロードロック室11内の汚染はほとんど発生しない。
The negatively charged fine particles are immediately attracted by the Coulomb force to the anode 22 along the line of electric force 31 formed by the cathode 21 and the anode 22, and the vacuum pump ( (Not shown) to efficiently discharge the load lock chamber 11 to the outside.
Contamination in the load lock chamber 11 hardly occurs.

【0020】このように、反応室12側から発生するエ
ッチングガスおよび反応生成物等によるパーティクル
(微粒子)を、ただ単に真空排気するだけでなく、陰極2
1と陽極22とにより電気力線31を発生させて帯電し
た微粒子の流れ32を形成することにより、微粒子を有
効に除去することができる。
As described above, particles due to the etching gas and reaction products generated from the reaction chamber 12 side
(Particles) are not only evacuated, but also
By generating lines of electric force 31 by the anode 1 and the anode 22 to form a flow 32 of charged fine particles, the fine particles can be effectively removed.

【0021】なお、図3に示すように、陽極22を覆っ
てフィルタ61を設置することが一層好ましい。
As shown in FIG. 3, it is more preferable that a filter 61 is provided so as to cover the anode 22.

【0022】このようにすると、微粒子はフィルタ61
に付蓄して、陽極22には付蓄しないため、陽極22が
過剰に汚れることを防止することができる。
In this case, the fine particles are removed from the filter 61.
And the anode 22 is not stored, so that the anode 22 can be prevented from being excessively contaminated.

【0023】また、図1および図2に示した構成では、
電極21,22がともにロードロック室11内に配置さ
れているが、図4に示すように、ロードロック室11の
外側に電極21,22を配置することもできる。その場
合、陰極21および陽極22の形状は、ロードロック室
11を取りまくようなリング形状となる。
In the configuration shown in FIGS. 1 and 2,
Although the electrodes 21 and 22 are both disposed in the load lock chamber 11, the electrodes 21 and 22 may be disposed outside the load lock chamber 11 as shown in FIG. In that case, the shape of the cathode 21 and the anode 22 is a ring shape surrounding the load lock chamber 11.

【0024】さらに、この実施形態では、真空室とし
て、搬送を伴うロードロック室11を用いた場合につい
て説明したが、局所的な真空容器でも、同様の効果が得
られることは言うまでもない。
Further, in this embodiment, the case where the load lock chamber 11 with transfer is used as the vacuum chamber has been described, but it goes without saying that the same effect can be obtained even with a local vacuum vessel.

【0025】[0025]

【発明の効果】本発明の半導体ウェハ処理装置では、次
の効果を奏する。
According to the semiconductor wafer processing apparatus of the present invention, the following effects can be obtained.

【0026】(1) 真空室内に存在してダストの元とな
る微粒子を陰極により負に帯電した後、帯電した微粒子
を陽極方向ヘクーロン力により引きつけることにより、
微粒子の流れを形成することができるため、電気力線を
広範囲に発生させて、真空中の微粒子を効率良く外部に
排出することができる。これによって、ダストの発生を
大幅に抑えて良好な真空状態を保持することができる。
(1) After the fine particles that are present in the vacuum chamber and are the source of dust are negatively charged by the cathode, the charged fine particles are attracted by Coulomb force in the anode direction.
Since the flow of the fine particles can be formed, the lines of electric force can be generated in a wide range, and the fine particles in a vacuum can be efficiently discharged to the outside. As a result, the generation of dust can be significantly suppressed and a favorable vacuum state can be maintained.

【0027】(2) 特に、紫外光源によって真空室内を
紫外光で照射すると、さらに微粒子のイオン化が促進さ
れるため微粒子の排出が良くなる。
(2) In particular, when the vacuum chamber is irradiated with ultraviolet light by an ultraviolet light source, ionization of the fine particles is further promoted, so that discharge of the fine particles is improved.

【0028】(3) また、陽極を覆ってフィルタを設置
すれば、微粒子が陽極に付蓄して汚れるのを防止するこ
とができる。
(3) If a filter is provided so as to cover the anode, it is possible to prevent fine particles from accumulating on the anode and becoming dirty.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態に係る半導体ウェハ処理装置
を平面的に見た概略構成図
FIG. 1 is a schematic configuration diagram showing a planar view of a semiconductor wafer processing apparatus according to an embodiment of the present invention.

【図2】図1の装置を側面から見た概略構成図FIG. 2 is a schematic configuration diagram of the apparatus of FIG. 1 as viewed from the side.

【図3】陽極の回りにフィルタを設置した図FIG. 3 shows a filter installed around an anode.

【図4】陰極および陽極をロードロック室の外側に配置
した図
FIG. 4 is a diagram in which a cathode and an anode are arranged outside a load lock chamber.

【図5】従来例に係る半導体ウェハ処理装置を平面的に
見た概略構成図
FIG. 5 is a schematic configuration diagram showing a planar view of a conventional semiconductor wafer processing apparatus.

【符号の説明】[Explanation of symbols]

11…ロードロック室、12…反応室、13…搬送系、
14…真空排気口、21…陰極、22…陽極、23…紫
外光源、61…フィルタ
11: load lock chamber, 12: reaction chamber, 13: transport system,
14 vacuum exhaust port, 21 cathode, 22 anode, 23 ultraviolet light source, 61 filter

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 真空室を備えるとともに、この真空室内
には真空排気口が開設されている半導体ウェハ処理装置
において、 前記真空室に、ガスまたは微粒子を帯電させる電極が設
置されていることを特徴とする半導体ウェハ処理装置。
1. A semiconductor wafer processing apparatus having a vacuum chamber and having a vacuum exhaust port opened in the vacuum chamber, wherein an electrode for charging gas or fine particles is installed in the vacuum chamber. Semiconductor wafer processing apparatus.
【請求項2】 前記真空室に対して、その内部のガスま
たは微粒子を帯電させる紫外光源が設置されていること
を特徴とする請求項1記載の半導体ウェハ処理装置。
2. The semiconductor wafer processing apparatus according to claim 1, wherein an ultraviolet light source for charging gas or fine particles inside the vacuum chamber is provided in the vacuum chamber.
【請求項3】 前記真空室は、半導体ウェハの処理室
と、この処理室に接続されたロードロック室とからな
り、前記ロードロック室の処理室側に陰極が、前記真空
排気口側に陽極がそれぞれ配置されていることを特徴と
する請求項1または請求項2記載の半導体ウェハ装置。
3. The vacuum chamber includes a semiconductor wafer processing chamber and a load lock chamber connected to the processing chamber. A cathode is provided on the load lock chamber on the processing chamber side and an anode is provided on the vacuum exhaust port side. The semiconductor wafer device according to claim 1 or 2, wherein each of the semiconductor wafer devices is arranged.
【請求項4】 前記陽極の近傍に微粒子捕獲用のフィル
タが設置されていることを特徴とする請求項3記載の半
導体ウェハ処理装置。
4. The semiconductor wafer processing apparatus according to claim 3, wherein a filter for capturing fine particles is provided near the anode.
JP1546898A 1998-01-28 1998-01-28 Semiconductor wafer processing apparatus Pending JPH11214364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1546898A JPH11214364A (en) 1998-01-28 1998-01-28 Semiconductor wafer processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1546898A JPH11214364A (en) 1998-01-28 1998-01-28 Semiconductor wafer processing apparatus

Publications (1)

Publication Number Publication Date
JPH11214364A true JPH11214364A (en) 1999-08-06

Family

ID=11889641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1546898A Pending JPH11214364A (en) 1998-01-28 1998-01-28 Semiconductor wafer processing apparatus

Country Status (1)

Country Link
JP (1) JPH11214364A (en)

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US8043667B1 (en) 2004-04-16 2011-10-25 Novellus Systems, Inc. Method to improve mechanical strength of low-K dielectric film using modulated UV exposure
US8062983B1 (en) 2005-01-31 2011-11-22 Novellus Systems, Inc. Creation of porosity in low-k films by photo-disassociation of imbedded nanoparticles
US8211510B1 (en) 2007-08-31 2012-07-03 Novellus Systems, Inc. Cascaded cure approach to fabricate highly tensile silicon nitride films
US8282768B1 (en) 2005-04-26 2012-10-09 Novellus Systems, Inc. Purging of porogen from UV cure chamber
US8398816B1 (en) 2006-03-28 2013-03-19 Novellus Systems, Inc. Method and apparatuses for reducing porogen accumulation from a UV-cure chamber
US8426778B1 (en) 2007-12-10 2013-04-23 Novellus Systems, Inc. Tunable-illumination reflector optics for UV cure system
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US8951348B1 (en) 2005-04-26 2015-02-10 Novellus Systems, Inc. Single-chamber sequential curing of semiconductor wafers
US8980769B1 (en) 2005-04-26 2015-03-17 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US9050623B1 (en) 2008-09-12 2015-06-09 Novellus Systems, Inc. Progressive UV cure
US9659769B1 (en) 2004-10-22 2017-05-23 Novellus Systems, Inc. Tensile dielectric films using UV curing
US9847221B1 (en) 2016-09-29 2017-12-19 Lam Research Corporation Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing
US10037905B2 (en) 2009-11-12 2018-07-31 Novellus Systems, Inc. UV and reducing treatment for K recovery and surface clean in semiconductor processing
US10388546B2 (en) 2015-11-16 2019-08-20 Lam Research Corporation Apparatus for UV flowable dielectric

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US8043667B1 (en) 2004-04-16 2011-10-25 Novellus Systems, Inc. Method to improve mechanical strength of low-K dielectric film using modulated UV exposure
US9659769B1 (en) 2004-10-22 2017-05-23 Novellus Systems, Inc. Tensile dielectric films using UV curing
JP2006165579A (en) * 2004-12-09 2006-06-22 Asml Netherlands Bv Lithographic apparatus and device manufacturing method
US8062983B1 (en) 2005-01-31 2011-11-22 Novellus Systems, Inc. Creation of porosity in low-k films by photo-disassociation of imbedded nanoparticles
US8980769B1 (en) 2005-04-26 2015-03-17 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US8282768B1 (en) 2005-04-26 2012-10-09 Novellus Systems, Inc. Purging of porogen from UV cure chamber
US10121682B2 (en) 2005-04-26 2018-11-06 Novellus Systems, Inc. Purging of porogen from UV cure chamber
US8889233B1 (en) 2005-04-26 2014-11-18 Novellus Systems, Inc. Method for reducing stress in porous dielectric films
US8951348B1 (en) 2005-04-26 2015-02-10 Novellus Systems, Inc. Single-chamber sequential curing of semiconductor wafers
US9873946B2 (en) 2005-04-26 2018-01-23 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
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