JPH11214518A - Placement and wiring equipment - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To perform processing of arranging and wiring in an arbitrary wiring layer and performing backing wiring in an arbitrary wiring layer in a multilayer wiring process. SOLUTION: By providing a pin wiring layer lifting portion 7, a pin is generated in an arbitrary wiring layer in a wiring layer for manufacturing a pin of a cell, the types of wiring layers that can be arranged and wired are increased, and the arrangement is increased. Increase the flexibility of wiring. By providing the priority wiring layer designating section 6, arrangement and wiring is performed centering on the designated wiring layer, and a wiring layer having low resistance is designated in terms of process, thereby increasing the speed. Specifying the uppermost wiring layer facilitates circuit correction by FIB and analysis by EB tester. By providing the backing wiring portion 8, the backing wiring is performed, the resistance of the wiring is reduced without increasing the wiring width, and the speed is increased. Backing with a wiring layer having a low wiring density increases the chip aperture ratio and increases the manufacturing yield.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a wiring arrangement apparatus used when designing a semiconductor mask layout by wiring arrangement.

[0002]

2. Description of the Related Art Conventionally, when a semiconductor mask layout is designed by placement and wiring, logical connection information created from a circuit diagram and a cell library in which cells are registered are
A method is used in which a logical arrangement and wiring is performed by arrangement and wiring.

Hereinafter, a conventional placement and routing apparatus will be described. FIG. 4 is a block diagram of a conventional placement and routing apparatus.
Is an input unit, 2 is a CPU which processes data with information input from the input unit 1, 3 is a cell library in which cells are registered, 4
Is a logical arrangement and wiring unit for selectively synthesizing data of the CPU 2 and the cell library 3 to perform arrangement and wiring, and 5 is an output unit for outputting the result of the CPU 2.

FIG. 5 is a plan view after the conventional arrangement and wiring. Reference numeral 10 denotes a cell X, 11 denotes a cell Y, 12 denotes a pin a of the pin a of the cell X10, and 13 denotes a pin of the pin b of the cell Y11. Pin, 14 is wiring from the first layer pin 12, 15 is the second layer pin 1
Wirings 3 and 16 are contacts for connecting the wirings 14 and 15.

FIG. 6 shows a cross-sectional structure between points A and B in FIG. In FIG. 6, reference numeral 20 denotes a semiconductor substrate, 21 denotes a LOCOS, 22 denotes a first interlayer film, and 23 denotes a second interlayer film.
An interlayer film, 24 a third interlayer film, 25 a fourth interlayer film, 26 a protective film, 27 a one-layer wiring, 28 a first via hole, 29
Is a two-layer wiring.

The operation of the arrangement and wiring apparatus configured as described above will be described below. First, the input unit 1 shown in FIG.
Is selected by the CPU 2. At this time, the CPU 2 extracts the logical connection information of the cell indicating that the pin a of the cell X10 and the pin b of the cell Y11 in the circuit diagram input from the input unit 1 are connected. Next, the logical connection information is sent to the logical arrangement and wiring unit 4. Next, the data of the cell X10, the cell Y11, and the contact 16 in the cell library 3 in which the cell has been registered are transferred to the logical layout and wiring unit 4 and the CPU.
Send to 2. At this time, the CPU 2 extracts reference wiring layer information that the wiring layer of the pin a of the cell X10 is the single-layer pin 12 and the wiring layer of the pin b of the cell Y11 is the second layer pin 13. Next, the reference wiring layer information is sent to the logical placement and wiring unit 4. At this time, the logical arrangement and wiring unit 4
Based on the reference wiring layer information and the logical connection information from U2, it is determined that the wiring 14 from the pin a of the cell X10 is to be wired by the single layer wiring 27, and the wiring 15 from the pin b of the cell Y11 is two layers. It is determined that wiring is to be performed using the wiring 29. At the same time, the contact 16 is required to connect the wiring 14 and the wiring 15 to satisfy the logical connection information, and it is determined that the first via hole 28 is used for the contact 16. Next, the layout wiring of the cell X10 and the cell Y11 is performed using the first layer wiring 27, the first via hole 28, and the second layer wiring 29. As a result, the mask layout data of the circuit diagram input by the input unit 1 is output from the output unit 5.

[0007]

However, in the above-mentioned conventional configuration, the placement and routing is performed with reference to the pin wiring layer of the cell registered in the cell library 3. However, this placement and routing is performed with reference to the pin wiring layer. In addition, there is a problem that the operation can be performed only in the direction from the lower layer to the upper layer, and the wiring layer of the arrangement wiring and the wiring layer direction at the time of wiring cannot be freely designated. Therefore, in the case of the multi-layer wiring process, the wiring density becomes lower toward the upper layer, and the correction by the FIB and the EB
There was a problem that analysis with a tester was difficult.

Further, there is only one wiring from pin to pin, and there is a problem that when the resistance of the wiring is reduced, the width of the wiring is increased and the wiring area is increased. The present invention solves the above-mentioned conventional problems.When designing a semiconductor mask layout by placement and routing, cells can be placed and routed in any wiring layer that is not restricted by the wiring layer of the pin defined first, It is an object of the present invention to provide an arrangement and wiring apparatus in which a wiring layer direction in which wiring is performed can be set freely and backing wiring can be performed in an arbitrary wiring layer.

[0009]

In order to solve this problem, a placement and routing apparatus according to the present invention is provided in which a cell pin is generated in an arbitrary wiring layer in a wiring layer to be manufactured, and a designated wiring layer is provided. , And the arrangement and wiring for freely setting the direction of the wiring layer to be wired are performed, and the backing wiring is performed in an arbitrary wiring layer.

[0010] Thus, when designing a semiconductor mask layout by arrangement and wiring, an arrangement and wiring apparatus can be obtained, which can be arranged and wired in an arbitrary wiring layer and can perform backing wiring in an arbitrary wiring layer.

[0011]

According to the present invention, a CPU for processing data with information input from an input unit, a cell library in which cells are registered, and data of the CPU and the cell library are selectively stored. A placement and routing apparatus having a logic placement and routing unit for combining and placing and routing, and an output unit for outputting a result of the CPU, further includes generating pins corresponding to any wiring layer for manufacturing pins in the cell. And a pin wiring layer lifting section for performing the following.

Thus, pins can be generated in an arbitrary wiring layer in the multilayer wiring process.

According to a second aspect of the present invention, a CPU for processing data with information input from an input unit, a cell library in which cells are registered, and data of the CPU and the cell library are selectively synthesized and arranged. A placement and routing apparatus having a logical placement and routing unit for performing routing and an output unit for outputting a result of the CPU, further comprising a priority wiring layer designating unit for designating a priority wiring layer of a circuit diagram; Are configured to perform logical connection centering on the wiring layer specified by the priority wiring layer specifying unit.

Thus, the arrangement and wiring can be performed centering on the specified wiring layer.

According to a third aspect of the present invention, there is provided a CPU for processing data with information input from an input unit, a cell library in which cells are registered, and data of the CPU and the cell library selectively synthesized and arranged. A placement and routing apparatus including a logical placement and routing unit for performing routing and an output unit for outputting a result of the CPU further includes a backing routing unit for performing backing routing of the placement and routing.

Thus, the wiring resistance from pin to pin can be reduced by the backing wiring portion.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 1 shows a block diagram of a placement and routing apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 6 denotes a priority wiring layer designating unit for designating which wiring layer in the multilayer wiring is to be preferentially placed and routed, and 7 designates a pin wiring layer of a cell registered in the cell library 3 as desired. Reference numeral 8 denotes a backing wiring portion which performs backing wiring with respect to the wiring at the time of placement and wiring. 1 is an input unit, 2 is a CPU,
Reference numeral 3 denotes a cell library, 4 denotes a logical arrangement and wiring unit, and 5 denotes an output unit, which are the same as those of the conventional example.

FIG. 2 is a plan view after the arrangement and wiring according to the embodiment of the present invention, wherein 17a is a pin corresponding to the multilayer wiring of the pin a of the cell X10, 17b is a pin corresponding to the multilayer wiring of the pin b of the cell Y11, 18 Is the pin a of the cell X10 and the cell Y11
And 19 is a backing wire connecting the pin a of the cell X10 and the pin b of the cell Y11. The cell X10 and the cell Y11 have the same configuration as the conventional example.

FIG. 3 shows a cross-sectional structure between points A and B in FIG. Here, reference numeral 30 denotes a second via hole, 31 denotes a three-layer wiring, 32 denotes a third via hole, and 33 denotes a four-layer wiring. 20 is a semiconductor substrate, 21 is a LOCOS, 22 is a first substrate.
An interlayer film, 23 is a second interlayer film, 24 is a third interlayer film, 25 is a fourth interlayer film, 26 is a protective film, 27 is a single layer wiring, 28 is a first via hole, and 29 is a two layer wiring. This is the same as the configuration of the conventional example.

The operation of the arrangement and wiring apparatus configured as described above will be described below. First, the circuit diagram input to the input unit 1 in FIG.
At this time, the CPU 2 extracts cell logical connection information indicating that the pin a of the cell X10 and the pin b of the cell Y11 of the circuit diagram input from the input unit 1 are connected. Next, the logical connection information is sent to the logical arrangement wiring unit 4 and the backing wiring unit 8. Further, the CPU sends the number of manufacturable wiring layers and the priority wiring information input from the input unit 1 and a signal for backing wiring to the priority wiring layer designation unit 6.

The priority wiring layer designating section 6 creates reference wiring layer information for judging that the four-layer wiring 33 is mainly used for the logical layout wiring and the two-layer wiring 29 is mainly used for the backing wiring.
This reference wiring layer information is sent to the pin wiring layer lifting section 7, the logical arrangement wiring section 4, and the backing wiring section 8. Further, the data of the cell X10 and the cell Y11 in the cell library 3 in which the cell is registered is sent to the CPU 2 and the pin wiring layer lifting section 7.

The CPU 2 determines that the wiring layer of the pin a of the cell X10 is the single-layer pin 12 and that the wiring layer of the pin b of the cell Y11 is the two-layer pin 13, and initializes the determined pin. Wiring layer information is transferred to pin wiring layer lifting section 7
Send to

In the pin wiring layer lifting section 7, the cell X10
Pin a of the cell Y11 and the pin b of the cell Y11,
Replace with 17b. At the same time, judging from the reference wiring layer information and the initial wiring layer information, it is determined that the pin a of the cell X10 is not one layer of the initial but two layers of the reference wiring layer information.
Change the attributes of the pins so that you can place and route them in layers.
At the same time, the attribute of the pin b is changed so that the pin b of the cell Y11 can be arranged and wired not only in the initial two layers but also in the second and fourth layers of the reference wiring layer information. Next, the data of the changed cells X10 and Y11 is sent to the cell library 3.

Next, the data of the cell X10 and the cell Y11 in the cell library 3 are sent to the logical arrangement and wiring section 4. The logical arrangement and wiring unit 4 determines to perform the arrangement and wiring based on the reference wiring information, and performs the logical arrangement and wiring of the pin a of the cell X10 and the pin b of the cell Y11 by the four-layer wiring 33.

The backing wiring section 8 determines to perform backing wiring based on the reference wiring information, and performs backing wiring between the pin a of the cell X10 and the pin b of the cell Y11 using the two-layer wiring 29.

As a result, the mask layout data of the circuit diagram input by the input unit 1 is output from the output unit 5.

As described above, according to this embodiment, the pin wiring of the cell is set to an arbitrary wiring layer by the pin wiring layer lifting section 7, so that the arrangement and wiring can be performed at an arbitrary wiring layer. In addition, by specifying the wiring layer to be used preferentially by the priority wiring layer specifying unit 6, it is possible to select a wiring with good characteristics or use a wiring that is easy to analyze. In addition, by freely setting the direction of the wiring layer where the wiring is performed, the degree of freedom of the arrangement wiring can be increased. By backing with an arbitrary wiring by the backing wiring portion 8, the resistance from pin to pin can be reduced, and the manufacturing yield of the wiring portion can be increased.

In the above-described embodiment, the multi-layer wiring corresponding pins which can be used in all the wiring layers at the pin positions of the cell are used. May be assigned respectively.
Further, when it is not possible to create a necessary wiring layer pin at the cell pin position, a pin may be created beyond the cell frame, and the cell frame may be defined again to create a cell.

[0029]

According to the present invention, by providing a pin wiring layer lifting portion, a pin can be generated in an arbitrary wiring layer in a wiring layer for manufacturing a pin of a cell, and a type of wiring layer that can be arranged and wired. And the degree of freedom in arrangement and wiring can be increased.

Further, by providing the priority wiring layer designating section, it is possible to arrange and route the wiring with the designated wiring layer as a center, and it is possible to specify a wiring layer having a low resistance in terms of process and to increase the speed. If the uppermost wiring layer is designated, circuit correction by FIB and analysis by EB tester can be easily performed. In addition, by freely setting the wiring layer direction of the wiring, a wiring method from the upper layer to the lower layer can be adopted as compared with the conventional wiring method from the lower layer to the upper layer, and the degree of freedom in the arrangement and wiring method can be increased.

By providing the backing wiring portion, the backing wiring can be performed, and the resistance of the wiring can be reduced without increasing the wiring width, and the speed can be increased. In particular, in the miniaturization process, the delay in wiring becomes dominant, so that the effect of increasing the speed is great. By backing with a wiring layer with low wiring density,
The manufacturing yield can be increased by increasing the chip aperture ratio.

Thus, according to the present invention, when designing a semiconductor mask layout by placement and routing, placement and routing can be performed on any wiring layer that is not restricted by the wiring layer of the pin whose cell is first defined, At that time, the direction of the wiring layer for wiring can be freely set. Further, it is possible to realize an excellent arrangement and wiring device that can perform backing wiring with an arbitrary wiring layer.

[Brief description of the drawings]

FIG. 1 is a block diagram of a placement and routing apparatus according to an embodiment of the present invention.

FIG. 2 is a plan view after arrangement and wiring according to the embodiment of the present invention.

FIG. 3 is a sectional view between a point A and a point B in FIG. 2;

FIG. 4 is a block diagram of a conventional placement and routing apparatus.

FIG. 5 is a plan view after a conventional arrangement and wiring.

6 is a cross-sectional view between point A and point B in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input part 2 CPU 3 Cell library 4 Logical arrangement wiring part 5 Output part 6 Priority wiring layer designation part 7 Pin wiring layer raising part 8 Backing wiring part

Claims (3)

[Claims] A CPU for processing data with information input from an input unit; a cell library in which cells are registered;
A placement and routing apparatus, comprising: a logic placement and routing unit for selectively combining data of a U and a cell library to perform placement and routing; and an output unit for outputting a result of the CPU, and further comprising: And a wiring device having a pin wiring layer lifting portion for generating a pin corresponding to any wiring layer. 2. A CPU for processing data with information input from an input unit, a cell library in which cells are registered,
1. A placement and routing apparatus, comprising: a logic placement and routing unit for selectively combining data of a U and a cell library to perform placement and routing; and an output unit for outputting a result of the CPU. A placement and routing apparatus comprising a priority wiring layer designating unit for designating a layer, wherein the logical placement and routing unit is configured to make a logical connection centering on the wiring layer designated by the priority wiring layer designating unit. 3. A CPU for processing data with information input from an input unit, a cell library in which cells are registered,
1. A placement and routing apparatus comprising: a logic placement and routing unit for selectively combining data of U and a cell library to perform placement and routing; and an output unit for outputting a result of a CPU, further comprising a backing wiring for the placement and routing. Placement and wiring apparatus provided with a backing wiring section for performing the following.