JPH11214617A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [Problem] Even if there is a sudden change in current consumption,
In addition, it supplies step-down power with low noise. SOLUTION: In a step-down power supply circuit 1 for supplying step-down power to peripheral circuits of a semiconductor integrated circuit device, when a standby mode is released, a control signal SM becomes a Hi signal, a switch SW1 is turned off, and a switch SW2 is turned on. Although the node a is switched from the power supply voltage V _CC to ground potential V _SS, the parasitic capacitance C _K of the gate, the voltage of the node a, to descend to the level gradually ground potential V _SS rather than abruptly become. Therefore, since the voltage at the node a immediately after the standby mode is released is high, the ON resistance of the transistor T5 is small, and even if the consumption current I _CC increases rapidly, the step-down voltage V _DL (clamped by the transistor T5) The voltage drop at node b) can be significantly reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology effective when applied to a stabilized supply of a step-down voltage supplied to a peripheral circuit by an internal power supply circuit.

[0002]

2. Description of the Related Art Semiconductor integrated circuit devices such as microcomputers are required to have low noise. The switching of a transistor is a factor of noise generation, and the noise tends to increase as the current flowing through the transistor increases.

According to studies made by the present inventors, in order to realize low noise, for example, in a step-down power supply circuit for generating an internal power supply voltage, a depletion type N-channel MOS (Metal Oxide Semiconductor) is used.
In other words, a so-called clamp-type step-down power supply circuit that generates a step-down voltage by clamping a power supply voltage by a transistor is used.

[0004] An example of this type of semiconductor integrated circuit device is described in detail in November 5, 1994.
Japan, published by Baifuma Co., Ltd., Kiyoo Ito (author), "Advanced Electronics I-9 Ultra LSI Memory" P26
7 to P277. In this document, DRAM (Dyn)
Amic Random Access Memory
The circuit system of the step-down power supply circuit as the internal power supply voltage generation circuit in y) is described.

[0005]

However, it has been found by the present inventors that the above-described step-down power supply circuit of the clamp system has the following problems.

That is, the depletion-type N-channel MOS transistor used for the voltage clamp has a very large ON resistance when energized, so that it consumes a large amount of power, such as supply to the entire peripheral circuit provided in the microcomputer. When used, there is a problem that the clamp voltage fluctuates greatly.

In particular, when the semiconductor integrated circuit device is released from the low power consumption mode, that is, the so-called standby mode, a large amount of current flows instantaneously, and the fluctuation range of the clamp voltage becomes very large. There is a risk of malfunction due to destruction of register information and the like.

An object of the present invention is to provide a semiconductor integrated circuit device which can supply a step-down power supply stably and with low noise even if there is a sudden fluctuation in current consumption.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the semiconductor integrated circuit device of the present invention, a clamp MOS transistor for generating a step-down voltage from a predetermined power supply voltage and a gate of the clamp MOS transistor having a power supply voltage or a reference potential based on a control signal. A step-down power supply comprising: switching means for switching and inputting any one of them; and voltage delay means for delaying the voltage drop time of the gate of the clamping MOS transistor when the connection of the switching means is switched from the power supply voltage to the reference potential. It has a circuit.

Further, in the semiconductor integrated circuit device according to the present invention, the clamp MOS transistor comprises a depletion type N-channel MOS transistor.

Further, the semiconductor integrated circuit device of the present invention
The voltage delay means comprises a capacitance element connected between the gate of the clamping MOS transistor and a reference potential.

Thus, even if a sudden change in the current consumption occurs when the standby mode is canceled, the voltage drop of the step-down voltage and the voltage change can be greatly reduced.

Further, in the semiconductor integrated circuit device according to the present invention, the delay means comprises a parasitic capacitance parasitic on a gate of the clamping MOS transistor.

As a result, it is not necessary to manufacture a new element, and the layout area can be reduced.

Furthermore, the semiconductor integrated circuit device of the present invention
MO for clamping that generates a step-down voltage from a predetermined power supply voltage
Switching means for switching and inputting either the power supply voltage or the correction voltage to the gate of the S transistor and the clamping MOS transistor based on the control signal, and when the connection of the switching means is switched from the power supply voltage to the correction voltage Voltage delay means for delaying the voltage drop time of the gate of the clamping MOS transistor, a reference voltage clamping MOS transistor for generating a reference voltage, and a reference voltage of the reference voltage clamping MOS transistor and a clamping MOS transistor. Performs differential amplification with the generated step-down voltage, increasing the voltage if the step-down voltage is lower than the reference voltage, and lowering the voltage if the step-down voltage is higher than the reference voltage. A step-down power supply circuit consisting of a differential amplifier that generates a correction voltage to stabilize the voltage Those were example.

Further, in the semiconductor integrated circuit device according to the present invention, the clamping MOS transistor is a depletion type N-channel MOS transistor.

Further, according to the semiconductor integrated circuit device of the present invention,
The voltage delay means comprises a capacitance element connected between the gate of the clamping MOS transistor and a reference potential.

Thus, even if the current consumed while the standby mode is released fluctuates, the optimum correction voltage corrected by the differential amplifier so that the step-down voltage becomes constant is input to the gate of the clamping MOS transistor. Therefore, the fluctuation of the step-down voltage due to the fluctuation of the current consumption can be greatly reduced, and the voltage drop of the step-down voltage can be significantly reduced even if the current consumption suddenly fluctuates when the standby mode is canceled.

Further, in the semiconductor integrated circuit device according to the present invention, the delay means includes a parasitic capacitance parasitic on a gate of the clamping MOS transistor.

As a result, it is not necessary to manufacture a new element, and the layout area can be reduced.

As described above, malfunctions and the like of the semiconductor integrated circuit device can be prevented, and the reliability can be greatly improved.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram of a step-down power supply circuit provided in a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is a step-down power supply according to the first embodiment of the present invention. 6 is a timing chart in a circuit.

In the first embodiment, the step-down power supply circuit 1
Is provided in, for example, a semiconductor integrated circuit device such as a single-chip microcomputer, and generates a step-down power supply to be supplied to peripheral circuits of the semiconductor integrated circuit device.

The step-down power supply circuit 1 has a P-channel MO
Transistors T1 and T2 made of S, N-channel MOS
Power supply transistor (clamp MOS transistor) composed of transistors T3 and T4, inverter Iv, and depletion type N-channel MOS
T5 and a capacitor C for stabilizing the power supply.

The transistor T5 has a sufficient drive capacity to supply a step-down voltage _VDL which is an internal power supply to peripheral circuits and the like.

[0029] One end of the transistor T1, T3, the power supply voltage V _CC supplied from the outside is supplied, the other end of the transistor T1, T3 are electrically connected to the gate of the transistor T5 ing.

Further, one connection of the transistors T2 and T4 is electrically connected to the ground potential V _SS, and the other connection of the transistors T2 and T4 is electrically connected to the gate of the transistor T5. ing.

The gates of the transistors T1 and T4 are electrically connected so that a control signal SM for setting the standby mode of the semiconductor integrated circuit device is input. Also, the inverter Iv is electrically connected so that the control signal SM is also input to the input portion thereof.
The output of v is electrically connected to the respective gates of the transistors T2 and T3.

A switch (switching means) SW1 is constituted by the transistors T1 and T3, and a switch (switching means) SW2 is constituted by the transistors T2 and T4.
Of the power supply voltage V _CC or the ground potential V _SS via the switches SW1 and SW2. The switches SW1 and SW2 constitute an input voltage switching unit 2.

Further, on one end of the transistor T5 is supplied with the power source voltage V _CC, etc. to the step-down voltage V _DL peripheral circuits each to be supplied from the other end of the transistor T5. One connection of a power stabilizing capacitor C is connected to the other connection of the transistor T5, and the other connection is electrically connected to the ground potential V _SS .

Next, the operation of the present embodiment will be described with reference to the timing charts of FIGS.

[0035] In Figure 2, the control signal SM from above to bottom, the voltage of the consumption current I _CC in the step-down voltage V _DL, the gate of the transistor T5 (node a) and the other end of the transistor T5 in (node b) The voltage, that is, the voltage of the step-down voltage _VDL is shown.

First, when the standby mode is set, the control signal SM is a Lo signal, the Lo signal of the control signal SM is input to the gates of the transistors T1 and T4, and the gates of the transistors T2 and T3. Is input with the Hi signal inverted by the inverter Iv.
Therefore, the switch SW1 is ON and the switch SW2 is OF
F, the voltage at the node a becomes the power supply voltage V _CC ,
Power supply voltage V _CC is output to node b.

When the control signal SM becomes Hi signal and the standby mode is released, the transistors T1 and T1
4 receives a Hi signal at the gate of the transistor T4.
2, the Lo signal inverted by the inverter Iv is input to the gate of T3, and the switch SW1 is turned off and the switch SW2 is turned on.

When the switch SW2 is turned on,
The node a is pulled from the power supply voltage V _CC to the level of the ground potential V _SS . However, as described above, the transistor T5 is a transistor having a sufficient drive capability and has a large gate size, so that the parasitic capacitance (voltage delay means) parasitic on this gate
Due to C _K , the voltage of the node a gradually decreases to the level of the ground potential V _SS .

Therefore, since the voltage at the node a immediately after the standby mode is released is high, the ON resistance of the transistor T5 is small, and the transistor T5 is clamped even when the current consumption I _CC increases sharply. The reduced voltage drop of the reduced voltage V _DL (node b) can be significantly reduced.

However, when there is no parasitic capacitance C _K , as shown by the dotted line in FIG. 2, the step-down voltage V _DL (node b) increases drastically due to an instantaneous increase in current consumption I _CC. The voltage will drop.

[0041] Thus, according to the first embodiment, the parasitic capacitance C _K of switches SW1, SW2 and the transistor T5, rapidly consumed current I _CC is also a clamped step-down voltage V _DL increases Since the voltage drop can be significantly reduced and a sharp voltage drop can be prevented, malfunction of the semiconductor integrated circuit device can be prevented.

(Embodiment 2) FIG. 3 is a circuit diagram of a step-down power supply circuit provided in a semiconductor integrated circuit device according to Embodiment 2 of the present invention.

In the second embodiment, the step-down power supply circuit 1a includes a differential amplifier SA, a transistor T11,
The above-described transistor T5 for clamp power supply, capacitor C for power supply stabilization, inverter Iv, switch SW
1 and SW2. This differential amplifier S
A corrects and reduces voltage fluctuations caused by fluctuations in the power consumption I _CC of peripheral circuits during normal operation.

The differential amplifier SA has a P-channel MO
The transistor (reference voltage clamping MOS transistor) T11 includes transistors T6 and T7 which are S and transistors T8 to T10 which are N-channel MOS.
Is a depletion type N-channel MOS, and generates a reference voltage V _REF used for the differential amplifier SA by a voltage clamp.

Further, the power supply voltage V _cc is supplied to one connecting portion of the transistors T6 and T7,
6, the gate of T7 is electrically connected to the other connection of the transistor T7.

One connection of the transistor T8 is electrically connected to the other connection of the transistor T6. One connection of the transistor T8 and the other connection of the transistor T6 are connected to the input voltage switching unit 2
Are electrically connected to one connecting portion of the transistor T2 and the other connecting portion of the transistor T4.

Further, one connection of the transistor T9 is electrically connected to the other connection of the transistor T7, and the other connection of the transistors T8 and T9 is
It is electrically connected to one connection portion of the transistor T10.

The other connecting portion of the transistor T10 is electrically connected to the ground potential V _SS, and has its gate connected to
Electrical connection is performed so that control signal SM is input.

The gate of the transistor T8 is electrically connected to the other connecting portion of the transistor T5, and the gate of the transistor T9 is connected to the transistor T11.
Is electrically connected to the other connecting portion. The power supply voltage V _CC is supplied to one connection portion of the transistor T11, and the gate thereof is electrically connected to the ground potential V _SS .

Next, the operation of the step-down power supply circuit 1a according to the second embodiment will be described.

First, when the standby mode is set and the control signal SM is a Lo signal, the transistor T
The Lo signal of the control signal SM is input to the gates of T1, T4 and T10, and the Hi signal inverted by the inverter Iv is input to the gates of the transistors T2 and T3.

Therefore, since the switch SW1 is turned on and the switch SW2 is turned off, the voltage at the node a becomes the power supply voltage V _CC , and the power supply voltage V _CC is output to the node b. Further, since the control signal SM of the transistor T10 is OFF, the differential amplifier SA is in an inactive state.

When the control signal SM becomes Hi signal and the standby mode is released, the transistors T1, T1
4 receives a Hi signal at the gate of the transistor T4.
2, the Lo signal inverted by the inverter Iv is input to the gate of T3, and the switch SW1 is turned off and the switch SW2 is turned on. At the same time, the Hi signal is also input to the gate of the transistor T10,
The differential amplifier SA is activated.

[0054] step-down voltage V _DL, which is clamped by the transistor T5 is supplied as an internal power source, is simultaneously input to the gate of the transistor T8.

When the step-down voltage V _DL clamped by the transistor T5 becomes higher than the reference voltage V _REF clamped by the transistor T11 when the current consumption I _CC of the peripheral circuit and the like becomes smaller,
Since the gate voltage of the transistor T8 increases, the transistor T8 flows more current, and the voltage at one connection (node d) of the transistor T8 decreases.

[0056] Thus, the gate voltage of the transistor T5 which is input through the switch SW2 is also lowered, voltage step-down voltage V _DL, which is clamped by the transistor T5 is lowered.

When the step-down voltage V _DL becomes lower than the reference voltage V _REF , the gate voltage of the transistor T8 decreases and the voltage at the node d increases, so the step-down voltage V _DL clamped by the transistor T5. Is also increased, and the step-down voltage _VDL is corrected and output.

[0058] Thus, in this second embodiment, in the standby mode is released, the step-down voltage V _DL, which is generated by the clamping of the transistor T5 so supplied while correcting the differential amplifier SA, the fluctuation of the consumption current I _CC The accompanying fluctuation of the step-down voltage _VDL can be greatly reduced.

Further, even if there is a sudden increase in the current consumption I _CC , the voltage drop of the clamped step-down voltage _VDL can be significantly reduced, and a sudden voltage drop can be prevented. Can be prevented.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the first and second embodiments, the gate voltage is slowly lowered by the parasitic capacitance of the transistor for the clamp power supply.
As shown in FIG. 5 may be a capacitor (capacitive element) C1 between the gate and the ground voltage V _SS of the transistor T5 of the clamping power of the step-down power supply circuit 1, 1a.

[0062] Also in this case, a sharp voltage drop of the step-down voltage _VDL can be significantly reduced.

[0063]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, since the gate voltage of the clamping MOS transistor can be slowly switched from the power supply voltage to the reference potential by the voltage delay means, a sudden increase in current consumption at the time of releasing the standby mode or the like is achieved. , The voltage drop and the voltage fluctuation of the step-down voltage can be greatly reduced.

(2) In the present invention, the use of the parasitic capacitance of the clamping MOS transistor as the voltage delay means makes it unnecessary to manufacture a new element and reduces the layout area.

(3) Further, according to the present invention, the correction voltage input to the gate of the clamping MOS transistor is generated by the differential amplifier, so that the fluctuation of the step-down voltage is greatly reduced even if the current consumption fluctuates. can do.

(4) According to the present invention, (1)
According to (3), malfunction of the semiconductor integrated circuit device can be prevented, and the reliability can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a step-down power supply circuit provided in a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a timing chart in the step-down power supply circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a step-down power supply circuit provided with a differential amplifier according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a step-down power supply circuit provided in a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 5 is a circuit diagram of a step-down power supply circuit provided with a differential amplifier according to another embodiment of the present invention.

[Explanation of symbols]

1 step-down power supply circuit 1a step-down power supply circuit 2 the input voltage switching unit T1, T2 transistors T3, T4 the transistor T5 transistors (clamping MOS transistor) T6～T10 transistor T11 the transistor (reference voltage clamping MOS transistor) Iv inverter C _K parasitic electrostatic Capacitance (voltage delay means) C1 capacitor (capacitance element) C capacitor SW1, SW2 switch (switching means) SA differential amplifier V _DL step-down voltage V _CC power supply voltage V _SS ground potential (reference potential) SM control signal I _CC consumption Electric power

Claims (8)

[Claims] 1. A clamping MOS transistor for generating a step-down voltage from a predetermined power supply voltage, and switching means for switching and inputting either a power supply voltage or a reference potential to a gate of the clamping MOS transistor based on a control signal. And a step-down power supply circuit comprising voltage delay means for delaying a voltage drop time of the gate of the clamping MOS transistor when connection of the switching means is switched from a power supply voltage to a reference potential. Semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein said clamping MOS transistor is a depletion type N-channel MOS transistor. 3. The semiconductor integrated circuit device according to claim 1, wherein said voltage delay means includes said clamp M
A semiconductor integrated circuit device comprising a capacitance element connected between a gate of an OS transistor and a reference potential. 4. The semiconductor integrated circuit device according to claim 1, wherein said delay means includes said clamp MOS.
A semiconductor integrated circuit device having a parasitic capacitance parasitic on a gate of a transistor. 5. A clamping MOS transistor for generating a step-down voltage from a predetermined power supply voltage, and switching means for switching and inputting either a power supply voltage or a correction voltage to a gate of the clamping MOS transistor based on a control signal. A voltage delay means for delaying a voltage drop time of a gate of the clamp MOS transistor when a connection of the switching means is switched from a power supply voltage to a correction voltage; and a reference voltage clamp MOS transistor for generating a reference voltage. Performing differential amplification between the reference voltage of the reference voltage clamping MOS transistor and the step-down voltage generated by the clamping MOS transistor, and increasing the voltage when the step-down voltage is lower than the reference voltage, If the voltage is higher than the reference voltage, lower the voltage The semiconductor integrated circuit device, characterized in that with more becomes step-down power supply circuit and a differential amplifier for generating a correction voltage to stabilize the voltage. 6. The semiconductor integrated circuit device according to claim 5, wherein said clamping MOS transistor is a depletion-type N-channel MOS transistor. 7. The semiconductor integrated circuit device according to claim 5, wherein said voltage delay means comprises said clamp M
A semiconductor integrated circuit device comprising a capacitance element connected between a gate of an OS transistor and a reference potential. 8. The semiconductor integrated circuit device according to claim 5, wherein said delay means comprises said MOS for clamping.
A semiconductor integrated circuit device having a parasitic capacitance parasitic on a gate of a transistor.