JPH11219997A - Electronic device inspection system and electronic device manufacturing method - Google Patents

Abstract

(57) Abstract: An object of the present invention is to reduce the inspection time without significantly lowering the production line yield. An object of the present invention is to reduce inspection time by consistently inspecting a limited area on a wafer in an electronic device manufacturing line. In particular, 300φ
For wafers with large diameters, etc., lack of uniformity within the wafer surface, and the value of inspection data detected between the wafer periphery and the wafer center is different. It was decided to increase the reliability of the test results by conducting more detailed tests. Further, an area to be inspected for each wafer is registered in a database or the like in advance, and each inspection apparatus downloads the area to be inspected from the database at the time of inspection and inspects the area. That is, the electronic device management system manages the inspection area on the wafer in each inspection apparatus so that a more preferable inspection area can be easily set in accordance with a product type, a product manufacturing situation, and the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device inspection system applied to an electronic device manufacturing line and a manufacturing method using the inspection system, and more particularly, to an electronic device system for shortening an inspection time and an inspection thereof. This is a technology related to a manufacturing method using a system.

[0002]

2. Description of the Related Art A conventional electronic device is formed by repeating a plurality of processing steps such as exposure, development, and etching on a wafer. On the other hand, the wafer processed in a predetermined processing step of the plurality of processing steps is inspected by a foreign substance inspection device or a visual inspection device or the like as needed, and the number, type, The size etc. are inspected. Hereinafter, the foreign matter to be detected by the foreign matter inspection device and the appearance defect to be detected by the appearance inspection device are collectively referred to as a defect.

[0003]

However, in the above-described inspection apparatus, the entire surface of the wafer is generally inspected, the inspection time is long, and the manufacturing period of the electronic device is lengthened. In particular, when the wafer diameter is increased to 300φ, the inspection time is further increased, and it is expected that the inspection time will be greatly affected.

[0004] It is an object of the present invention to reduce the inspection time without significantly reducing the production line yield.

[0005]

SUMMARY OF THE INVENTION The present invention reduces the inspection time by consistently inspecting a limited area on a wafer in an electronic device manufacturing line. In particular, for a wafer with a large diameter such as 300φ, the uniformity within the wafer surface is lacking, and the value of inspection data detected between the wafer periphery and the wafer center is different. It was decided to increase the reliability of the inspection results by performing more detailed inspections.

In addition, an area to be inspected for each wafer is registered in a database or the like in advance, and each inspection apparatus downloads the area to be inspected from the database at the time of inspection and inspects the area. That is, the electronic device management system manages the inspection area on the wafer in each inspection apparatus so that a more preferable inspection area can be easily set in accordance with a product type, a product manufacturing situation, and the like.

As a result, it is possible to suppress the inspection time of a single wafer, which increases with an increase in the diameter of the wafer. For example, it is possible to target several wafers in a lot without increasing the time required for inspection of one lot. Failure analysis of process traces and the like was made possible.

In addition, since the inspection area can be freely set in advance for each wafer, the inspection area can be selected according to the state of occurrence of defects in the manufacturing process, and more effective inspection can be performed. In addition, by limiting the inspection area, it is possible to finish the inspection within the inspection time allowed for the inspection process, and time consistency with the preceding and following manufacturing processes can be ensured, and the impact of product lot stagnation can be reduced. It has become possible to prevent it.

In addition, since it is possible to prevent inspection of a wafer whose wafer identifier is not registered in the database, it is possible to avoid acquisition of inspection data that cannot be connected to the preceding and following manufacturing processes due to an error of an analysis operator. It became.

The present invention will be described more specifically. To achieve the above object, the present invention provides a plurality of processing steps for processing a work to be an electronic device, and respective work steps processed in the different processing steps. And setting an inspection apparatus for inspecting the work to inspect a plurality of regions in the work, and inspecting each of the works processed in the different processing steps.

A plurality of areas set in the inspection apparatus are arranged at a first area for inspecting at least two continuous chips arranged in a peripheral area of the workpiece and at an inner circumference of the peripheral area. And a second area for testing at least two continuous chips. In this case, it is preferable to arrange a plurality of second regions arranged on the inner periphery so that the inner periphery can be inspected substantially uniformly.

Further, the plurality of areas set in the inspection apparatus include a plurality of areas in the work for inspecting at least two continuous chips arranged on the work. In this case, it is preferable to arrange the plurality of regions so that the inside of the work can be inspected substantially uniformly.

According to the present invention, in order to achieve the above object, a plurality of inspection apparatuses for inspecting a work serving as an electronic device are connected to the plurality of inspection apparatuses via a network, and the inspection apparatuses perform the inspection. An analysis unit having at least storage means for storing inspection area information representing an inspection area in the work, wherein the inspection area is transmitted to the inspection apparatus by transmitting the inspection area information stored by the analysis unit to the inspection apparatus. Is set.

[0014] Further, a plurality of pieces of inspection area information in which inspection areas in a work to be inspected by the inspection apparatus are different are stored in storage means of the analysis unit, and a plurality of pieces of inspection area information stored in the analysis unit are stored. Any one
One is transmitted to the inspection device.

Further, the inspection area information includes first information for inspecting at least two continuous chips arranged in a peripheral area of the work, and at least two continuous chips arranged on an inner periphery of the peripheral area. And the second information to be inspected. Also in this case, it is preferable to arrange a plurality of second regions arranged on the inner periphery so that the inner periphery can be inspected substantially uniformly.

The inspection area information includes information for inspecting at least two continuous chips arranged on the work in a plurality of areas in the work. Also in this case, it is preferable to arrange the plurality of regions so that the inside of the work can be inspected substantially uniformly.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing an entire configuration of an inspection system according to the present invention.

In FIG. 1, reference numeral 101 denotes a manufacturing process for processing a wafer; 102, various inspection apparatuses such as a foreign substance inspection apparatus and a visual inspection apparatus for inspecting a wafer being manufactured; 103, an inspection area of the wafer in the various inspection apparatuses 102; A database for storing inspection results of the various inspection devices 102,
Reference numeral 104 denotes an analyzer that registers the inspection area in the database 103 and performs analysis processing using the inspection results stored in the database 103, and 105 denotes a network connected to the inspection apparatus 102, the database 103, and the analyzer 104.

First, in the manufacturing line 101, after a wafer is loaded, processes such as film formation, exposure, and etching are repeated, and the wafer is processed through processes such as ion implantation as necessary.

The wafers that have passed through each of the manufacturing processing steps are subjected to an inspection apparatus 1 such as a foreign substance inspection apparatus or a visual inspection apparatus, if necessary.
02, and inspected for defects such as foreign matter attached to the wafer and defective appearance.

Here, the inspection in the inspection apparatus 102 will be described with reference to FIG.

First, when a wafer subjected to a predetermined process is inspected by the inspection apparatus 102, identification information of the wafer to be inspected is input to the analysis apparatus 104 (step 100). This identification information is a wafer number or the like.

Next, the analysis device 104 acquires inspection area information stored in the database 103 in advance based on the identification information (step 101). FIG. 3 shows an example of this inspection area information. The inspection area information is obtained by associating the wafer identification information with the coordinates indicating the inspection area. For example, the wafer 001 has 10 consecutive chips in the horizontal direction from the coordinates (4, 2) on the lower side of the wafer. It indicates that eight chips in a horizontal direction from the upper coordinate (5,15) chip of the wafer, the central coordinate (2,4) chip, the coordinate (4,4) and the like are inspected one chip at a time. FIG. 3 shows an inspection area for each chip so that the influence of a defect on a final product (chip) can be analyzed. Also,
The inspection area information to the foreign substance inspection apparatus is configured such that one inspection area includes at least two continuous chips. Similarly, the inspection area information to the visual inspection apparatus is configured such that one inspection area includes at least three consecutive chips.
This is necessary for each inspection device to accurately detect a defect.

Next, the analysis device 104 operates the database 1
Inspection area information obtained from the network 105
Is transmitted to the corresponding inspection apparatus 102 through the step (step 102).

FIG. 4 shows an example of the inspection apparatus 102. In the figure, reference numeral 401 denotes a defect detection unit for detecting a defect on a wafer; 402, a detection signal processing unit for processing an inspection result detected by the defect detection unit 401; and 403, inspection area information, inspection results, various control information, and the like. Memory, 404, a keyboard as an input device, 405, an ID reader as an input device, 406, a CRT as an output device, 407, a printer as an output device, 408, an external communication unit connected to a network, and 409, a wafer. Stage to put on,
A stage control unit 410 controls the movement of the stage 409.

In such a configuration, the inspection apparatus 102
Stores the transmitted inspection area information in the external communication unit 408
And stores it in the memory 403 (step 1
03).

Then, the stage control unit 410
Stage 409 based on the inspection area information stored in
Is controlled (step 104).

Then, the stage 409 is moved based on the inspection area information, and a defect existing in a desired area on the wafer is detected (step 105).

FIG. 5 is an image diagram showing an area to be inspected by the inspection apparatus 102. FIG. 5 shows a layout of the wafer 500 displayed for each chip, and a black area 501 in the figure shows an inspection area in the inspection apparatus 102. In the figure, rows to be inspected and rows not to be inspected in the wafer 500 are set. Further, the row to be inspected is set by setting a row for continuously inspecting a plurality of chips in a horizontal direction and a row for discontinuously inspecting some of a plurality of chips arranged in a horizontal direction. I have. Although not shown, it is preferable that each of the rows to be inspected is set to inspect at least two consecutive chips for the above-described reason. Then, a row to be inspected continuously in the horizontal direction is set to the wafer 50.
It is arranged above or below 0. A plurality of rows to be inspected continuously in the horizontal direction may be arranged vertically. When the area to be inspected is defined in units of rows as described above, the stage movement of the inspection apparatus in the row direction (either the X direction or the Y direction of the inspection apparatus) is smooth, so that the inspection speed is significantly reduced. There is nothing.

In general, defects detected from a wafer often appear as a specific distribution mode. For example, 30
In a wafer having a large diameter such as 0φ, a defect is likely to appear near the wafer. Therefore, as shown in FIG. 5, it is preferable to inspect the area where a defect is likely to appear in more detail. That is, since the weights of the inspection results in the wafer are different, the reliability of the inspection results is ensured by focusing the inspection on the region with the higher weight of the inspection results.

Next, the inspection apparatus 102 adds information such as a wafer processing step and a wafer number to the information such as the number of defects and the location where the defects are collected in this inspection, and
05 to the database 103 (step 106).

The analysis terminal 104 uses the information stored in the database 103 to perform a failure analysis such as a change in the number of defects or a process trace (step 107).
In order to perform the defect analysis such as the change in the number of defects and the process trace, it is necessary to inspect the same area in each wafer in the inspection after each process. Inspection is performed consistently using the area information, and the inspection result in that area is stored in the database 103. For example, in the inspection after the completion of the step A, the predetermined inspection chip is instructed to the inspection apparatus, and then in the inspection after the completion of the step C, the same inspection chip as the inspection area after the completion of the step A is instructed to the inspection apparatus. I do. The same applies to the inspection after the other steps. This makes it possible to perform defect analysis such as a temporal change in the number of defects between processes, a temporal change in the number of defects between wafers inspecting the same inspection area, and a process trace for identifying a process in which a defect appears. Inspection results can be obtained.

As described above, the same region is integrated throughout the manufacturing process so that the weighted region can be inspected with priority and the inspection results between processes can be compared (temporal transition of the number of defects, process trace, etc.). If the inspection is performed, the inspection time can be shortened without lowering the yield even if the limited area in each wafer is inspected. Reducing the inspection time leads to an improvement in the throughput of the production line, thereby improving the production efficiency. Here, the weighted area is an area that affects the yield, such as an area where defects are likely to occur and an area where defective chips are likely to occur.

In addition, the possibility of overlooking the occurrence of a sudden defect is reduced by inspecting areas other than the weighted areas to a certain degree to a certain extent, so that delays in countermeasures due to oversight of the occurrence of a defect are reduced and the yield is improved. Can be done. If a plurality of inspection areas other than the weighted area are prepared and inspected, the possibility of missing a defect is further reduced, and the yield is improved.

Further, since the instruction of the inspection area is transmitted via the network 105 according to the wafer, in a production line where a plurality of types are mixed, it is easy to set the inspection area according to the type. Becomes in this case,
What is necessary is just to include the type information of the wafer to be inspected in the above-mentioned identification information and set the inspection area for each type of the wafer to be inspected. In addition, even in the same product type, the distribution mode in which defects occur varies from the trial production period to the mass production period, so that the inspection area can be easily set according to the change.

As in the present embodiment, the inspection area may be set in advance in the inspection apparatus 102 without receiving the instruction of the inspection area from the analysis apparatus 104. In this case, use of a control card or the like improves usability.

Further, as shown in FIG. 1, the identification information of the wafer may be inputted from the inspection apparatus 102. In this case, the input identification information is sent to the analyzer 104.

Next, other inspection patterns will be described with reference to FIG.

In the drawing, an inspection pattern 601 is for inspecting a wafer uniformly. This inspection pattern
Since the entire surface of the wafer is uniformly inspected, it is effective to use it when the distribution of defects cannot be specified. Next, the inspection pattern 602 is to inspect the peripheral portion of the wafer with emphasis and to inspect the central portion evenly. This inspection pattern allows more detailed inspection around the wafer than the inspection pattern shown in FIG. Next, the inspection pattern 603 is to inspect mainly the peripheral portion except for the outermost periphery of the wafer, and to inspect the central portion evenly. It is effective to use this inspection pattern when the probability that the outermost chip becomes defective is extremely high. Next, the inspection pattern 604 is to inspect mainly the peripheral portion and the central portion of the wafer. Although not shown, it is needless to say that at least two continuous chips are preferably used as the inspection chips in these cases.

As a method of setting an inspection pattern,
As shown in FIG.
May be displayed, and a desired one may be selected from the displayed information. In this case, information associating each inspection pattern with inspection area information is stored in the database 103. That is, the apparatus is configured to acquire the corresponding inspection area information from the inspection pattern information selected corresponding to the wafer identification information to be inspected, and transmit the inspection area information to the inspection apparatus.

Next, a method of setting an inspection pattern using the inspection result of the probe inspection (electrical characteristic inspection) will be described.

FIG. 7 is an overall system diagram, and FIG.
In the system shown in FIG.
6 and a database 707 for storing the test results. In this test step 706, after the processing in all the manufacturing steps 701 is completed, the electrical characteristics of each chip formed on the wafer are inspected. More specifically, the tester determines whether all chips are good or bad. The collected inspection data is transmitted to the network 705
Is transmitted to the database 707 and stored.

When an inspection pattern is set in this system, for example, as shown in FIG. 8, a probe inspection result of a wafer of the same type as the inspected wafer is displayed as a P inspection data map on the analysis terminal 704 or the like. FIG. 8 shows that the chip with the symbol A is a defective chip.

If there is a regionality in the distribution of failures appearing in the P inspection data map (in this case, failures of category A are concentrated in the upper half of the wafer), the inspection area is determined based on this. To set. That is, as shown in FIG. 9, the inspection is set so as to focus on the upper half in which the defects are concentrated. This may be set based on the distribution of defective bits.

If the inspection is performed using the inspection area information set as described above, the inspection is performed with emphasis on the area that is likely to be defective, so that the inspection time can be shortened without significantly lowering the yield.

Next, the method of registering the inspection pattern described above will be described. As a registration method, as shown in FIG. 3, the coordinates indicating the inspection area may be input. However, in order to improve the usability, the chip layout of the corresponding type is displayed, and the layout is selected from among the layouts. It is preferable to register a test pattern by specifying a chip to be tested. In this case, a conversion file for converting the chip position into the coordinates of the corresponding chip is stored in a database or the like in advance, and by using this conversion file, it is possible to generate coordinates representing the corresponding inspection area from the specified chip position. it can. Naturally, it is also possible to generate coordinates representing the corresponding inspection area from the specified chip row by a similar conversion method.

Next, an example of setting the number of chips to be inspected (inspection area) described above will be described.

In general, if the inspection time in the inspection step of inspecting the work to be inspected is longer than the processing time in the processing step in which the wafer to be inspected has been processed, the amount of work in the inspection step increases, and the production time increases. The production efficiency of the entire line decreases. Therefore, it is preferable to make the inspection time in the inspection step shorter than the processing time in the processing step in order to improve production efficiency.

Therefore, the inspection allowable time which does not disturb the flow of the lot (wafer) in the manufacturing process is input via the analysis terminal 104, and the number of inspection chips is set based on the input inspection allowable time.

First, identification information of an inspection apparatus to be used is input via the analysis terminal 104.

Next, the analysis terminal 104 connects to the database 10
3 and transmits the identification information.

The database 103 that has received the identification information transmits information such as the inspection time of the corresponding identification information to the analysis terminal 104 from the stored inspection device data file. FIG. 11 is an example of the inspection data file. The inspection data file 1101 includes information on the identification information 1102 of the inspection device, the inspection time 1103, and the movement time 1104. Here, the inspection time 1103 is an inspection time per unit area, and the movement time 1104 is a time required for moving the chip from one row to another during the inspection.

Next, the analysis terminal 104 calculates the number of test chips from the function shown in Equation 1 by using the input permissible test time, the test time 1103 and the movement time 1104 obtained from the test apparatus data file 1101. Is calculated. That is, the number of test chips is determined so as not to exceed the allowable test time.

[0055]

(Equation 1)

As described above, by determining the number of test chips from the time given to the test and setting the test pattern based on the determined number of test chips, it is possible to suppress an increase in the amount of work in progress in the test apparatus, and Efficiency can be improved. Note that the above-described function is not limited to Equation 1, but may be any function that can determine the number of test chips from the time given to the test.
Needless to say, any function may be used.

Although the above-described embodiment has been described with a focus on semiconductor manufacture, the present invention is not limited to semiconductor manufacture, and products (eg, magnetic disks, circuit boards, Needless to say, the present invention can be applied to the production line of (1).

When the database is constituted by a server capable of performing analysis processing, the processing described so far may be performed by the server or by distributing the processing between the server and the analysis terminal. For example, the server that has received the instruction of the inspection chip from the analysis terminal may transmit the corresponding inspection area information to the inspection device.

It is not necessary to provide a separate database, and there is no problem if information stored in the database is stored in the storage means of the analysis terminal or the inspection device.

[0060]

According to the present invention, the inspection time can be reduced without significantly lowering the production line yield.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention.

FIG. 2 is a processing flowchart showing an embodiment of the present invention.

FIG. 3 is a data configuration diagram showing an embodiment of the present invention.

FIG. 4 is an apparatus configuration diagram showing an embodiment of the present invention.

FIG. 5 is an image diagram of a test chip showing an embodiment of the present invention.

FIG. 6 is an image diagram of a test chip showing an embodiment of the present invention.

FIG. 7 is a system configuration diagram showing an embodiment of the present invention.

FIG. 8 is a map diagram of an electrical characteristic test result showing one embodiment of the present invention.

FIG. 9 is an image diagram of a test chip showing an embodiment of the present invention.

FIG. 10 is a data configuration diagram showing an embodiment of the present invention.

[Explanation of symbols]

101, 701: manufacturing process, 102, 702: inspection apparatus, 103, 703, 707: database, 104,
704: analysis terminal, 105, 705: network, 4
01: defect detection unit, 402: detection signal processing unit, 403:
Memory, 404 ... keyboard, 405 ... ID reader, 40
6 CRT, 407 printer, 408 external communication unit, 4
09: stage, 410: stage controller, 706: test step.

Claims (7)

[Claims] 1. A plurality of inspection apparatuses for inspecting a work serving as an electronic device, and inspection area information that is connected to the plurality of inspection apparatuses via a network and indicates an inspection area in the work to be inspected by the inspection apparatus. An electronic device inspection system, comprising: an analysis unit having at least storage means for storing, and transmitting inspection area information stored by the analysis unit to the inspection apparatus to set an inspection area to be inspected by the inspection apparatus. . 2. A storage means of the analysis unit stores a plurality of pieces of inspection area information in which a plurality of inspection areas in a work to be inspected by the inspection apparatus are different, and among the plurality of pieces of inspection area information stored by the analysis unit, 2. The electronic device inspection system according to claim 1, wherein any one of them is transmitted to said inspection apparatus. 3. The inspection area information includes first information for inspecting at least two consecutive chips arranged in a peripheral area of the work, and at least two consecutive chips arranged on an inner periphery of the peripheral area. 3. The electronic device inspection system according to claim 1, further comprising: second information for inspecting the electronic device. 4. The inspection area information includes information for causing at least two continuous chips arranged on the work to be inspected in a plurality of areas in the work.
Or the electronic device inspection system according to 2. 5. An inspection apparatus for inspecting each of the workpieces processed in the different processing steps, wherein the inspection apparatus inspects each of the workpieces processed in the different processing steps. A plurality of regions to be inspected, and inspecting each of the workpieces processed in the different processing steps. 6. A plurality of areas to be set in the inspection apparatus are arranged in a first area for inspecting at least two continuous chips arranged in a peripheral area of the workpiece and an inner circumference of the peripheral area. 6. The method for manufacturing an electronic device according to claim 5, further comprising a second region for inspecting at least two continuous chips. 7. The electronic device according to claim 5, wherein the plurality of areas set in the inspection apparatus include a plurality of areas in the work for inspecting at least two continuous chips arranged on the work. Device manufacturing method.