JPH11233526A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A semiconductor device and a method of manufacturing the same, wherein a source electrode and a drain electrode are formed in a recess of a cap layer and are prevented from being connected to a gate electrode via the cap layer. Is manufactured easily and with good yield. SOLUTION: A channel layer 3 through which carriers pass and a high resistance cap layer 7 is formed on the channel layer 3, and the channel layer 3 is formed in a recess 7A in the cap layer 7.
A source electrode 12S for injecting carriers into the substrate and a drain electrode 12D for collecting carriers passing through the channel layer 3 in the recess 7A in the cap layer 7;
The gate electrode 11 is buried in the cap layer 7 between the source electrode 12S and the drain electrode 12D. 9 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MESFET (m
et al semiconductor field
effect transformer) or HEMT (h
high electron mobility tra
The present invention relates to a semiconductor device including a compound semiconductor field-effect transistor such as a semiconductor device and a method for manufacturing the same.

The above-mentioned semiconductor device is often used in a high frequency band because of its good high-frequency operation characteristics. However, since the gate electrode is in contact with the channel, the leakage current increases when the voltage applied to the gate electrode is increased. Becomes larger.

Therefore, there is a limitation on the voltage applied to the gate electrode, and as a result, it is said that a large output cannot be obtained from this type of semiconductor device. Means are disclosed.

[0004]

2. Description of the Related Art FIG. 3 is a cutaway side view showing a main part of a field effect transistor for explaining an improved conventional example. FIG. 4 is a sectional view showing an improved field effect transistor for explaining the improved conventional example. It is a principal part cut side view showing.

In each figure, 1 is a substrate, 2 is a buffer layer, 3 is a channel layer, 4 is a barrier layer, 5 is a spacer layer,
6 is a stopper layer, 7 is a cap layer, 8 is an n ⁺ region, 10
Is an insulating film, 11 is a gate electrode, 12S is a source electrode, 1
2D indicates a drain electrode.

The difference between the field effect transistors shown in FIGS. 3 and 4 is that the conventional example of FIG.
⁺ To form a region 8, a source electrode 12S to the n ⁺ region 8
Alternatively, in contrast to the structure in which the drain electrode 12D is in ohmic contact, the conventional example in FIG. Where you are.

An improvement of each of the field effect transistors shown in the figure is that the barrier layer 4 is interposed between the channel layer 3 and the gate electrode 11 in order to eliminate the limitation on the voltage applied to the gate electrode 11. Where you are.

In this field-effect transistor, the source electrode 12S and the drain electrode 12D, which are ohmic electrodes, are in contact with the n ⁺ region 8 formed by ion implantation and reaching the channel layer 3 from the surface. Alternatively, since the source electrode 12S and the drain electrode 12D enter deeply so as to approach the channel layer 3, the source electrode 12S and the drain electrode 12D and the gate electrode 11 are connected via the cap layer 7. become.

Since the cap layer 7 is usually made of i-GaAs, its resistance value is relatively high. However, this is also a problem. If the distance between the electrodes is small, the cap layer 7 is in a state in which impurities are not added. Even if it does, current will flow.

Therefore, when an attempt is made to increase the gate voltage to induce a large amount of carriers in the channel layer 3, the gate voltage is reduced.
Since the leakage current between the sources becomes large, the gate voltage that can be applied is limited, and a large output cannot be obtained.

Therefore, attempts have been made to increase the distance between the gate and the source. However, since the source resistance increases, proposals have been made to further improve this.

FIG. 5 is a fragmentary side view showing a field effect transistor for explaining a further improved conventional example.
The same symbols as those used in FIGS. 3 and 4 represent the same parts or have the same meanings.

In the field effect transistor shown in FIG. 5, a source electrode 12S and a drain electrode 12D are formed in a recess 7A penetrating the cap layer 7 and the like.
By making the structure that does not directly contact the periphery of the recess 7A,
The current flowing between the gate and source is reduced.

According to the structure of the field-effect transistor shown in FIG. 5, the problem of an increase in the distance between the gate and the source caused by the leakage current between the gate and the source is solved, and the two are brought close to each other to reduce the source resistance. It is now possible to do that.

By the way, in this field-effect transistor, it is necessary to accurately align the n ⁺ region 8 and the recess 7A in order to sufficiently exhibit the effect of the improvement. If there is a difference between the two, the leakage current between the gate and the source will increase, or the source resistance will increase.

[0016] As a method to match the n ⁺ region 8 and the recess 7A correctly, there are several means, for example, n ⁺
In the patterning in the recess step performed after the formation of the region 8, the patterning is repeatedly performed until the region exactly the same as the patterning in forming the n ⁺ region 8 can be patterned.

However, this method is unsuitable for producing goods because the number of steps is too large.

Further, for example, in one patterning, n
There is also a method of forming the ⁺ region 8 and the formation of the recess 7A. In this case, the state where the recess 7A is formed, that is,
Since heat treatment for activation is performed in a state where large irregularities are generated, defects increase due to stress, which causes deterioration in transistor characteristics and a reduction in manufacturing yield.

[0019]

An ohmic electrode such as a source electrode and a drain electrode is formed in a recess in a cap layer to prevent the ohmic electrode from being connected to a gate electrode via the cap layer. The semiconductor device including the semiconductor device can be manufactured by simple means and at a high yield.

[0020]

According to the present invention, the number of carrier traps is increased by introducing impurities into the side wall of a cap layer exposed in a recess for forming ohmic electrodes such as a source electrode and a drain electrode. Prevention is fundamental.

As described above, in the semiconductor device and the method of manufacturing the same according to the present invention, (1) a channel layer (for example, channel layer 3) through which carriers pass and a high-resistance cap formed on the channel layer Layer (for example, cap layer 7) and a source electrode (for example, source electrode 12) that is in a recess (for example, recess 7A) formed in the cap layer and injects carriers into the channel layer.
S) and a drain electrode (for example, a drain electrode 12D) for collecting carriers passing through the channel layer in a recess formed in the cap layer, and a gate electrode embedded in the cap layer between the source electrode and the drain electrode. (For example, the gate electrode 11) and an impurity introduction region (for example, the impurity introduction region 9) formed on at least a surface of the side surface of the cap layer facing the gate electrode exposed in the recess. Features, or

(2) In the above (1), a material interposed between the channel layer and the cap layer and having a larger energy band gap than the channel layer (for example, i-Al
_0.5 Ga _0.5 As), and a barrier layer (eg, barrier layer 4) having no carrier is provided immediately below the impurity introduction region formed on the side surface of the cap layer exposed in the recess. Or

(3) In the above (1) or (2),
Characterized in that the threshold voltage is -0.5 [V] or more, or

(4) In any one of the above (1) to (3), an impurity is introduced into the outermost surface of the cap layer, or

[0025] (5) (1) to (4) at any one of the material of the channel layer is GaAs or an In _y Ga
_1-y As (0 <y <0.3), and the material of the cap layer is GaAs, or

(6) In any one of the above (1) to (5), the material of the barrier layer is AlGaAs or InGa.
P, or

(7) In any one of the above (1) to (6), the carrier in the impurity introduction region formed on the side surface of the cap layer exposed in the recess is n-type. Features, or

(8) In any one of the above (1) to (7), the electron concentration in the impurity introduction region formed on the side surface of the cap layer exposed in the recess is 1 × 10 ¹⁷ [ cm
^-3 ] to 5 × 10 ¹⁷ [cm ^-3 ], or

(9) In any one of the above (1) to (8), the width of the impurity introduction region formed on the side surface of the cap layer exposed in the recess is 30 [nm] to 10 [nm].
Characterized by being in the range of 0 [nm], or

(10) At least a channel layer (eg, channel layer 3) is formed on a semiconductor substrate (eg, semiconductor substrate 1).
A step of laminating and forming a semiconductor layer including a cap layer (for example, a cap layer 7), and forming a recess (for example, a recess 7A) by removing at least the cap layer in a portion where a source region is to be formed and a portion where a drain region is to be formed. A step of forming an impurity-doped region (for example, an n ⁺ region 8) for making an ohmic contact on the semiconductor surface exposed at the bottom of the recess; Forming an impurity introduction region (for example, impurity introduction region 9) on the side surface of the cap layer exposed in the recess, or

(11) A step of laminating a semiconductor layer including at least a channel layer and a cap layer on a semiconductor substrate, and removing at least the cap layer in a portion where a source region is to be formed and a portion where a drain region is to be formed to form a recess. A step of forming, and a step of forming an impurity introduction region for making an ohmic contact on a semiconductor surface exposed at the bottom of the recess by introducing impurities using an etching mask at the time of forming the recess, A step of reducing the mask pattern used to form the recess and the impurity introduction region for making ohmic contact to expose the edge of the cap layer; and introducing an impurity into the exposed edge of the cap layer. Forming an impurity introduction region on the side surface of the cap layer exposed in the recess.

In the above (1), a configuration in which an impurity is introduced into the side wall of the cap layer exposed in the recess is described. This makes it possible to prevent an increase in carrier traps. Therefore, the leakage current between the gate and the source is reduced, and the parasitic resistance is also reduced.

In the above (2), a barrier layer is interposed between the channel layer and the gate electrode, and the carrier layer is provided in the stopper layer and the spacer layer immediately below the impurity introduction region formed on the side wall of the carrier layer. Is described, the gate forward breakdown voltage can be kept high.

In (3), the threshold voltage is set to -0.5.
[V] The configuration described above is described because the field effect transistor according to the present invention is characterized in that a high gate voltage can be applied, which increases the maximum drain current _Idmax. This is because it is effective when doing.

That is, in a field-effect transistor having a structure in which a source electrode and a drain electrode are formed in a recess penetrating a cap layer and the like and do not directly contact the periphery of the recess, it is particularly effective to use V _th ≧ −0.5
[V], for which data exists.

FIG. 2 is a diagram showing the relationship between the maximum drain current I _dmax and the threshold voltage V _th in the field-effect transistor. The vertical axis represents the maximum drain current I _dmax , and the horizontal axis represents the threshold voltage. V _th is taken, and the invention is indicated by a field effect having a structure in which a source electrode and a drain electrode are formed in a recess penetrating a cap layer or the like and do not directly contact the periphery of the recess. The characteristic line of the transistor, which is indicated as a conventional example, is a characteristic line of a field-effect transistor in which a source electrode and a drain electrode are formed on a cap layer, and V _th <−0.5.
In [V], the maximum drain current I _dmax is equal in any of the field-effect transistors, but V _th > −0.5 [V]
Now you can see the difference.

The above (4) describes a configuration in which an impurity is introduced into the outermost surface of the cap layer. This is effective for reducing the source resistance. That is, by adding impurities to the outermost surface of the cap layer, the sheet resistance between the n ⁺ region and the gate electrode can be reduced. For example, when doping is performed at a sheet concentration of 2 × 10 ¹² [cm ⁻² ]. , Sheet resistance from 2000 [Ω] / □ to 1200
[Ω] / □, corresponding to this, the source resistance is 1.
It is reduced from 5 [Ω / mm] to 1.1 [Ω / mm].

In the above (5) and (6), the configuration in which the constituent materials of the semiconductor device according to the present invention are limited is described. The reason is that at present, many compound semiconductor field effect transistors are easily available. A possible GaAs substrate is used, and a heterostructure required for a field-effect transistor is caused by a requirement that there should be no large lattice mismatch with the GaAs substrate. The channel layer is made of GaAs or InGaAs (In composition 0.3 or less)
Becomes The barrier layer needs to have a larger energy band gap than the channel layer, and becomes AlGaAs or InGaP due to the limitation of the lattice mismatch.
Further, a material having a high resistance is desirable. If the Al composition is high, the resistance tends to be high. The cap layer is made of GaAs because of its high resistance and the limitation of lattice mismatch.

The above (7) describes a configuration in which the carrier is limited to n-type. The reason is that electrons are usually more defective than holes in a group III-V compound semiconductor. The present invention is particularly effective for an n-type carrier because it is easily trapped in the carrier, but basically any carrier of the n-type and the p-type may be used.

The above (8) describes a configuration in which the amount of impurities introduced into the side wall of the cap layer is specified. In the present invention, in order to exhibit the effect of preventing an increase in traps, 1 × 10 An impurity of ¹⁷ [cm ⁻³ ] or more is required. However, if the amount of the impurity is too large, the impurity is diffused to the outside of the region to which the impurity is to be added, and the gate forward breakdown voltage is reduced. For these reasons, the upper limit is 5 × 10 ¹⁷ [cm ⁻³ ]
And

In the above (9), a configuration in which the width of the impurity introduction region formed on the side wall of the cap layer is specified is described. A width of [nm] is required. In order to reduce the source resistance, it is desirable to reduce the distance between the source and the gate. However, if the width of the impurity introduction region is too large, the impurity introduction region comes into contact with the gate electrode. Therefore, the width of the impurity-doped region has an upper limit of 100 [nm].

In the above (10), a method of introducing impurities into the side wall of the cap layer is described. After forming a recess in the cap layer, oblique ion implantation is performed.

The above (11) describes another method of introducing impurities into the side wall of the cap layer, and reduces the size of the resist film mask used for forming the recess and the n ⁺ region to form a new one. The ion implantation is performed as a simple mask.

By adopting the above means, a structure is provided in which a high resistance layer is interposed between the channel and the gate electrode, and the ohmic electrode is prevented from being connected to the gate electrode via the cap layer. In addition, a semiconductor device including a field effect transistor having a small number of carrier traps, a small gate leakage current, and a small parasitic resistance can be easily manufactured at a high yield.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cutaway side view showing a main part of a semiconductor device for explaining an embodiment of the present invention. The same symbols as those used in FIG. Or have the same meaning.

The semiconductor device shown in FIG. 1 is different from the conventional semiconductor device described with reference to FIG. 5 in that a recess 7A penetrating the cap layer 7 and the like is formed, and the exposed side wall of the cap layer 7 is formed. Since the impurity introduction region 9 is formed by implanting Si ions or the like, a process of manufacturing the semiconductor device will be described below.

(1) MOVPE (metalorga)
By applying a nic vapor phase epitaxy method, a buffer layer 2, a channel layer 3, a barrier layer 4, a spacer layer 5, a stopper layer 6,
The cap layer 7 is formed by lamination.

Here, the main data relating to each of the semiconductor portions will be exemplified as follows. For the substrate 1 material: the semi-insulating GaAs buffer layer 2 Material: undoped GaAs Thickness: 5000 [Å] For the channel layer 3 _{materials: n-In y Ga 1-} y As (y = 0.2) electron density: 7 0.5 × 10 ¹⁷ [cm ⁻³ ] Thickness: 150 [Å] About the barrier layer 4 Material: i-Al _x Ga _{1 -x} As (x = 0.5) Thickness: 30 [Å] About the spacer layer 5 Material: i-GaAs Thickness: 50 [Å] For stopper layer 6 Material: i-Al _x Ga _{1 -x} As (x = 0.5) Thickness: 30 [Å] For cap layer 7 Material: i-GaAs Thickness: 1500 [Å]

(2) A resist film having an opening in a portion where an ohmic region is to be formed is formed by applying a resist process in lithography technology.

(3) By applying the ion implantation method, using the resist film formed in the step (2) as a mask, the ion acceleration voltage is, for example, 180 [keV], and the dose is, for example, 4 × 10 ¹³ [cm]. ^-2 ] to form an n ⁺ region 8 by implanting Si ions.

(4) A dry etching method using SiCl ₄ as an etching gas and a wet etching method using ammonia as an etchant with the resist film used as an ion implantation mask left. Then, a recess 7A reaching the surface of the spacer layer 5 from the surface of the cap layer 7 is formed.

(5) With the resist film used as a mask when the recess 7A is formed, ion implantation is applied, the ion acceleration voltage is 40 keV, and the dose is 2 × 10 ¹² cm. ^-2 ] and implanting Si ions into the side wall exposed in the recess 7A while the substrate 1 is inclined at about 45 ° with respect to the ion source,
Is implanted at an angle of about 135 ° with respect to the ion source to form an impurity-doped region 9.

(6) After removing the resist film used as the ion implantation mask and the recess formation mask, the activation heat treatment of the ion-implanted Si is performed at a temperature of 850 ° C. and a time of 15 seconds. .

(7) CVD (chemical va
By applying a por deposition method, an insulating film 10 made of SiN having a thickness of, for example, 3000 [Å] is formed on the entire surface.

(8) By applying a resist process in the lithography technique and a dry etching method using SF ₆ as an etching gas, the portion of the insulating film 10 where a gate electrode is to be formed is etched. Row to form openings.

(9) Subsequently, the cap layer 7 is etched to extend the opening by applying a dry etching method using SiCl ₄ as an etching gas.

(10) Subsequently, the stopper layer 6 is etched to extend the opening by applying a wet etching method using ammonia as an etchant.

(11) A WSi film having a thickness of, for example, 1000 [１０００] is formed by applying a sputtering method, and then a thickness of, for example, 5000 [Å] is formed by applying a vacuum deposition method. Of the Au film is laminated.

(12) The gate electrode 11 is formed by performing ion milling of the WSi / Au film by applying a resist process in a lithography technique and an ion milling method using Ar ions. .
In this case, the gate length was 1 [μm].

(13) By applying the lithography technique, the portion where the ohmic electrode is to be formed in the insulating film 10 in the recess 7A is etched to form an ohmic electrode contact opening.

(14) The thickness is, for example, 300 [Å] / 4000 [Å] by applying a vacuum deposition method while leaving the resist film used as a mask when the opening for the ohmic electrode contact is formed. Of an AuGe / Au film is formed.

(15) By applying the lift-off method, the resist film on which the AuGe / Au film is adhered is removed, and the source electrode 12S and the drain electrode 12D which are ohmic electrodes are formed.

After the step (4), the n ⁺ region 8 is formed by applying a dry etching method using oxygen gas.
After the pattern of the resist film used as a mask when forming the recess 7A is reduced by, for example, about 50 [nm], the impurity introduction region 9 can be formed on the side wall of the recess 7A by implanting Si ions. .

When such a means is adopted, an operation such as tilting the substrate at a required angle with respect to the ion source becomes unnecessary when implanting Si ions, so that the ion implantation apparatus and the manufacturing process can be simplified. Can be.

In the above embodiments, the dimensions, the doping concentration, the doping conditions, the manufacturing process, and the like of each semiconductor portion have been specified and described. However, it is needless to say that the present invention is not limited to this.

[0066]

In the semiconductor device and the method of manufacturing the same according to the present invention, a channel layer through which carriers pass and a high-resistance cap layer are formed, and the channel layer is formed in a recess formed in the cap layer. A source electrode for injecting carriers and a drain electrode for collecting carriers passing through the channel layer in a recess formed in the cap layer are formed, and a gate electrode is embedded in the cap layer between the source and drain electrodes. Then, an impurity introduction region is formed on at least a surface of the side surface of the cap layer exposed in the recess facing the gate electrode direction.

By adopting the above configuration, a structure is provided in which a high resistance layer is interposed between the channel and the gate electrode, and the ohmic electrode is prevented from being connected to the gate electrode via the cap layer. In addition, a semiconductor device including a field effect transistor having a small number of carrier traps, a small gate leakage current, and a small parasitic resistance can be easily manufactured at a high yield.

[Brief description of the drawings]

FIG. 1 is a fragmentary side view showing a semiconductor device for describing an embodiment of the present invention;

FIG. 2 is a diagram illustrating a relationship between a maximum drain current I _dmax and a threshold voltage V _{th in a} field effect transistor.

FIG. 3 is a cutaway side view showing a main part of a field-effect transistor for explaining an improved conventional example.

FIG. 4 is a fragmentary side view showing a field-effect transistor for explaining an improved conventional example.

FIG. 5 is a fragmentary side view showing a field-effect transistor for explaining a further improved conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Channel layer 4 Barrier layer 5 Spacer layer 6 Stopper layer 7 Cap layer 7A Recess 8 n ⁺ region 9 Impurity introduction region 10 Insulating film 11 Gate electrode 12S Source electrode 12D Drain electrode

Claims (11)

[Claims] 1. A channel layer for passing carriers, a high-resistance cap layer formed on the channel layer, a source electrode in a recess formed in the cap layer, and a source electrode for injecting carriers into the channel layer and a cap layer. A drain electrode for collecting carriers passing through the channel layer in the formed recess; a gate electrode embedded in the cap layer between the source electrode and the drain electrode; and a cap layer exposed in the recess. A semiconductor device comprising: an impurity introduction region formed on at least a side of a side surface facing a gate electrode direction. 2. An impurity introducing region formed between a channel layer and a cap layer, made of a material having an energy band gap larger than that of the channel layer, and formed on a side surface of the cap layer exposed in the recess. 2. The semiconductor device according to claim 1, further comprising a barrier layer in which no carrier exists immediately below the semiconductor device. 3. The semiconductor device according to claim 1, wherein the threshold voltage is -0.5 [V] or more. 4. The method according to claim 1, wherein impurities are introduced into the outermost surface of the cap layer.
13. The semiconductor device according to claim 1. Material wherein the channel layer is GaAs or In _y
5. The semiconductor device according to claim 1, wherein Ga _1-y As (0 <y <0.3) and the material of the cap layer is GaAs. 6. The material of the barrier layer is AlGaAs or InGaAs.
6. The semiconductor device according to claim 1, wherein the semiconductor device is GaP. 7. The semiconductor device according to claim 1, wherein the carrier in the impurity introduction region formed on the side surface of the cap layer exposed in the recess is n-type. 8. An electron concentration in an impurity introduction region formed on a side surface of the cap layer exposed in the recess is 1 × 10 ^17.
8. The semiconductor device according to claim 1, wherein the value is in the range of [cm ^-3 ] to 5 × 10 ¹⁷ [cm ^-3 ]. 9. The semiconductor device according to claim 1, wherein the width of the impurity introduction region formed on the side surface of the cap layer exposed in the recess is in a range of 30 nm to 100 nm.
9. The semiconductor device according to claim 1. 10. A step of laminating a semiconductor layer including at least a channel layer and a cap layer on a semiconductor substrate, and forming a recess by removing at least the cap layer in a portion where a source region is to be formed and a portion where a drain region is to be formed. Forming an impurity-introduced region for making ohmic contact with the semiconductor surface exposed at the bottom of the recess; and ion-implanting the semiconductor substrate obliquely from the semiconductor substrate to expose the semiconductor substrate. Forming an impurity introduction region on the side surface of the cap layer. 11. A step of laminating a semiconductor layer including at least a channel layer and a cap layer on a semiconductor substrate, and forming a recess by removing at least the cap layer in a portion where a source region is to be formed and a portion where a drain region is to be formed. Forming an impurity-introduced region for making ohmic contact with the semiconductor surface exposed at the bottom of the recess by introducing an impurity by using an etching mask at the time of forming the recess; A step of reducing the pattern of the mask used for forming the impurity introduction region for forming the ohmic contact and exposing the edge of the cap layer, and introducing an impurity into the edge of the exposed cap layer. Forming an impurity introduction region on the side surface of the cap layer exposed in the recess. Device manufacturing method.