JPH11243152A

JPH11243152A - High voltage IC

Info

Publication number: JPH11243152A
Application number: JP10045261A
Authority: JP
Inventors: Tomoyuki Yamazaki; 智幸山崎
Original assignee: Fuji Electric Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 1998-02-26
Filing date: 1998-02-26
Publication date: 1999-09-07
Anticipated expiration: 2018-02-26
Also published as: JP3941206B2

Abstract

(57)【要約】【課題】ｎチャネルおよびｐチャネルレベルシフタの寄
生抵抗を大きくする。【解決手段】高耐圧ｎチャネルＭＯＳＦＥＴのｎドレイ
ン領域５とｎ領域３との間のｎ^-ウエル領域１を局部的
にｐ基板１００が露出する開口部２１を設け、高耐圧ｐ
チャンネルＭＯＳＦＥＴのｐ⁺ドレイン領域１８とｐウ
エル領域４の間のｐ^-オフセット領域２にｎ^-ウエル領
域が露出する開口部２２を設けて、高抵抗領域を形成す
る。 (57) Abstract: To increase the parasitic resistance of an n-channel and p-channel level shifter. An n ^- well region (1) between an n drain region (5) and an n region (3) of a high breakdown voltage n-channel MOSFET is provided with an opening (21) through which a p substrate (100) is locally exposed.
An opening 22 for exposing the n ^- well region is provided in the p ^- offset region 2 between the p ⁺ drain region 18 and the p well region 4 of the channel MOSFET to form a high resistance region.

Description

DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、パワーデバイス
の制御駆動用などに用いられる高耐圧ＩＣに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage IC used for controlling and driving a power device.

【０００２】[0002]

【従来の技術】パワーデバイスは、モータ制御用のイン
バータやコンバータなど多くの分野で広く利用されてい
る。このパワーデバイスの駆動および制御は、従来個別
の半導体素子や電子部品を組み合わせて構成した電子回
路によっていたが、近年ＬＳＩ（大規模集積回路）技術
を利用した１０００Ｖを超える高耐圧ＩＣが実用化され
ており、更に駆動・制御回路とパワーデバイスと同一半
導体基板上に集積したパワーＩＣが用いられている。2. Description of the Related Art Power devices are widely used in many fields such as inverters and converters for motor control. Conventionally, the driving and control of this power device has been performed by an electronic circuit configured by combining individual semiconductor elements and electronic components. However, in recent years, a high-voltage IC exceeding 1000 V using LSI (large-scale integrated circuit) technology has been put into practical use. In addition, a power IC integrated with a drive / control circuit and a power device on the same semiconductor substrate is used.

【０００３】図１０はモータ制御用インバータのパワー
部を中心に説明する回路構成図である。三相モータ７０
を駆動するために用いるパワーデバイスはブリッジ回路
を構成し、同一パッケージに収納されたパワーモジュー
ル７１の構造をしている。この図ではパワーモジュール
７２はパワーデバイスである絶縁ゲート型バイポーラト
ランジスタ（以下、ＩＧＢＴと称す）とダイオードによ
って構成されている。同図ではＩＧＢＴはＱ１〜Ｑ６、
ダイオードはＤ１〜Ｄ６で示されている。主電源ＶCC
2 の高電位側ＶCC2HはＱ１、Ｑ２、Ｑ３のコレクタに接
続し、低電位側ＶCC2LはＱ４、Ｑ５、Ｑ６のエミッタに
接続し、各ＩＧＢＴのゲートは主回路駆動回路７２の出
力に接続し、主回路駆動回路７２の入力端子Ｉ／Ｏは通
常のマイクロコンピュータに接続し、パワーモジュール
７１で構成されるインバータの出力Ｕ、Ｖ、Ｗは三相モ
ータ７０に接続している。FIG. 10 is a circuit diagram mainly illustrating a power section of a motor control inverter. Three-phase motor 70
The power device used to drive the power supply constitutes a bridge circuit, and has a structure of a power module 71 housed in the same package. In this figure, the power module 72 includes an insulated gate bipolar transistor (hereinafter, referred to as IGBT) as a power device and a diode. In the figure, IGBTs are Q1-Q6,
Diodes are designated D1-D6. Main power supply VCC
2, the high potential side VCC2H is connected to the collectors of Q1, Q2, Q3, the low potential side VCC2L is connected to the emitters of Q4, Q5, Q6, the gate of each IGBT is connected to the output of the main circuit drive circuit 72, The input terminal I / O of the main circuit drive circuit 72 is connected to a normal microcomputer, and the outputs U, V, W of the inverter constituted by the power module 71 are connected to the three-phase motor 70.

【０００４】主電源ＶCC2 は通常１００〜４００Ｖと高
電圧である。特にＱ４，Ｑ５，Ｑ６がそれぞれオフ状態
の時は、Ｑ１，Ｑ２，Ｑ３のソース電位がそれぞれ高電
圧になるため、これらのゲートを駆動する場合にソース
電位より更に高い電圧で駆動しなければならないため、
主回路駆動回路７２にはフォトカプラー（ＰＣ：Ｐｈｏ
ｔｏＣｏｕｐｌｅｒ）や高耐圧ＩＣ（以下、ＨＶＩＣ
と称す。ＨＶＩＣ：ＨｉｇｈＶｏｌｔａｇｅＩｎｔ
ｅｇｒａｔｅｄＣｉｒｃｕｉｔ）が用いられる。また
主回路駆動回路７２の入出力端子Ｉ／Ｏ（Ｉｎｐｕｔ／
Ｏｕｔｐｕｔ）は通常マイクロコンピュータへ接続さ
れ、そのマイクロコンピュータによりパワーモジュール
７１で構成されるインバータ回路全体の制御がなされ
る。つぎにこの中のＨＶＩＣについて一例を示す。[0004] The main power supply VCC2 is normally a high voltage of 100 to 400V. In particular, when Q4, Q5, and Q6 are each in the off state, the source potentials of Q1, Q2, and Q3 become high voltages, respectively. Therefore, when these gates are driven, they must be driven with a voltage higher than the source potential. For,
The main circuit drive circuit 72 includes a photocoupler (PC: Pho
to Coupler) and high voltage IC (hereinafter HVIC)
Called. HVIC: High Voltage Int
(Egrated Circuit) is used. Also, the input / output terminal I / O (Input /
Output) is usually connected to a microcomputer, and the microcomputer controls the entire inverter circuit including the power module 71. Next, an example of the HVIC will be described.

【０００５】図１１はＨＶＩＣの素子構成図である。主
回路駆動回路７２を形成しているＨＶＩＣは入出力端子
Ｉ／Ｏを通してマイクロコンピュータと信号のやり取り
を行い、どのＩＧＢＴをオンさせオフさせるかの制御信
号を発生させる制御回路（以下、ＣＵと称す。ＣＵ：Ｃ
ｏｎｔｒｏｌＵｎｉｔ）と、このＣＵからの信号を、
受けてＩＧＢＴのゲートを駆動し、またＩＧＢＴの過電
流、加熱を検出し、異常信号をＣＵに伝えるゲート駆動
回路（以下、ＧＤＵと称す。ＧＤＵ：ＧａｔｅＣｏｎｔ
ｒｏｌＵｎｉｔ）と、図１０のブリッジを構成するＩ
ＧＢＴの内、高電位側に接続するＱ１，Ｑ２，Ｑ３のゲ
ート信号およびアラーム信号について、ＶＣＣ２Ｌレベ
ルとＶＣＣ２Ｈとを媒介する働きをするレベルシフト回
路（以下、ＬＳＵと称す。ＬＳＵ：ＬｅｖｅｌＳｈｉ
ｆｔＵｎｉｔ）とからなる。このＧＤＵはＱ１、Ｑ
２、Ｑ３と接続するＧＤＵ−Ｕ、ＧＤＵ−Ｖ、ＧＤＵ−
ＷとＱ４、Ｑ５、Ｑ６と接続するＧＤＵ−Ｘ、ＧＤＵ−
Ｙ、ＧＤＵ−Ｚで構成される。つぎにこの中のＬＳＵに
ついて一例を示す。FIG. 11 is a diagram showing the element configuration of the HVIC. The HVIC forming the main circuit drive circuit 72 exchanges signals with a microcomputer through an input / output terminal I / O, and generates a control signal (hereinafter, referred to as a CU) for controlling which IGBT is turned on and off. CU: C
control Unit) and the signal from this CU
The gate drive circuit (hereinafter, referred to as GDU; GDU: GateCont) that drives the gate of the IGBT, detects overcurrent and heating of the IGBT, and transmits an abnormal signal to the CU.
role Unit) and I which constitute the bridge of FIG.
Among the GBTs, the gate signal and the alarm signal of Q1, Q2, and Q3 connected to the high potential side and the level shift circuit (hereinafter, referred to as LSU; LSU: Level Shi) that mediates the VCC2L level and the VCC2H for the VCC2L level and the VCC2H.
ft Unit). This GDU is Q1, Q
2. GDU-U, GDU-V, GDU- connected to Q3
GDU-X, GDU- connected to W and Q4, Q5, Q6
Y, GDU-Z. Next, an example of the LSU will be described.

【０００６】図１２はＬＳＵの基本構成図である。基本
構成としては高耐圧ｎチャネルＭＯＳＦＥＴ６１と抵抗
ＲL1および高耐圧ｐチャネルＭＯＳＦＥＴ６２と抵抗Ｒ
L2が用いられる。高耐圧ｎチャネルＭＯＳＦＥＴ６１は
ＣＵからの信号を高電位側ＶＣＣ２ＨにあるＧＤＵ−
Ｕ，Ｖ，Ｗへレベルシフトするためのもの、また高耐圧
ｐチャネルＭＯＳＦＥＴ６２は過電流や加熱の異常信号
を低電位側ＶＣＣ２ＬにあるＣＵへレベルシフトするた
めのものであり、特にＱ１，Ｑ２，Ｑ３の過電流検知や
加熱検知等の異常信号を出さない場合は、この高耐圧ｐ
チャネルＭＯＳＦＥＴ６２は不要となる。このＬＳＵに
用いられる高耐圧ｎチャネルＭＯＳＦＥＴ６１および高
耐圧ｐチャネルＭＯＳＦＥＴ６２は三相モータ７０を駆
動するＩＧＢＴ（Ｑ１〜Ｑ６）と同等の６００Ｖから１
２００Ｖの耐圧値が要求される。FIG. 12 is a basic configuration diagram of the LSU. The basic configuration is as follows: a high breakdown voltage n-channel MOSFET 61 and a resistor RL1, and a high breakdown voltage p-channel MOSFET 62 and a resistor R
L2 is used. The high-breakdown-voltage n-channel MOSFET 61 converts a signal from the CU into a GDU-
The U-, V-, and W-level shifters, and the high-breakdown-voltage p-channel MOSFET 62 is for shifting the level of an overcurrent or abnormal heating signal to the CU on the lower potential side VCC2L. If no abnormal signal such as overcurrent detection or heating detection of Q3 is issued,
The channel MOSFET 62 becomes unnecessary. The high-breakdown-voltage n-channel MOSFET 61 and the high-breakdown-voltage p-channel MOSFET 62 used for this LSU are from 600 V to 1 which are equivalent to IGBTs (Q1 to Q6) for driving the three-phase motor 70.
A withstand voltage of 200 V is required.

【０００７】つぎに、高耐圧部の回路を低耐圧部の回路
から電気的に分離する具体的な高耐圧分離方法について
説明する。これまで誘電体分離、接合分離および自己分
離が報告されているが、誘電体分離や接合分離は分離構
造が複雑で製造コストが高く、耐圧が高くなるほど製造
コストが高くなる。これに対して、自己分離は製造コス
トが低く抑えられるという長所を有する。Next, a specific high withstand voltage separating method for electrically separating the circuit of the high withstand voltage section from the circuit of the low withstand voltage section will be described. Although dielectric isolation, junction isolation, and self-isolation have been reported so far, dielectric isolation and junction isolation have a complicated isolation structure and a high manufacturing cost, and the higher the breakdown voltage, the higher the manufacturing cost. In contrast, self-separation has the advantage that manufacturing costs can be kept low.

【０００８】図１３は自己分離により形成した従来の高
耐圧ｎチャネルレベルシフタと高耐圧ｐチャネルレベル
シフタを有する高耐圧ＩＣの要部平面図である。同図に
おいて、１００はｐ^-基板、１はｎ^-ウエル領域、２は
ｐ^-オフセット領域、３はｎ領域、４はｐウエル領域、
５はｎドレイン領域、６ａ、６ｂはｐ領域、１０はｎ ⁺
ソース領域、１３と１４はｎ⁺領域、１５ａ、１５ｂは
ｐ⁺領域、１７はｐ⁺ソース領域、１８はｐ⁺ドレイン
領域、３１、３２はゲート電極を示す。FIG. 13 shows a conventional high-profile formed by self-separation.
Withstand voltage n-channel level shifter and high withstand voltage p-channel level
FIG. 3 is a plan view of a main part of a high withstand voltage IC having a shifter. In the figure
Then, 100 is p^-Substrate, 1 is n^-Well area, 2
p^-Offset region, 3 is an n region, 4 is a p-well region,
5 is an n drain region, 6a and 6b are p regions, 10 is n ⁺
Source regions, 13 and 14 are n⁺The areas 15a and 15b are
p⁺Region, 17 is p⁺Source region, 18 is p⁺drain
Regions 31 and 32 indicate gate electrodes.

【０００９】高耐圧ｎチャネルレベルシフタはｎドレイ
ン領域５と、ｎドレイン領域５と図示されていないドレ
イン電極とのオーミック接触をとるためのｎ⁺領域１３
と、ゲート電極３１と、ｎ⁺ソース領域１０と、ゲート
駆動回路Ｕ−ＧＤＵ（この他にＶ−ＧＤＵ、Ｗ−ＧＤ
Ｕ、Ｘ−ＧＤＵ、Ｙ−ＧＤＵ、Ｚ−ＧＤＵがある）の電
源の高電位側と接続する高電位電極と接続するｎ領域３
で構成される。The high-breakdown-voltage n-channel level shifter has an n drain region 5 and an n ⁺ region 13 for making ohmic contact between the n drain region 5 and a drain electrode (not shown).
, A gate electrode 31, an n ⁺ source region 10, and a gate drive circuit U-GDU (other than V-GDU, W-GDU).
U, X-GDU, Y-GDU, Z-GDU) n region 3 connected to a high potential electrode connected to the high potential side of the power supply
It consists of.

【００１０】一方、高耐圧ｐチャネルレベルシフタはｐ
⁺ドレイン領域１８と、ゲート電極３２と、ｐ⁺ソース
領域１７と、図示されていないＣＯＭ電極４１と接続す
るｐウエル領域４で構成される。高耐圧ｎチャネルレベ
ルシフタは、ｎドレイン領域５とｎ領域３との間隔を広
して、図１４の寄生抵抗Ｒ１を大きくしている。また高
耐圧ｐチャネルレベルシフタは、ｐ⁺ドレイン領域１８
とｐウエル領域４との間隔を広くして、図１５の寄生抵
抗Ｒ２を大きくしている。また、通常、ｎドレイン領域
５およびｐ⁺ドレイン領域１８が、ゲート電極３１およ
びゲート電極３２で取り囲まれるようにレイアウトす
る。On the other hand, a high breakdown voltage p-channel level shifter
^{It comprises a +} drain region 18, a gate electrode 32, a p ⁺ source region 17, and a p-well region 4 connected to a COM electrode 41 (not shown). The high-breakdown-voltage n-channel level shifter increases the distance between the n-drain region 5 and the n-region 3 to increase the parasitic resistance R1 in FIG. Also, the high breakdown voltage p-channel level shifter is a p ⁺ drain region 18.
The parasitic resistance R2 in FIG. 15 is increased by increasing the distance between the P-well region 4 and the p-well region 4. Normally, the layout is made so that n drain region 5 and p ⁺ drain region 18 are surrounded by gate electrode 31 and gate electrode 32.

【００１１】図１４は図１３のＣ−Ｃ’線で切断した要
部断面図である。同図はｎチャネルレベルシフタの要部
断面図である。同図において、４１はＣＯＭ（ＣＯＭ電
極）、４２ａはドレイン電極、４３はＧＤＵ電源の高電
位電極、４４はＧＤＵ電源の低電位電極、ＲL1はレベル
シフト用抵抗、Ｒ１は寄生抵抗、ＨＶＪＴは高耐圧構造
部を示す。前記のＣＯＭは図１０のＶCC2Lと接続する。
ＶCCはＧＤＵ−Ｕの電源である。Ｕ−ＯＵＴはＶCCの低
電位側に接続する端子で図１０のＵ−ＯＵＴと接続し、
三相モータＭと接続する。ＯＵＴはドレイン電極４２ａ
と接続するドレイン端子でＧＤＵ−Ｕと接続する。Ｕ−
ＶCCはＶCCの高電位側に接続する端子である。その他の
符号は図１３と同一である。FIG. 14 is a sectional view of an essential part taken along line CC 'of FIG. FIG. 3 is a cross-sectional view of a main part of the n-channel level shifter. In the figure, 41 is a COM (COM electrode), 42a is a drain electrode, 43 is a high potential electrode of a GDU power source, 44 is a low potential electrode of a GDU power source, RL1 is a level shift resistor, R1 is a parasitic resistor, and HVJT is high. 3 shows a pressure-resistant structure. The above COM is connected to VCC2L in FIG.
VCC is the power supply of GDU-U. U-OUT is a terminal connected to the low potential side of VCC, connected to U-OUT in FIG.
Connect to three-phase motor M. OUT is the drain electrode 42a
Is connected to GDU-U by a drain terminal connected to GDU-U. U-
VCC is a terminal connected to the high potential side of VCC. Other reference numerals are the same as those in FIG.

【００１２】つぎに、さらに詳しく説明する。各構成素
子はｎ^-ウエル領域１表面上に形成され、高耐圧ｎチャ
ネルＭＯＳＦＥＴはゲート電極３１、ｐウエル領域４に
形成されたｎ⁺ソース領域１０、ｐ^-オフセット領域２
を用いたダブルＲＥＳＵＲＦ（ＲＥｄｕｃｅｄ−ＳＵＲ
ｆａｃｅ−Ｆｉｅｌｄ：表面耐圧構造の一種）による高
耐圧分離部（以下ＨＶＪＴ称す。ＨＶＪＴ：Ｈｉｇｈ
ＶｏｌｔａｇｅＪｕｎｃｔｉｏｎＴｅｒｍｉｎａ
ｌ）およびｎ⁺ドレイン領域５により構成される。ま
た、ｎ^-ウエル領域１と、ｎ^-ウエル領域１内に構成さ
れる低耐圧のｎチャネルＭＯＳＦＥＴと低耐圧のｐチャ
ネルＭＯＳＦＥＴからなる相補形ＭＯＳＦＥＴ回路（以
下、ＣＭＯＳ回路と称す）のＬｏｗレベル（以下、Ｌレ
ベルと称す）に相当する電位にあるｐウエル領域４は、
ＨＶＩＣを駆動するための電源ＶCCを介して接続され、
このｎ^-ウエル領域１とｐウエル領域４のｐｎ接合は常
に逆バイアスされている。抵抗ＲL1はこの電源ＶCCと接
続するｎ⁺領域１４と高耐圧ｎチャネルＭＯＳＦＥＴの
ｎドレイン領域５間に設けられ、抵抗ＲL1を通る電流に
よって所定の電圧を発生させ、ＶCC2Lレベルのオン・オ
フ信号を高電位のＵ−ＶCCレベルのオン・オフ信号へと
出力する。Next, a more detailed description will be given. Each constituent element is formed on the surface of the n ^- well region 1, and the high breakdown voltage n-channel MOSFET is a gate electrode 31, an n ⁺ source region 10 formed in the p well region 4, a p ^- offset region 2
RESURF (REduced-SUR)
face-Field: a high withstand voltage separation portion (hereinafter referred to as HVJT) by a surface withstand voltage structure (HVJT: High)
Voltage Junction Termina
1) and the n ⁺ drain region 5. Further, a Low level (hereinafter referred to as a CMOS circuit) of a complementary MOSFET circuit (hereinafter referred to as a CMOS circuit) including the n ^- well region 1 and the low-breakdown-voltage n-channel MOSFET and the low-breakdown-voltage p-channel MOSFET formed in the n ^- well region 1. The p-well region 4 at a potential corresponding to the L level)
Connected via a power supply VCC for driving the HVIC,
The pn junction between the n ^- well region 1 and the p well region 4 is always reverse biased. The resistor RL1 is provided between the n ⁺ region 14 connected to the power supply VCC and the n-drain region 5 of the high-breakdown-voltage n-channel MOSFET, generates a predetermined voltage by the current passing through the resistor RL1, and outputs a VCC2L level on / off signal. It outputs a high potential U-VCC level on / off signal.

【００１３】図１５は図１３のＤ−Ｄ’線で切断した要
部断面図である。同図は高耐圧ｐチャネルレベルシフタ
の要部断面図である。符号は図１４と同一である。また
４２ｂはドレイン電極、ＲL2はレベルシフト用抵抗、Ｒ
２は寄生抵抗、ＯＵＴはドレイン電極４２ｂと接続する
ドレイン端子でＣＵと接続する。つぎに、詳しく説明す
る。前記と同様に各構成素子はｎ^-ウエル領域１の表面
上に形成され、高耐圧ｐチャネルＭＯＳＦＥＴはゲート
電極３２、ｐ⁺ソース領域１７、ドリフト領域を兼ねる
ｐ^-オフセット領域２によるＨＶＪＴおよびｐ⁺ドレイ
ン領域１８により構成される。ｎ領域３とＣＭＯＳのＬ
レベルに相当する電位にあるｐウエル領域４はＨＶＩＣ
を駆動するための電源ＶCCを介して接続され、このｎ^-
ウエル領域１とｐウエル領域４のｐｎ接合は常に逆バイ
アスされている。抵抗ＲL2はＶＣＣ２Ｌと接続されるｐ
ウエル領域４と高耐圧ｐチャネルＭＯＳＦＥＴのｐ⁺ド
レイン領域１８間に設けられ、抵抗ＲL2を通る電流によ
って所定の電圧を発生させ、ＶCC2Hレベルの異常信号を
ＶCC2Lレベルの信号へと出力する。素子のレイアウトは
図１５に示すように高耐圧ｎチャネルＭＯＳＦＥＴと同
様にｐ⁺ドレイン領域１６をゲート電極３２が取り囲む
ような形となる。FIG. 15 is a sectional view of an essential part taken along line DD 'of FIG. FIG. 3 is a cross-sectional view of a main part of a high breakdown voltage p-channel level shifter. The reference numerals are the same as those in FIG. 42b is a drain electrode, RL2 is a level shift resistor, and R
2 is a parasitic resistance, and OUT is a drain terminal connected to the drain electrode 42b and connected to CU. Next, a detailed description will be given. Similarly to the above, each component is formed on the surface of the n ^- well region 1, and the high withstand voltage p-channel MOSFET is composed of the HVJT and p ⁺ by the gate electrode 32, the p ⁺ source region 17, and the p ^- offset region 2 also serving as a drift region. It is constituted by a drain region 18. n region 3 and CMOS L
The p-well region 4 at a potential corresponding to the level is HVIC
It is connected via a power supply VCC for driving, the n ^-
The pn junction between the well region 1 and the p well region 4 is always reverse biased. The resistance RL2 is connected to VCC2L by p
A predetermined voltage is generated between the well region 4 and the p ⁺ drain region 18 of the high-breakdown-voltage p-channel MOSFET by the current passing through the resistor RL2, and a VCC2H level abnormal signal is output as a VCC2L level signal. As shown in FIG. 15, the layout of the element is such that the gate electrode 32 surrounds the p ⁺ drain region 16 similarly to the high breakdown voltage n-channel MOSFET.

【００１４】[0014]

【発明が解決しようとする課題】この高耐圧ｎチャネル
ＭＯＳＦＥＴおよび高耐圧ｐチャネルＭＯＳＦＥＴを用
いたレベルシフタ（以下、ｎチャネルレベルシフタ、ｐ
チャネルレベルシフタと称す）において、入力信号をレ
ベルシフトするためには抵抗（ＲL1、ＲL2）にこの高耐
圧ｎチャネルおよびｐチャネルＭＯＳＦＥＴからの電流
が十分に流れて、抵抗（ＲL1，ＲL2）の両端にＧＤＵお
よびＣＵのＣＭＯＳを駆動させることができる電圧を発
生させる必要がある。しかし、これらの構造を自己分離
により形成すると、高耐圧ｎチャネルＭＯＳＦＥＴが形
成される場合においては、ｎ^-ウエル領域、あるいはｐ
チャネルＭＯＳＦＥＴが形成される場合においては、ｐ
^-オフセット領域に図１３、図１４に示すように寄生抵
抗Ｒ１、Ｒ２が作り込まれてしまう。具体的に説明する
と、図１３の高耐圧ｎチャネルＭＯＳＦＥＴの場合にお
いて、チャネルを通った電子はｎドレイン領域５の他に
電源ＶＣＣの高電位側ＶＣＣ２Ｈがｎ⁺領域１４を介し
て接続するｎ領域３にも入り得る。また高耐圧ｐチャネ
ルＭＯＳＦＥＴの場合においては、正孔はｐ⁺ドレイン
領域１８の他に電源ＶＣＣの低電位側ＶＣＣ２Ｌに接続
するｐウエル領域４にも入り得る。このため、抵抗（Ｒ
L1_,ＲL2）の抵抗値に比べて寄生抵抗Ｒ１、Ｒ２の抵抗
値が小さい場合には、電流は寄生抵抗Ｒ１、Ｒ２を通し
て殆ど流れ、抵抗（ＲL1_,ＲL2）を通して流れない。そ
うすると、抵抗（ＲL1_,ＲL2）で発生する電圧がＧＤＵ
内に形成されたＣＭＯＳを駆動する電圧（スレッシュホ
ールド電圧）に達せず、レベルシフタとして機能をしな
くなる。SUMMARY OF THE INVENTION A level shifter using the high-breakdown-voltage n-channel MOSFET and the high-breakdown-voltage p-channel MOSFET (hereinafter referred to as an n-channel level shifter,
In order to shift the level of the input signal in the channel level shifter), the current from the high-breakdown-voltage n-channel and p-channel MOSFETs sufficiently flows through the resistors (RL1, RL2), so that both ends of the resistors (RL1, RL2) It is necessary to generate a voltage capable of driving the CMOS of the GDU and the CU. However, when these structures are formed by self-isolation, when a high breakdown voltage n-channel MOSFET is formed, the n ^- well region or the p-type
When a channel MOSFET is formed, p
^- Figure 13, the parasitic resistance R1, R2 will be built as shown in FIG. 14 in the offset region. More specifically, in the case of the high-breakdown-voltage n-channel MOSFET shown in FIG. 13, electrons passing through the channel are, in addition to the n-drain region 5, the n-region where the high-potential side VCC2H of the power supply VCC is connected via the n ⁺ region 14. It can enter 3. In the case of a high-breakdown-voltage p-channel MOSFET, holes can enter not only p ⁺ drain region 18 but also p well region 4 connected to low potential side VCC2L of power supply VCC. Therefore, the resistance (R
When the resistance values of the parasitic resistances R1 and R2 are smaller than the resistance values of the resistances (L1 _and RL2), the current almost flows through the parasitic resistances R1 and R2 and does not flow through the resistances (RL1 _and RL2). Then, the voltage generated by the resistors (RL1 _, RL2) becomes GDU.
It does not reach the voltage (threshold voltage) for driving the CMOS formed therein, and does not function as a level shifter.

【００１５】これを回避する方法として、寄生抵抗を大
きくすることが有効である。つまり、高耐圧ｎチャネル
ＭＯＳＦＥＴに関してはｎドレイン領域５とｎ領域３と
の距離を大きくとり、また高耐圧ｐチャンネルＭＯＳＦ
ＥＴに関してはｐ⁺ドレイン領域１８とＶＣＣ２Ｌレベ
ルにあるｐウエル領域４との距離を大きくとることで寄
生抵抗を大きくする方法である。しかし、この方法だと
レベルシフタの面積が大きくなりチップコストが高くな
るという欠点である。一方、小さな寄生抵抗に大きな電
流を流して、寄生抵抗に発生する電圧を大きくして、こ
の寄生抵抗と並列接続している抵抗（ＲL1_,ＲL2）に発
生する電圧を大きくして、ＧＤＵを構成するＣＭＯＳを
動作させ、オン・オフ信号をレベルシフトさせることは
可能である。しかし、この場合は、消費電力が大きくな
るという欠点がある。As a method for avoiding this, it is effective to increase the parasitic resistance. That is, for the high-breakdown-voltage n-channel MOSFET, the distance between the n-drain region 5 and the n-region 3 is increased, and the high-breakdown-voltage p-channel MOSFET is increased.
Regarding ET, this is a method of increasing the parasitic resistance by increasing the distance between the p ⁺ drain region 18 and the p well region 4 at the VCC2L level. However, this method is disadvantageous in that the area of the level shifter increases and the chip cost increases. On the other hand, a large current flows through a small parasitic resistance to increase the voltage generated in the parasitic resistance, and the voltage generated in the resistors (RL1 _and RL2) connected in parallel with the parasitic resistance to increase the GDU. In this case, it is possible to operate the CMOS and shift the level of the on / off signal. However, in this case, there is a disadvantage that power consumption increases.

【００１６】この発明の目的は、前記課題を解決するた
めに、ｎチャネルおよびｐチャネルレベルシフタの寄生
抵抗を大きくすることで、チップサイズの小型化を図
り、低コストで且つ、低消費電力のＨＶＩＣを提供する
ことである。An object of the present invention is to solve the above problems by increasing the parasitic resistance of the n-channel and p-channel level shifters, thereby reducing the chip size, reducing the cost, and reducing the power consumption of the HVIC. It is to provide.

【００１７】[0017]

【課題を解決するための手段】前記の目的を達成するた
めに、第一導電形の第一領域（１００）と、第一領域
（１００）の第一主面の表面層に選択的に形成された第
二導電形の第二領域（１）と、第二領域（１）の表面層
に選択的に形成された第一導電形の第三領域（４）と、
第三領域（４）の表面層に選択的に形成された第二導電
形の第一ソース領域（１０）と、第三領域（４）と離れ
て第二領域の表面層に選択的に形成された第二ドレイン
領域と、第三領域（４）と第一ドレイン領域（５）の間
を両者に接するように形成された第一導電形の第五領域
（２）と、第一ソース領域（１０）および第二領域
（１）に挟まれた第三領域（４）の表面上に絶縁膜を介
して形成された第一ゲート電極（３１）と、第二領域
（１）の表面層に選択的に形成され、第二領域（１）の
表面層に選択的に形成され、第二領域（１）内に構成さ
れる他回路の高電位側に接続される第二導電形の第六領
域（３）と、第一ドレイン領域（５）上に形成された第
一電極（４２）と第六領域（３）上に形成された第二電
極（４３）との間に設けられた第一レベルシフト用抵抗
（ＲL1）とを備える高耐圧ＩＣにおいて、第一ドレイン
領域（５）と第六領域（３）間の第二領域（１）に、第
一ドレイン領域（５）を挟んで第一ソース領域（１０）
と対向する箇所に選択的に第一高抵抗領域（５１）を形
成する構成とする。In order to achieve the above object, a first region of a first conductivity type and a surface layer of a first main surface of the first region are selectively formed. A second region (1) of the second conductivity type and a third region (4) of the first conductivity type selectively formed on the surface layer of the second region (1);
A first source region of the second conductivity type selectively formed on the surface layer of the third region; and selectively formed on the surface layer of the second region apart from the third region. A second drain region, a fifth region (2) of the first conductivity type formed so as to contact between the third region (4) and the first drain region (5), and a first source region. (10) a first gate electrode (31) formed on the surface of a third region (4) sandwiched between the second region (1) via an insulating film, and a surface layer of the second region (1) And the second conductivity type selectively formed on the surface layer of the second region (1) and connected to the high potential side of another circuit formed in the second region (1). Six regions (3), provided between a first electrode (42) formed on the first drain region (5) and a second electrode (43) formed on the sixth region (3). In the high-voltage IC having the first level shift resistor (RL1), the first drain region (5) is provided in the second region (1) between the first drain region (5) and the sixth region (3). The first source region (10) across
The first high-resistance region (51) is selectively formed at a position opposed to.

【００１８】第一導電形の第一領域（１００）と、第一
領域（１００）の第一主面の表面層に選択的に形成され
た第二導電形の第二領域（１）と、第二領域（１）の表
面層に第一領域（１００）に重なりを持つように選択的
に形成された第一導電形の第五領域（２）と、第五領域
（２）とは別に第二領域（１）の表面層に選択的に形成
され、第二領域（１）内に構成される他回路の高電位側
に接続される第二導電形の第六領域（３）と、第二領域
（１）の表面層に選択的に形成された第一導電形の第二
ソース領域（１７）と、第五領域（２）と第二ソース領
域（１７）に挟まれた第二領域（１）の表面上に絶縁膜
を介して形成された第二ゲート電極（３２）と、第五領
域（２）に選択的に形成された第一導電形の第二ドレイ
ン領域（１８）と、第五領域（２）内で、第二領域
（１）の外側に形成された第一領域（１００）とオーミ
ックコンタクトをとるための第一導電形の第八領域（１
６）と、第八領域（１６）上に形成された第三電極（４
１）と第二ドレイン領域（１８）上に形成された第一電
極（４２）との間に設けられた第二レベルシフト用抵抗
（ＲL2）を備える高耐圧ＩＣにおいて、第二ドレイン領
域（１８）と第十領域（１６）の間の第五領域（２）
に、第二ドレイン領域（１８）を挟んで、第二ソース領
域（１７）と対向する箇所に選択的に第二高抵抗領域
（５２）を形成する構成とする。A first region (100) of the first conductivity type and a second region (1) of the second conductivity type selectively formed on the surface layer of the first main surface of the first region (100); A fifth region (2) of the first conductivity type selectively formed on the surface layer of the second region (1) so as to overlap the first region (100), and a fifth region (2) are separately provided. A sixth region (3) of the second conductivity type selectively formed on the surface layer of the second region (1) and connected to the high potential side of another circuit configured in the second region (1); A second source region (17) of the first conductivity type selectively formed on the surface layer of the second region (1), and a second source region (17) sandwiched between the fifth region (2) and the second source region (17). A second gate electrode (32) formed on the surface of the region (1) via an insulating film; and a second drain region (18) of the first conductivity type selectively formed in the fifth region (2). When In the fifth region (2), the second region (1) a first conductivity type of the eighth region (1 for ohmic contact with the first region (100) formed on the outside of
6) and a third electrode (4) formed on the eighth region (16).
1) In a high breakdown voltage IC including a second level shift resistor (RL2) provided between the first electrode (42) formed on the second drain region (18) and the second drain region (18). ) And the fifth area (2) between the tenth area (16)
Then, a second high-resistance region (52) is selectively formed at a position facing the second source region (17) with the second drain region (18) interposed therebetween.

【００１９】第一導電形の第一領域（１００）と、第一
領域（１００）の第一主面の表面層に選択的に形成され
た第二導電形の第二領域（１）と、第二領域（１）の表
面層に選択的に形成された第一導電形の第三領域（４）
と、第三領域（４）の表面層に選択的に形成された第二
導電形の第一ソース領域（１０）と、第三領域（４）と
第一ドレイン領域（５）の間を両者に接するように形成
された第一導電形の第五領域（２）と、第一ソース領域
（１０）および第二領域（１）に挟まれた第三領域
（４）の表面上に絶縁膜を介して形成された第一ゲート
電極（３１）と、第二領域（１）の表面層に選択的に形
成され、第二領域（１）の表面層に選択的に形成され、
第二領域（１）内に構成される他回路の高電位側に接続
される第二導電形の第六領域（３）と、第二領域（１）
の表面層に選択的に形成され、前記の他回路の低電位側
に接続される第一導電形の第七領域（６）と、第一ドレ
イン領域（５）上に形成された第一電極（４２）と第六
領域（３）上に形成された第二電極（４３）との間に設
けられた第一レベルシフト用抵抗（ＲL1）とを備える高
耐圧ＩＣにおいて、第一ドレイン領域（５）と第六領域
（３）間の第二領域（１）の一部であって、第一ドレイ
ン領域（５）を挟んで第一ソース領域（１０）と対向す
る箇所に選択的に第一高抵抗領域（５１）を形成する構
成とする。A first region (100) of the first conductivity type, a second region (1) of the second conductivity type selectively formed on the surface layer of the first main surface of the first region (100), Third region (4) of the first conductivity type selectively formed on the surface layer of second region (1)
A first source region (10) of the second conductivity type selectively formed on the surface layer of the third region (4); and a region between the third region (4) and the first drain region (5). An insulating film on the surface of the fifth region (2) of the first conductivity type formed so as to be in contact with the first region and the third region (4) interposed between the first source region (10) and the second region (1). The first gate electrode (31) formed via the first region and the surface layer of the second region (1), and selectively formed on the surface layer of the second region (1);
A sixth region (3) of the second conductivity type connected to the high potential side of another circuit formed in the second region (1), and a second region (1)
A seventh region (6) of the first conductivity type selectively formed on the surface layer of the first circuit and connected to the low potential side of the other circuit; and a first electrode formed on the first drain region (5). (42) and a first level shift resistor (RL1) provided between the second electrode (43) formed on the sixth region (3) and a high withstand voltage IC having a first drain region (RL). 5) A part of the second region (1) between the sixth region (3) and a portion selectively facing the first source region (10) with the first drain region (5) interposed therebetween. One high resistance region (51) is formed.

【００２０】第一導電形の第一領域（１００）と、第一
領域（１００）の第一主面の表面層に選択的に形成され
た第二導電形の第二領域（１）と、第二領域（１）の表
面層に第一領域（１００）に重なりを持つように選択的
に形成された第一導電形の第五領域（２）と、第五領域
（２）とは別に第二領域（１）の表面層に選択的に形成
され、第二領域（１）内に構成される他回路の高電位側
に接続される第二導電形の第六領域（３）と、第六領域
（３）の表面層に第二領域（１）と重なりを持つように
選択的に形成された第一導電形の第二ソース領域（１
７）と、第五領域（２）と第二ソース領域（１７）に挟
まれた第二領域（１）の表面上に絶縁膜を介して形成さ
れた第二ゲート電極（３２）と、第五領域（２）に選択
的に形成された第一導電形の第二ドレイン領域（１８）
と、第二領域（１）内に構成される他回路の低電位側に
接続される第一導電形の第七領域（６）と、第五領域
（２）内で、第二領域（１）の外側に第一領域（１０
０）とオーミックコンタクトをとるための第一導電形の
第八領域（１６）と、第八領域（１６）上に形成された
第三電極（４１）と第二ドレイン領域（１８）上に形成
された第一電極（４２）との間に設けられた第二レベル
シフト用抵抗（ＲL2）を備える高耐圧ＩＣにおいて、第
二ドレイン領域（１８）と第十領域（１６）の間の第五
領域（２）の一部に、第二ドレイン領域（１８）を挟ん
で、第二ソース領域（１７）と対向する箇所に選択的に
第二高抵抗領域（５２）を形成する構成とする。A first region of the first conductivity type, a second region of the second conductivity type selectively formed on the surface layer of the first main surface of the first region; A fifth region (2) of the first conductivity type selectively formed on the surface layer of the second region (1) so as to overlap the first region (100), and a fifth region (2) are separately provided. A sixth region (3) of the second conductivity type selectively formed on the surface layer of the second region (1) and connected to the high potential side of another circuit configured in the second region (1); The second source region (1) of the first conductivity type selectively formed on the surface layer of the sixth region (3) so as to overlap the second region (1).
7) a second gate electrode (32) formed on the surface of the second region (1) interposed between the fifth region (2) and the second source region (17) via an insulating film; A second drain region of a first conductivity type selectively formed in the five regions;
A seventh region (6) of the first conductivity type connected to the lower potential side of another circuit formed in the second region (1); and a second region (1) in the fifth region (2). ) Outside the first area (10
0), an eighth region (16) of the first conductivity type for making ohmic contact with the third electrode (41) and the second drain region (18) formed on the eighth region (16). In the high withstand voltage IC including the second level shift resistor (RL2) provided between the first electrode (42) and the fifth electrode between the second drain region (18) and the tenth region (16), The second high resistance region (52) is selectively formed in a part of the region (2) opposite to the second source region (17) with the second drain region (18) interposed therebetween.

【００２１】第一導電形の第一領域（１００）と、第一
領域（１００）の第一主面の表面層に選択的に形成され
た第二導電形の第二領域（１）と、第二領域（１）の表
面層に選択的に形成された第一導電形の第三領域（４）
と、第三領域（４）の表面層に選択的に形成された第二
導電形の第一ソース領域（１０）と、第三領域（４）と
第一ドレイン領域（５）の間を両者に接するように形成
された第一導電形の第五領域（２）と、第一ソース領域
（１０）および第二領域（１）に挟まれた第三領域
（４）の表面上に絶縁膜を介して形成された第一ゲート
電極（３１）と、第二領域（１）の表面層に選択的に形
成され、第二領域（１）の表面層に選択的に形成され、
第二領域（１）内に構成される他回路の高電位側に接続
される第二導電形の第六領域（３）と、第二領域（１）
の表面層に選択的に形成され、前記の他回路の低電位側
に接続される第一導電形の第七領域（６）と、第一ドレ
イン領域（５）上に形成された第一電極（４２）と第六
領域（３）上に形成された第二電極（４３）との間に設
けられた第一レベルシフト用抵抗（ＲL1）とを備え、第
一導電形の第一領域（１００）と、第一領域（１００）
の第一主面の表面層に選択的に形成された第二導電形の
第二領域（１）と、第二領域（１）の表面層に第一領域
（１００）に重なりを持つように選択的に形成された第
一導電形の第五領域（２）と、第五領域（２）とは別に
第二領域（１）の表面層に選択的に形成され、第二領域
（１）内に構成される他回路の高電位側に接続される第
二導電形の第六領域（３）と、第六領域（３）の表面層
に第二領域（１）と重なりを持つように選択的に形成さ
れた第一導電形の第二ソース領域（１７）と、第五領域
（２）と第三ソース領域（１７）に挟まれた第二領域
（１）の表面上に絶縁膜を介して形成された第二ゲート
電極（３２）と、第五領域（２）に選択的に形成された
第一導電形の第二ドレイン領域（１８）と、第二領域
（１）内に構成される他回路の低電位側に接続される第
一導電形の第七領域（６）と、第五領域（２）内で、第
二領域（１）の外側に第一領域（１００）とオーミック
コンタクトをとるための第一導電形の第八領域（１６）
と、第八領域（１６）上に形成された第三電極（４１）
と第二ドレイン領域（１８）上に形成された第一電極
（４２）との間に設けられた第二レベルシフト用抵抗
（ＲL2）を備える高耐圧ＩＣにおいて、第一ドレイン領
域（５）と第六領域（３）間の第二領域（１）の一部
に、第一ドレイン領域（５）を挟んで第一ソース領域
（１０）と対向する箇所に選択的に第一高抵抗領域（５
１）を形成し、且つ、第二ドレイン領域（１８）と第八
領域（１６）の間の第五領域（２）の一部に、第二ドレ
イン領域（１８）を挟んで、第二ソース領域（１７）と
対向する箇所に選択的に第二高抵抗領域（５２）を形成
する構成とする。A first region (100) of the first conductivity type and a second region (1) of the second conductivity type selectively formed on the surface layer of the first main surface of the first region (100); Third region (4) of the first conductivity type selectively formed on the surface layer of second region (1)
A first source region (10) of the second conductivity type selectively formed on the surface layer of the third region (4); and a region between the third region (4) and the first drain region (5). An insulating film on the surface of the fifth region (2) of the first conductivity type formed so as to be in contact with the first region and the third region (4) interposed between the first source region (10) and the second region (1). The first gate electrode (31) formed via the first region and the surface layer of the second region (1), and selectively formed on the surface layer of the second region (1);
A sixth region (3) of the second conductivity type connected to the high potential side of another circuit formed in the second region (1), and a second region (1)
A seventh region (6) of the first conductivity type selectively formed on the surface layer of the first circuit and connected to the low potential side of the other circuit; and a first electrode formed on the first drain region (5). (42) and a first level shift resistor (RL1) provided between the second electrode (43) formed on the sixth region (3), and a first region of the first conductivity type (RL1). 100) and the first area (100)
And the second region (1) of the second conductivity type selectively formed on the surface layer of the first main surface of the first region and the first region (100) on the surface layer of the second region (1). The selectively formed fifth region (2) of the first conductivity type and the second region (1) are selectively formed on the surface layer of the second region (1) separately from the fifth region (2). The sixth region (3) of the second conductivity type connected to the high potential side of the other circuit formed therein and the second region (1) overlap with the surface layer of the sixth region (3). An insulating film is formed on the surface of the selectively formed second source region (17) of the first conductivity type and the second region (1) sandwiched between the fifth region (2) and the third source region (17). A second gate electrode (32) formed through the first region, a second drain region (18) of the first conductivity type selectively formed in the fifth region (2), and a second region (1). Composed Forming an ohmic contact with the first region (100) outside the second region (1) within the seventh region (6) of the first conductivity type connected to the low potential side of the circuit and within the fifth region (2); Eighth region of the first conductivity type to be taken (16)
And a third electrode (41) formed on the eighth region (16)
A high-breakdown-voltage IC having a second level-shifting resistor (RL2) provided between the first drain region (5) and the first electrode (42) formed on the second drain region (18). In a part of the second region (1) between the sixth regions (3), the first high-resistance region () is selectively located at a position facing the first source region (10) with the first drain region (5) interposed therebetween. 5
1) is formed, and a second source is formed in a part of the fifth region (2) between the second drain region (18) and the eighth region (16) with the second drain region (18) interposed therebetween. The second high-resistance region (52) is selectively formed at a position facing the region (17).

【００２２】前記の第一高抵抗領域（５１）が、第二領
域（１）の一部を切り離して、形成されてもよい。また
この第一高抵抗領域（５１）が、第二領域（１）の一部
の拡散深さを浅くして形成されてもよい。第一高抵抗領
域（５１）が、第二領域（１）の一部に第一導電形の第
八領域（５５）を設けることで形成されてもよい。この
第一高抵抗領域（５１）が、第二領域の一部にトレンチ
溝の第九領域（５７）を設けることで形成されてもよ
い。さらに、前記の第二高抵抗領域（５２）が、第五領
域（２）の一部を切り離して形成されてもよい。この第
二高抵抗領域（５２）が、第五領域（２）の一部の拡散
深さを浅くして形成されてもよい。また第二高抵抗領域
（５２）が、第五領域（２）の一部に第二導電形の第十
一領域（５６）を設けることで形成されてもよい。この
第二高抵抗領域（５２）が、第五領域（２）の一部にト
レンチ溝の第十二領域（５８）を設けることで形成され
てもよい。The first high-resistance region (51) may be formed by cutting off a part of the second region (1). Further, the first high-resistance region (51) may be formed by reducing the diffusion depth of a part of the second region (1). The first high resistance region (51) may be formed by providing an eighth region (55) of the first conductivity type in a part of the second region (1). The first high resistance region (51) may be formed by providing a ninth region (57) of the trench groove in a part of the second region. Further, the second high-resistance region (52) may be formed by cutting off a part of the fifth region (2). The second high-resistance region (52) may be formed with a shallow diffusion depth of a part of the fifth region (2). The second high resistance region (52) may be formed by providing an eleventh region (56) of the second conductivity type in a part of the fifth region (2). The second high resistance region (52) may be formed by providing a twelfth region (58) of the trench groove in a part of the fifth region (2).

【００２３】前記の第一ソース領域（１０）が複数個に
分割されて形成されてもよい。前記のように第一または
第二高抵抗領域を設けることで、チップサイズを大きく
することなしにレベルシフタの寄生抵抗を大きくするこ
とができる。The first source region (10) may be divided into a plurality of portions. By providing the first or second high resistance region as described above, the parasitic resistance of the level shifter can be increased without increasing the chip size.

【００２４】[0024]

【発明の実施の形態】図１はこの発明の第１実施例で、
ＨＶＩＣの一部の要部平面図であり、図２は図１のｎチ
ャネルＭＯＳＦＥＴ部を拡大した要部平面図であり、図
３は図１のＡ−Ａ’線で切断した要部断面図であり、図
４は図１のＢ−Ｂ’線で切断した要部断面図である。FIG. 1 shows a first embodiment of the present invention.
FIG. 2 is a plan view of an essential part of the HVIC, FIG. 2 is an enlarged plan view of an essential part of the n-channel MOSFET part of FIG. 1, and FIG. FIG. 4 is a cross-sectional view of a main part taken along line BB ′ of FIG.

【００２５】図１は図１０の上アームにあるＩＧＢＴで
あるＱ１を駆動する図１１に示した一つのＧＤＵである
ＧＤＵ−Ｕと、ＬＳＵ（ＲL1、ＲL2は省略されている）
を示している。勿論、ＧＤＵ−Ｖ、ＧＤＵ−Ｗも同様の
構成をしている。また半導体の表面にゲート電極が投影
された平面図を示している。尚、同図においてｎチャネ
ルレベルシフタおよびｐチャネルレベルシフタは一つず
つ記載してあるが、この１入力方式では、ｎチャネルＭ
ＯＳＦＥＴおよびｐチャネルＭＯＳＦＥＴが長い期間オ
ン状態となり、これらのＭＯＳＦＥＴのオン期間中に貫
通電流が流れ続けて、消費電力が大きくなる。これを回
避するためにそれぞれ二つずつｎチャネルＭＯＳＦＥＴ
およびｐチャネルＭＯＳＦＥＴを設ける２入力方式とす
ることで、オン信号・オフ信号をパルス的に伝えること
でＭＯＳＦＥＴのオン期間を短縮して、レベルシフタの
消費電力を大幅に低減するできるので、この方式が用い
られることが多い。以下に説明する実施例では単純化し
て１入力方式に対応するＨＶＩＣについてである。勿
論、２入力方式に同様のやり方で拡張できる。FIG. 1 shows one GDU GDU-U shown in FIG. 11 for driving the IGBT Q1 in the upper arm of FIG. 10, and LSU (RL1 and RL2 are omitted).
Is shown. Of course, GDU-V and GDU-W have the same configuration. In addition, a plan view in which a gate electrode is projected on a surface of a semiconductor is shown. It should be noted that although one n-channel level shifter and one p-channel level shifter are shown in FIG.
The OSFET and the p-channel MOSFET are on for a long period of time, and a through current continues to flow during the on-period of these MOSFETs, thereby increasing power consumption. To avoid this, two n-channel MOSFETs each
By using a two-input method in which a p-channel MOSFET is provided, the on-period of the MOSFET can be shortened by transmitting the ON signal and the OFF signal in a pulsed manner, and the power consumption of the level shifter can be greatly reduced. Often used. In the embodiment described below, the HVIC corresponding to the one-input method is simplified. Of course, it can be extended in a similar manner to a two-input system.

【００２６】図１、図２、図３および図４を用いて、こ
の発明の第１実施例のＨＶＩＣを説明する。まず、ｎチ
ャネルレベルシフタについて説明する。図１に示すよう
に、ｎチャネルレベルシフタに用いられる高耐圧ｎチャ
ネルＭＯＳＦＥＴはＧＤＵ−Ｕの角に配置されている。
この高耐圧ｎチャネルＭＯＳＦＥＴのｎ⁺ソース領域１
０は、図２で示すように第１ｎ⁺ソース領域１１と第２
ｎ⁺ソース領域１２の２個に分離されて形成されている
（この第１と第２の番号をつけたのは、同一導電形のｎ
⁺ソース領域を二分割したためで、請求項で述べた第二
導電形の第一ソース領域（１０）と第一導電形の第二ソ
ース領域（１７）とは意味が違う）。高耐圧ｎチャネル
ＭＯＳＦＥＴのｎドレイン領域５と電源ＶCCの高電位側
と接続するｎ領域３との間のｎ^-ウエル領域１を局部的
にｐ基板１００が露出する開口部２１を設け、図３で示
す高抵抗領域５１を形成する。この高抵抗領域５１はｎ
^-ウエル領域１が湾曲している箇所を含んでいる。この
高抵抗領域５１を設けることで高耐圧ｎチャネルＭＯＳ
ＦＥＴのｎドレイン５からｎ領域３にいたる寄生抵抗Ｒ
1をチップ面積を大きくすること無く、大きくすること
ができる。なぜならば、第１および第２ソース領域１
１、１２からゲート電極３１の真下に形成されたチャネ
ルを通して、ｎ^-ウエル領域１に注入された電子の一部
が寄生抵抗Ｒ１を通してｎ領域３に流入し、不要な電流
となる。しかし、この高抵抗領域５１を設けることで、
この電流が高抵抗領域５１を迂回して流れ、その結果、
寄生抵抗Ｒ１が大きくなり、不要な電流を低減すること
ができる。The HVIC according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3 and 4. First, the n-channel level shifter will be described. As shown in FIG. 1, the high-breakdown-voltage n-channel MOSFET used for the n-channel level shifter is arranged at a corner of the GDU-U.
N ⁺ source region 1 of this high breakdown voltage n-channel MOSFET
0 is the first n ⁺ source region 11 and the second n ⁺ source region 11 as shown in FIG.
n ⁺ source regions 12 (the first and second numbers indicate n ⁺ source regions 12 of the same conductivity type).
^{Since the +} source region is divided into two, the first source region of the second conductivity type and the second source region of the first conductivity type have different meanings. An opening 21 through which the p-substrate 100 is locally exposed is provided in the n ^- well region 1 between the n-drain region 5 of the high-breakdown-voltage n-channel MOSFET and the n-region 3 connected to the high potential side of the power supply VCC. The high resistance region 51 shown by the symbol is formed. This high resistance region 51 is n
^- includes a location where the well region 1 is curved. By providing this high resistance region 51, a high breakdown voltage n-channel MOS
Parasitic resistance R from n drain 5 to n region 3 of FET
1 can be increased without increasing the chip area. This is because the first and second source regions 1
Some of the electrons injected into the n ^- well region 1 from the transistors 1 and 12 through the channel formed immediately below the gate electrode 31 flow into the n-region 3 through the parasitic resistance R1, resulting in unnecessary current. However, by providing this high resistance region 51,
This current flows around the high resistance region 51, and as a result,
The parasitic resistance R1 increases, and unnecessary current can be reduced.

【００２７】この高抵抗領域５１の入れ方としては、高
耐圧ｎチャネルＭＯＳＦＥＴのｎドレイン領域５とＧＤ
Ｕ−Ｕの外周に位置するｎ領域３とを結ぶ点線とＧＤＵ
−Ｕの外周に位置するｎ領域３で囲まれた三角形領域
で、且つ、高耐圧ｎチャネルＭＯＳＦＥＴの第２ｎ⁺ソ
ース領域１２とｎドレイン領域５を挟んで対向する箇所
に形成すると前記の迂回して流れる電子の通路の長さが
長くなり効果的である。但しこの高抵抗領域５１が前記
の点線に達すると耐圧が劣化する可能性があるため、こ
れに達しないようにしなければならない。なぜならばこ
の点線は空乏層が広がるＨＶＪＴの端部となるため、こ
の点線に高抵抗領域５１が達すると、空乏層の延びが抑
えられて、電界集中を起こすからである。The way to insert the high resistance region 51 is as follows: the n drain region 5 of the high breakdown voltage n channel MOSFET and the GD
A dotted line connecting the n region 3 located on the outer periphery of UU and GDU
The above-described detour is formed in a triangular region surrounded by the n region 3 located on the outer periphery of -U, and at a position facing the second n ⁺ source region 12 and the n drain region 5 of the high breakdown voltage n-channel MOSFET. This is effective because the length of the path of the flowing electrons is increased. However, if the high-resistance region 51 reaches the above-mentioned dotted line, the withstand voltage may be degraded. This is because the dotted line is the end of the HVJT where the depletion layer spreads, and when the high resistance region 51 reaches this dotted line, the extension of the depletion layer is suppressed and electric field concentration occurs.

【００２８】またｎ^-ウエル領域１を開口した場合は、
高抵抗領域５１でｎ^-ウエル領域１は二分されることが
なく、高抵抗領域５１以外の領域はｎ^-ウエル領域１で
繋がっている。Ｕ−ＶCCとＣＯＭ間に電圧を印加する
と、ｎ^-ウエル領域１とｐ^-基板１００で形成されるｐ
ｎ接合が逆バイアスされ、この高抵抗領域５１（この領
域はｐ^-基板１００である）は低い電圧でピンチオフす
る。そのため、ｎ^-ウエル領域１を完全に二分した場合
（開口するのでは無く、完全にｎ^-ウエル領域１を切り
離した場合）に比べて耐圧の低下は小さいという利点が
ある。開口部２１の形状をスリット状に形成した場合、
このスリットは開口部が潰れない程度の幅でよい。When the n ^- well region 1 is opened,
The n ⁻ well region 1 is not divided into two in the high resistance region 51, and regions other than the high resistance region 51 are connected by the n ⁻ well region 1. When a voltage is applied between the U-VCC and COM, n ^- well region 1 and the p ^- p formed in the substrate 100
The n-junction is reverse biased and this high resistance region 51 (which is the p ^- substrate 100) pinches off at a low voltage. Therefore, n ^- if you divide the well region 1 entirely (rather than open, completely n ^- If you disconnected well region 1) decrease in breakdown voltage in comparison with the advantage that small. When the shape of the opening 21 is formed in a slit shape,
This slit may have such a width that the opening is not crushed.

【００２９】また図１ではｎドレイン領域５を中心に円
弧を書くような曲線状の開口部２１を示したが、曲線で
なく多数の直線の集まりでもよく、また多数の小さな独
立した円が連なっても、寄生抵抗Ｒ1 が増加するので、
効果がある。また全体のレイアウトの都合上、ＧＤＵ−
Ｕを四角に近い形でレイアウトする場合は、図１０のよ
うに高耐圧ｎチャネルＭＯＳＦＥＴはゲート電極１０と
ｎドレイン領域５のある領域がとび出た形にしてもよ
い。Although FIG. 1 shows the curved opening 21 which draws an arc centered on the n-drain region 5, it may be a set of a large number of straight lines instead of a curved line, and a large number of small independent circles are connected. However, since the parasitic resistance R1 increases,
effective. Also, due to the overall layout, GDU-
When U is laid out in a shape close to a square, the high-breakdown-voltage n-channel MOSFET may have a shape in which a region including the gate electrode 10 and the n-drain region 5 protrudes as shown in FIG.

【００３０】次にｐチャネルレベルシフタについて述べ
る。図１において高耐圧ｐチャネルＭＯＳＦＥＴはＧＤ
Ｕ−Ｕの角に配置し、高耐圧ｐチャンネルＭＯＳＦＥＴ
のｐ ⁺ドレイン領域１８とｐ^-オフセット領域２の外周
のｐウエル領域４（この外周にＶＣＣ２Ｌレベルのコン
タクトをとるためのｐ⁺領域１６があり、ｐ⁺ドレイン
領域１８と同時に形成される。）の間のｐ^-オフセット
領域２を局部的に開口する。この開口部２２でｎ^-ウエ
ル領域１が露出するスリット状の高抵抗領域５２を設け
る。高抵抗領域５２は図４のようにｐ^-オフセット領域
２が湾曲している箇所も含む。Next, the p-channel level shifter will be described.
You. In FIG. 1, the high breakdown voltage p-channel MOSFET is GD
High breakdown voltage p-channel MOSFET placed at the corner of U-U
P ⁺Drain region 18 and p^-Outer circumference of offset area 2
P well region 4 (a VCC2L level
P for taking tact⁺There is a region 16 and p⁺drain
It is formed simultaneously with the region 18. P during^-offset
The region 2 is locally opened. In this opening 22, n^-Ue
A slit-shaped high-resistance region 52 from which the metal region 1 is exposed.
You. As shown in FIG.^-Offset area
2 includes a curved portion.

【００３１】こうすることで高耐圧ｐチャネルＭＯＳＦ
ＥＴのｐ⁺ドレイン領域１８からｐウエル領域４にいた
る寄生抵抗Ｒ２をチップ面積を大きくすること無く、大
きくすることができる。この高抵抗領域５２は、ｐ^-オ
フセット領域２の外周側に形成されたｐウエル領域４の
内周部の曲線部と、高耐圧ｐチャンネルＭＯＳＦＥＴの
ｐ⁺ドレイン領域１８とこのｐウエル領域４の内周部の
直線部に垂直に下ろした点線とで囲まれる三角形領域に
形成する。但し、前記と同様な理由で、この高抵抗領域
５２が前記の点線（ＨＶＪＴの一端を示す点線）に達す
ると耐圧が劣化する可能性がある。また開口部２２をス
リット状に形成した場合、このスリットは開口部が潰れ
ない程度の幅でよい。By doing so, a high breakdown voltage p-channel MOSF
The parasitic resistance R2 from the p ⁺ drain region 18 of the ET to the p well region 4 can be increased without increasing the chip area. The high resistance region 52 includes a curved portion of the inner periphery of the p well region 4 formed on the outer periphery of the p ⁻ offset region 2, the p ⁺ drain region 18 of the high breakdown voltage p-channel MOSFET, and the p well region 4. It is formed in a triangular region surrounded by a straight line portion on the inner periphery and a dotted line vertically lowered. However, for the same reason as described above, if the high resistance region 52 reaches the dotted line (dotted line indicating one end of the HVJT), the breakdown voltage may be degraded. When the opening 22 is formed in a slit shape, the slit may have such a width that the opening is not crushed.

【００３２】また図１ではｐ⁺ドレイン領域１８を中心
に円弧を書くような曲線状の開口部２２を示したが、曲
線でなく多数の直線の集まりでもよく、また多数の小さ
な独立した円が連なっても、寄生抵抗Ｒ２が増加するの
で効果がある。また全体のレイアウトの都合上、これを
ＧＤＵ−Ｕの角にせず、ＧＤＵ−Ｕの辺上に形成しても
よい。Although FIG. 1 shows the curved opening 22 which draws an arc centered on the p ⁺ drain region 18, it may be a collection of a large number of straight lines instead of a curve. Even if they are connected, it is effective because the parasitic resistance R2 increases. In addition, for convenience of the entire layout, this may not be a corner of the GDU-U but may be formed on a side of the GDU-U.

【００３３】尚、前記ではｎチャネルＭＯＳＦＥＴのソ
ース領域が第１ｎ⁺ソース領域１１と第２ｎ⁺ソース領
域１２に分離されているが、接続していても構わない。
また、図２において、ｐ^-オフセット領域２がｎ^-ウエ
ル領域１の内側で分離しているが、ｐ^-オフセット領域
２を分離せずｎドレイン領域５とｎ領域３間をｐ^-オフ
セット領域２で結んでも構わない。In the above description, the source region of the n-channel MOSFET is separated into the first n ⁺ source region 11 and the second n ⁺ source region 12, but they may be connected.
Further, in FIG. 2, p ^- although separated inside the well region 1, p ^- ^- offset region 2 n between n drain region 5 and the n region 3 without separating the offset region 2 p ^- offset regions 2 May be tied together.

【００３４】また、前記以外のｐウエル領域４とｎ領域
３が直線で対向しているｎ^-ウエル領域１およびｐ^-オ
フセット領域２に高抵抗領域５１および高抵抗領域５２
を形成しても寄生抵抗Ｒ1 、Ｒ2 を大きくする効果は極
めて小さく、また設けない場合に比べて耐圧を低下させ
るため、高抵抗領域５１、５２を形成しない方がよい。
尚、ＧＤＵ−Ｕ内に形成されるＵ−ＶCCは電源ＶCCの高
電位端子、Ｕ−ＯＵＴは電源ＶCCの低電位端子、Ｕ−Ｇ
ＡＴＥはＧ端子、Ｕ−ＯＣは過電流検出端子、Ｕ−ＯＴ
は加熱検出端子を示す。The n ^- well region 1 and the p ^- offset region 2 where the p-well region 4 and the n-region 3 other than those described above are linearly opposed to each other, have a high resistance region 51 and a high resistance region 52.
Is formed, the effect of increasing the parasitic resistances R1 and R2 is extremely small, and the withstand voltage is reduced as compared with the case where they are not provided. Therefore, it is better not to form the high resistance regions 51 and 52.
U-VCC formed in the GDU-U is a high potential terminal of the power supply VCC, U-OUT is a low potential terminal of the power supply VCC, and UG
ATE is G terminal, U-OC is overcurrent detection terminal, U-OT
Indicates a heating detection terminal.

【００３５】つぎに、前記の第１実施例のＨＶＩＣを製
造するための製造方法について説明する。基板はｐ^-基
板１００を用い、比抵抗は素子耐圧に大きく依存する
が、例えば６００Ｖクラスの耐圧を得ようとした場合、
１００Ωｃｍ程度が必要である。このｐ^-基板１００に
低濃度（１０¹²ｃｍ^-2のオーダ）で接合深さ５〜６μｍ
程度のリン拡散によるｎ^-ウエル領域１を形成し、次に
ＲＥＳＵＲＦを構成するためのｐ^-オフセット領域２を
ドーズ量が１０¹³ｃｍ^-2のオーダで接合深さが１μｍ程
度のボロンのイオン注入で形成する。このｎ^-ウエル領
域１とｐ^-オフセット領域２は前記の高抵抗領域５１、
５２が形成されるように、イオン注入時のマスクに選択
的に開口部（拡散後の開口部２１、２２となる）を設け
る。Next, a manufacturing method for manufacturing the HVIC of the first embodiment will be described. As the substrate, a p ⁻ substrate 100 is used, and the specific resistance greatly depends on the withstand voltage of the element.
About 100Ωcm is required. The p ^- substrate 100 has a low concentration (on the order of 10 ¹² cm ^-2 ) and a junction depth of 5 to 6 μm.
An n ^- well region 1 is formed by phosphorus diffusion to a degree, and then a p ^- offset region 2 for forming a RESURF is ion-implanted with boron having a dose of the order of 10 ¹³ cm ^-2 and a junction depth of about 1 μm. Formed. The n ^- well region 1 and the p ^- offset region 2 correspond to the high resistance region 51,
Openings (which become openings 21 and 22 after diffusion) are selectively provided in the mask at the time of ion implantation so that 52 is formed.

【００３６】このｐ^-オフセット領域２は高電圧におい
て完全に空乏化させる必要があり、また濃度によって電
界集中のバランスが大きくことなるため、高耐圧を実現
するためにはこのｐ^-オフセット領域２とｎ^-ウエル領
域１のイオン注入時のドーズ量と接合深さの最適化が重
要である。次にｎチャネルＭＯＳＦＥＴのチャネルを形
成するためのｐウエル領域４をドーズ量１０¹³ｃｍ^-2の
オーダで接合深さ１μｍ程度、ボロンのイオン注入で形
成し、電源ＶCCの高電位電極４３にｎ⁺領域１４を介し
て接続するｎ領域３、ｎドレイン領域５を１０¹³ｃｍ^-2
のオーダで接合深さ１μｍ程度、リンのイオン注入で形
成したあと、活性領域とポリシリコンによりゲート電極
３１、３２を形成する。更にそれぞれのｐ領域６、ｎ領
域３およびｎドレイン領域５とのコンタクトさせるため
のｐ⁺領域１５、ｎ⁺領域１４、あるいはｎチャネルＭ
ＯＳＦＥＴのｎ⁺ソース領域１１、１２を形成するため
のｎ⁺拡散をフッ化ボロン（ＢＦ₂）やヒ素で、オーミ
ックコンタクトが可能な表面濃度で行い、その後アルミ
ニウムでＣＯＭ電極４１、ドレイン電極４２、高電位電
極４３、低電位電極４４を形成する。[0036] The p ^- offset region 2 must be completely depleted at high voltages, and because the different large balance of electric field concentration by the concentration, in order to realize a high breakdown voltage the p ^- offset region 2 It is important to optimize the dose and the junction depth of the n ^- well region 1 during ion implantation. Next, a p-well region 4 for forming a channel of an n-channel MOSFET is formed by ion implantation of boron at a junction depth of about 1 μm with a dose of 10 ¹³ cm ⁻² and an n-type ⁺ the n region 3, n drain region 5 connected through the area 14 10 ¹³ cm ^-2
Then, a junction depth of about 1 μm is formed by ion implantation of phosphorus, and then gate electrodes 31 and 32 are formed of an active region and polysilicon. Further, ap ⁺ region 15, an n ⁺ region 14 for making contact with the respective p region 6, n region 3 and n drain region 5, or n channel M
The n ⁺ diffusion for forming the n ⁺ source regions 11 and 12 of the OSFET is performed with boron fluoride (BF ₂ ) or arsenic at a surface concentration at which ohmic contact is possible, and thereafter, the COM electrode 41, the drain electrode 42, and the like are formed of aluminum. A high potential electrode 43 and a low potential electrode 44 are formed.

【００３７】図５はこの発明の第２実施例の要部平面図
である。同図のＡ−Ａ切断線による断面図は図３と同一
である。同図の説明は第１実施例で説明したので省略す
る。この実施例ではｐチャネルシフトレジスタが不要な
場合や、別の半導体チップに設ける場合であり、当然チ
ップサイズは第１実施例より小さくすることができる。FIG. 5 is a plan view of a main part of a second embodiment of the present invention. The sectional view taken along the line AA in FIG. 7 is the same as FIG. The description of FIG. 11 has been described in the first embodiment, and a description thereof will be omitted. In this embodiment, the p-channel shift register is unnecessary or provided on another semiconductor chip, and the chip size can be made smaller than that of the first embodiment.

【００３８】図６はこの発明の第３実施例の要部平面図
である。同図のＢ−Ｂ切断線による断面図は図４と同一
である。同図の説明は第１実施例で説明したので省略す
る。この実施例ではｎチャネルシフトレジスタを別の半
導体チップに設ける場合であり、当然チップサイズは第
１実施例より小さくすることができる。図７はこの発明
の第４実施例で、高抵抗領域を開口部が潰れた場合で、
同図（ａ）はｎ^-ウエル領域に高抵抗領域を設けた場
合、同図（ｂ）はｐ^-オフセット領域に高抵抗領域を設
けた場合である。同図（ａ）は図１のＡ−Ａ’線で切断
した要部断面図を示し、同図（ｂ）は図１のＢ−Ｂ’線
で切断した要部断面図である。図示されるように開口部
２１、２２が拡散で埋まり、その部分の拡散深さｔ1 、
ｔ2 がｎ^-ウエル領域１の拡散深さＸｊ1 またはｐ^-オ
フセット領域２の拡散深さＸｊ2 より浅くなっている場
合でも、その箇所の高抵抗領域５３、５４の領域のシー
ト抵抗が大きくなるので、寄生抵抗を大きくするという
点で効果がある。しかし、第１実施例のようにｎ^-ウエ
ル領域１やｐ^-オフセット領域２が完全に開口している
場合に比べるとその効果は小さい。ここでは、図１に相
当した実施例を説明したが、勿論、図５、図６に相当す
る実施例もある。FIG. 6 is a plan view of a main part of a third embodiment of the present invention. The cross-sectional view taken along the line BB of FIG. The description of FIG. 11 has been described in the first embodiment, and a description thereof will be omitted. In this embodiment, the n-channel shift register is provided on another semiconductor chip, and the chip size can be made smaller than that of the first embodiment. FIG. 7 shows a fourth embodiment of the present invention, in which the high resistance region is crushed at the opening.
FIG. 3A shows a case where a high resistance region is provided in an n ⁻ well region, and FIG. 3B shows a case where a high resistance region is provided in a p ⁻ offset region. FIG. 2A is a sectional view taken along line AA ′ in FIG. 1, and FIG. 2B is a sectional view taken along line BB ′ in FIG. As shown, the openings 21 and 22 are filled with diffusion, and the diffusion depth t1,
Even if t2 is shallower than the diffusion depth Xj1 of the n ^- well region 1 or the diffusion depth Xj2 of the p ^- offset region 2, the sheet resistance of the high resistance regions 53 and 54 at that location becomes large. This is effective in increasing the parasitic resistance. However, the effect is smaller than when the n ^- well region 1 and the p ^- offset region 2 are completely open as in the first embodiment. Here, the embodiment corresponding to FIG. 1 has been described, but of course, there is also an embodiment corresponding to FIG. 5 and FIG.

【００３９】図８はこの発明の第５実施例で、高抵抗領
域を反対の導電形領域で形成した場合で、同図（ａ）は
ｎ^-ウエル領域に高抵抗領域を設けた場合、同図（ｂ）
はｐ ^-オフセット領域に高抵抗領域を設けた場合であ
る。同図（ａ）は図１のＡ−Ａ’線で切断した要部断面
図を示し、同図（ｂ）は図１のＢ−Ｂ’線で切断した要
部断面図である。勿論、同図では高抵抗領域５５、５６
が接合を突き抜けているが、突き抜けなくともよい。図
１のようにこの場合も同様に寄生抵抗は大きくなる。FIG. 8 shows a fifth embodiment of the present invention.
In the case where the region is formed by the opposite conductivity type region, FIG.
n^-In the case where a high resistance region is provided in the well region, FIG.
Is p ^-When a high resistance area is provided in the offset area
You. FIG. 2A is a cross-sectional view of a main part taken along line A-A ′ in FIG.
FIG. 2B is a sectional view taken along line B-B ′ of FIG.
It is a fragmentary sectional view. Of course, in FIG.
Penetrates the joint, but does not have to penetrate. Figure
As in the case of 1, the parasitic resistance also becomes large in this case.

【００４０】図９はこの発明の第６実施例で、高抵抗領
域をトレンチ溝で形成した場合の図で、同図（ａ）はｎ
^-ウエル領域に高抵抗領域を設けた場合、同図（ｂ）は
ｐ^-オフセット領域に高抵抗領域を設けた場合である。
同図（ａ）は図１のＡ−Ａ’線で切断した要部断面図を
示し、同図（ｂ）は図１のＢ−Ｂ’線で切断した要部断
面図である。勿論、同図では高抵抗領域５７、５８が接
合を突き抜けているが、突き抜けなくともよい。図１の
ようこの場合も寄生抵抗は大きくなる。FIG. 9 shows a sixth embodiment of the present invention, in which a high-resistance region is formed by a trench. FIG.
^- If provided a high-resistance region in the well region, FIG. (B) is p ^- is a case in which the high-resistance region in the offset region.
FIG. 2A is a sectional view taken along line AA ′ in FIG. 1, and FIG. 2B is a sectional view taken along line BB ′ in FIG. Needless to say, the high resistance regions 57 and 58 penetrate the junction in FIG. As shown in FIG. 1, the parasitic resistance also increases in this case.

【００４１】尚、図１において、第一高抵抗領域５１と
第二高抵抗領域５２の形成に当たっては前記した実施例
を組み合わせても勿論よい。In FIG. 1, the first embodiment and the second high resistance region 52 may be formed by combining the above embodiments.

【００４２】[0042]

【発明の効果】この発明によれば、ｎ^-ウエル領域およ
びｎ^-オフセット領域の一部に、開口する領域の形成、
反対導電形領域の形成、さらにトレンチ溝の形成により
高抵抗領域を設けることのより、それぞれｎチャネルレ
ベルシフタの高耐圧ｎチャネルＭＯＳＦＥＴおよびｐチ
ャネルレベルシフタの高耐圧ｐチャネルＭＯＳＦＥＴの
耐圧特性を損なうことなく、電源と接続するｎ領域また
はｐ領域とドレイン領域との間に存在する寄生抵抗を大
きくすることができる。これにより、従来、大きな面積
を占めていた前記のドレイン領域とｎ領域またはｐ領域
間の面積を小さくできて、チップサイズの小型化と低コ
スト化を図ることができる。また寄生抵抗に流れる電流
を小さくできるので、ＨＶＩＣの消費電力を小さくでき
る。Effects of the Invention According to the present invention, n ^- well region and the n ^- part of the offset region, formed in the opening region,
By providing the high resistance region by forming the opposite conductivity type region and further forming the trench groove, the breakdown voltage characteristics of the high breakdown voltage n-channel MOSFET of the n-channel level shifter and the high breakdown voltage p-channel MOSFET of the p-channel level shifter can be reduced, respectively. The parasitic resistance existing between the drain region and the n region or the p region connected to the power supply can be increased. As a result, the area between the drain region and the n region or the p region, which conventionally occupies a large area, can be reduced, and the chip size and cost can be reduced. Further, since the current flowing through the parasitic resistance can be reduced, the power consumption of the HVIC can be reduced.

[Brief description of the drawings]

【図１】この発明の第１実施例で、ＨＶＩＣの一部の要
部平面図FIG. 1 is a plan view of a main part of an HVIC according to a first embodiment of the present invention;

【図２】図１のｎチャネルＭＯＳＦＥＴ部を拡大した要
部平面図FIG. 2 is an enlarged plan view of an essential part of the n-channel MOSFET section of FIG. 1;

【図３】図１のＡ−Ａ’線で切断した要部断面図FIG. 3 is a sectional view of an essential part taken along line A-A ′ in FIG. 1;

【図４】図１のＢ−Ｂ’線で切断した要部断面図FIG. 4 is a sectional view of an essential part taken along line B-B ′ of FIG. 1;

【図５】この発明の第２実施例の要部平面図FIG. 5 is a plan view of a main part of a second embodiment of the present invention.

【図６】この発明の第３実施例の要部平面図FIG. 6 is a plan view of a main part of a third embodiment of the present invention.

【図７】この発明の第４実施例で、高抵抗領域を開口部
が潰れた場合で、同図（ａ）はｎ^-ウエル領域に高抵抗
領域を設けた場合、同図（ｂ）はｐ^-オフセット領域に
高抵抗領域を設けた場合の要部断面図FIGS. 7A and 7B show a fourth embodiment of the present invention in which an opening is crushed in a high resistance region, FIG. 7A shows a case where a high resistance region is provided in an n ^- well region, Sectional view of main part when high resistance region is provided in p ^- offset region

【図８】この発明の第５実施例で、高抵抗領域を反対の
導電形領域で形成した場合で、同図（ａ）はｎ^-ウエル
領域に高抵抗領域を設けた場合の要部断面図で、同図
（ｂ）はｐ^-オフセット領域に高抵抗領域を設けた場合
の要部断面図[8] In the fifth embodiment of the present invention, in case of forming a high resistance region at the opposite conductivity type regions, Fig. (A) the n ^- fragmentary sectional obtained when a high-resistance region in the well region FIG. 3B is a cross-sectional view of a main part when a high resistance region is provided in a p ⁻ offset region.

【図９】図９はこの発明の第６実施例で、高抵抗領域を
トレンチ溝で形成した場合の図で、同図（ａ）はｎ^-ウ
エル領域に高抵抗領域を設けた場合、同図（ｂ）はｐ^-
オフセット領域に高抵抗領域を設けた場合の要部断面図FIG. 9 is a view showing a sixth embodiment of the present invention, in which a high resistance region is formed by a trench groove. FIG. 9A shows a case where a high resistance region is provided in an n ⁻ well region. Figure (b) is p ^-
Sectional view of main part when high resistance area is provided in offset area

【図１０】モータ制御用インバータのパワー部を中心に
説明する回路構成図FIG. 10 is a circuit configuration diagram mainly illustrating a power unit of a motor control inverter;

【図１１】ＨＶＩＣの素子構成図FIG. 11 is an element configuration diagram of an HVIC.

【図１２】ＬＳＵの基本構成図FIG. 12 is a basic configuration diagram of an LSU.

【図１３】自己分離により形成した従来の高耐圧ｎチャ
ネルレベルシフタと高耐圧ｐチャネルレベルシフタを有
する高耐圧ＩＣの要部平面図FIG. 13 is a plan view of an essential part of a high breakdown voltage IC having a conventional high breakdown voltage n-channel level shifter and a high breakdown voltage p-channel level shifter formed by self-isolation.

【図１４】図１３のＣ−Ｃ’線で切断した要部断面図FIG. 14 is a sectional view of an essential part taken along line C-C ′ in FIG. 13;

【図１５】図１３のＤ−Ｄ’線で切断した要部断面図FIG. 15 is a sectional view of an essential part taken along line D-D ′ in FIG. 13;

[Explanation of symbols]

１００ｐ^-基板１ｎ^-ウエル領域２ｐ^-オフセット領域３ｎ領域４ｐウエル領域５ｎドレイン領域６ｐ⁺領域１０ｎ⁺ソース領域１１第１ｎ⁺ソース領域１２第２ｎ⁺ソース領域１３ｎ⁺領域１４ｎ⁺領域１５ｐ⁺領域１６ｐ⁺領域１７ｐ⁺ソース領域１８ｐ⁺ドレイン領域２１開口部２２開口部３１、３２ゲート電極４１ＣＯＭ電極４２ドレイン電極４３高電位電極４４低電位電極５１〜５８高抵抗領域６１ｎチャネルＭＯＳＦＥＴ６２ｐチャネルＭＯＳＦＥＴ７０三相モータ７１パワーモジュール７２主回路駆動回路ＶCC2 主回路電源ＶCC2H 主回路電源の高電位側／高電位側電位ＶCC2L 主回路電源の低電位側／低電位側電位ＶCC ＨＶＩＣの電源ＨＶＪＴ高耐圧構造部ＲL1 レベルシフト用抵抗ＲL2 レベルシフト用抵抗ＣＯＭＶCC2Lに接続する端子Ｇゲート端子ＯＵＴドレイン端子Ｕ−ＶCC ＶCCの高電位側に接続する端子／端子の電位Ｕ−ＯＵＴＶCCの低電位側に接続する端子／端子の電
位Ｖ−ＯＵＴＶCCの低電位側に接続する端子／端子の電
位Ｗ−ＯＵＴＶCCの低電位側に接続する端子／端子の電
位Ｑ１〜Ｑ６ＩＧＢＴＤ１〜Ｄ６ダイオードＧＤＵゲート駆動回路ＣＵ制御回路ＬＳＵシフトレジスタＨＶＩＣ高耐圧ＩＣｔ1 拡散深さ（ｎ^-ウエル領域の開口部が潰れた
箇所）ｔ2 拡散深さ（ｐ^-オフセット領域の開口部が潰
れた箇所）Ｘｊ1 拡散深さ（ｎ^-ウエル領域）Ｘｊ2 拡散深さ（ｐ^-オフセット領域）Ｒ１寄生抵抗Ｒ２寄生抵抗100 p ^- substrate 1 n ^- well region 2 p ^- offset region 3 n region 4 p-well region 5 n drain region 6 p ⁺ region 10 n ⁺ source region 11 first n ⁺ source region 12 second n ⁺ source region 13 n ⁺ region 14 n ⁺ region 15 p ⁺ region 16 p ⁺ region 17 p ⁺ source region 18 p ⁺ drain region 21 opening 22 opening 31, 32 gate electrode 41 COM electrode 42 drain electrode 43 high potential electrode 44 low potential electrode 51 to 58 High resistance region 61 n-channel MOSFET 62 p-channel MOSFET 70 three-phase motor 71 power module 72 main circuit drive circuit VCC2 main circuit power supply VCC2H high potential side / high potential side potential of main circuit power supply VCC2L low potential side / low of main circuit power supply Potential side potential VCC HVIC power supply HVJT High breakdown voltage structure RL1 Level shift resistor RL2 level Shift resistor COM Terminal connected to VCC2L G Gate terminal OUT Drain terminal U-VCC Terminal / terminal connected to high potential side of VCC U-OUT Terminal / terminal potential connected to low potential side of VCC V-OUT Potential of terminal / terminal connected to low potential side of VCC W-OUT Potential of terminal / terminal connected to low potential side of VCC Q1-Q6 IGBT D1-D6 Diode GDU Gate drive circuit CU Control circuit LSU Shift register HVIC High breakdown voltage IC t1 diffusion depth (where the opening of the n ^- well region is crushed) t2 diffusion depth (where the opening of the p ^- offset region is crushed) Xj1 diffusion depth (n ^- well region) Xj2 diffusion depth ( (p ^- offset region) R1 parasitic resistance R2 parasitic resistance

Claims

[Claims]

A first region of a first conductivity type and a second region of a second conductivity type selectively formed on a surface layer of a first main surface of the first region. And a third region (4) of the first conductivity type selectively formed on the surface layer of the second region (1).
A first source region of the second conductivity type selectively formed on the surface layer of the third region; and a surface layer of the second region separated from the third region. A first source region (10) of the second conductivity type selectively formed in the first region and a third region (4).
Between the first drain region (5) and the fifth region (2) of the first conductivity type formed so as to be in contact with both, and the first source region (10) and the second region (1). A first gate electrode (31) formed on the surface of the third region (4) via an insulating film; and a first gate electrode (31) formed selectively on the surface layer of the second region (1). Selectively formed on the surface layer,
A sixth region (3) of the second conductivity type connected to the high potential side of another circuit formed in the second region (1), and a first electrode (5) formed on the first drain region (5). 42) and a first level shift resistor (RL1) provided between the second electrode (43) formed on the sixth region (3) and a high withstand voltage IC including a first drain region (5 ) And the sixth region (3), a first high-resistance region (51) is selectively formed at a position facing the first source region (10) with the first drain region (5) interposed therebetween. ), Wherein the high-voltage IC is formed.

2. A first region (100) of a first conductivity type and a second region (1) of a second conductivity type selectively formed on a surface layer of a first main surface of the first region (100). A fifth region (2) of the first conductivity type selectively formed on the surface layer of the second region (1) so as to overlap the first region (100); and a fifth region (2). The sixth region (3) of the second conductivity type is formed selectively on the surface layer of the second region (1) and connected to the high potential side of another circuit formed in the second region (1). And a second source region (17) of the first conductivity type selectively formed on the surface layer of the second region (1); and a fifth region (2) and a second source region (17). A second gate electrode (32) formed on the surface of the second region (1) via an insulating film; and a second drain region of the first conductivity type selectively formed on the fifth region (2). 18) and In the fifth region (2), the second region (1) a first conductivity type of the eighth region (1 for ohmic contact with the first region (100) formed on the outside of
6) and a third electrode (4) formed on the eighth region (16).
In a high-breakdown-voltage IC provided with a second level shift resistor (RL2) provided between the first electrode (1) and the first electrode (42) formed on the second drain region (18), the second drain region (18) ) And a fifth region (2) between the tenth region (16) and a second drain region (18).
A high withstand voltage IC, wherein a second high resistance region (52) is selectively formed at a position facing the second source region (17).

3. A first region of a first conductivity type and a second region of a second conductivity type selectively formed on a surface layer of a first main surface of the first region. And a third region (4) of the first conductivity type selectively formed on the surface layer of the second region (1).
A first source region (10) of the second conductivity type selectively formed on the surface layer of the third region (4); and a region between the third region (4) and the first drain region (5). An insulating film on the surface of the fifth region (2) of the first conductivity type formed so as to be in contact with the first region and the third region (4) interposed between the first source region (10) and the second region (1). The first gate electrode (31) formed via the first region and the surface layer of the second region (1), and selectively formed on the surface layer of the second region (1);
A sixth region (3) of the second conductivity type connected to the high potential side of another circuit formed in the second region (1), and a second region (1)
A seventh region (6) of the first conductivity type selectively formed on the surface layer of the first circuit and connected to the low potential side of the other circuit; and a first electrode formed on the first drain region (5). (42) and a high-voltage IC having a first level shift resistor (RL1) provided between the second electrode (43) formed on the sixth region (3); 5) A part of the second region (1) between the sixth region (3) and a portion selectively facing the first source region (10) with the first drain region (5) interposed therebetween. A high withstand voltage IC wherein one high resistance region (51) is formed.

4. A first region (100) of a first conductivity type and a second region (1) of a second conductivity type selectively formed on a surface layer of a first main surface of the first region (100). A fifth region (2) of the first conductivity type selectively formed on the surface layer of the second region (1) so as to overlap the first region (100); and a fifth region (2). The sixth region (3) of the second conductivity type is formed selectively on the surface layer of the second region (1) and connected to the high potential side of another circuit formed in the second region (1). And a second source region (1) of the first conductivity type selectively formed on the surface layer of the sixth region (3) so as to overlap the second region (1).
7) a second gate electrode (32) formed on the surface of the second region (1) interposed between the fifth region (2) and the second source region (17) via an insulating film; A second drain region of a first conductivity type selectively formed in the five regions;
A seventh region (6) of the first conductivity type connected to the lower potential side of another circuit formed in the second region (1); and a second region (1) in the fifth region (2). ) Outside the first area (10
0), an eighth region (16) of the first conductivity type for making ohmic contact with the third electrode (41) and the second drain region (18) formed on the eighth region (16). A high withstand voltage IC including a second level shift resistor (RL2) provided between the first electrode (42) and the fifth electrode between the second drain region (18) and the tenth region (16). A second high resistance region (52) is selectively formed in a part of the region (2) opposite to the second source region (17) with the second drain region (18) interposed therebetween. High withstand voltage IC.

5. A first region of a first conductivity type and a second region of a second conductivity type selectively formed on a surface layer of a first main surface of the first region. And a third region (4) of the first conductivity type selectively formed on the surface layer of the second region (1).
A first source region (10) of the second conductivity type selectively formed on the surface layer of the third region (4); and a region between the third region (4) and the first drain region (5). An insulating film on the surface of the fifth region (2) of the first conductivity type formed so as to be in contact with the first region and the third region (4) interposed between the first source region (10) and the second region (1). The first gate electrode (31) formed via the first region and the surface layer of the second region (1), and selectively formed on the surface layer of the second region (1);
A sixth region (3) of the second conductivity type connected to the high potential side of another circuit formed in the second region (1), and a second region (1)
A seventh region (6) of the first conductivity type selectively formed on the surface layer of the first circuit and connected to the low potential side of the other circuit; and a first electrode formed on the first drain region (5). (42) and a first level shift resistor (RL1) provided between the second electrode (43) formed on the sixth region (3), and a first region of the first conductivity type (RL1). 100) and the first area (10
0) The second region (1) of the second conductivity type selectively formed on the surface layer of the first main surface and the first region (100) overlap with the surface layer of the second region (1). The fifth region (2) of the first conductivity type selectively formed as described above and the fifth region (2) are selectively formed on the surface layer of the second region (1) separately from the second region (1). The sixth region (3) of the second conductivity type connected to the high potential side of the other circuit formed in (1), and the second region (1) overlaps the surface layer of the sixth region (3). The second source region (17) of the first conductivity type selectively formed as described above, and the surface of the second region (1) sandwiched between the fifth region (2) and the third source region (17). A second gate electrode (32) formed through an insulating film; a second drain region (18) of the first conductivity type selectively formed in the fifth region (2); and a second region (1). Configured within A seventh region (6) of the first conductivity type connected to the lower potential side of the other circuit and an ohmic contact with the first region (100) outside the second region (1) within the fifth region (2). Eighth area of the first conductivity type for making contact (16)
And a third electrode (41) formed on the eighth region (16)
A high withstand voltage IC having a second level shift resistor (RL2) provided between the first drain region (5) and the first electrode (42) formed on the second drain region (18); In a part of the second region (1) between the sixth regions (3), the first high-resistance region () is selectively located at a position facing the first source region (10) with the first drain region (5) interposed therebetween. 51) is formed, and a second source is formed in a part of the fifth region (2) between the second drain region (18) and the eighth region (16) with the second drain region (18) interposed therebetween. A high withstand voltage IC wherein a second high resistance region (52) is selectively formed at a position facing the region (17).

6. The high breakdown voltage IC according to claim 1, wherein the first high resistance region is formed by cutting off a part of the second region.

7. The high breakdown voltage IC according to claim 3, wherein the first high resistance region is formed by making a part of the second region have a small diffusion depth. .

8. The first high-resistance region (51) is formed by providing an eighth region (55) of the first conductivity type in a part of the second region (1). 6. The high withstand voltage IC according to 1, 3, or 5.

9. The first high-resistance region (51) is formed by providing a ninth region (57) of a trench groove in a part of the second region. 2. A high withstand voltage IC according to claim 1.

10. The high breakdown voltage IC according to claim 2, wherein the second high resistance region is formed by cutting off a part of the fifth region.

11. The device according to claim 2, wherein the second high-resistance region is formed by reducing the diffusion depth of a part of the fifth region. High voltage IC.

12. The second high-resistance region (52) is formed by providing an eleventh region (56) of the second conductivity type in a part of the fifth region (2). Item 6. A high withstand voltage IC according to item 2, 4 or 5.

13. The second high resistance region (52) is formed by providing a twelfth region (58) of a trench groove in a part of the fifth region (2). 6. The high withstand voltage IC according to 4 or 5.

14. The high breakdown voltage IC according to claim 1, wherein the first source region is divided into a plurality of parts.