JPH11243175A - Composite semiconductor device - Google Patents
Composite semiconductor deviceInfo
- Publication number
- JPH11243175A JPH11243175A JP10044078A JP4407898A JPH11243175A JP H11243175 A JPH11243175 A JP H11243175A JP 10044078 A JP10044078 A JP 10044078A JP 4407898 A JP4407898 A JP 4407898A JP H11243175 A JPH11243175 A JP H11243175A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- package
- small
- composite
- composite semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は高密度実装可能な複
合半導体装置に関する。The present invention relates to a composite semiconductor device capable of high-density mounting.
【０００２】[0002]
【従来の技術】従来、半導体装置は、チップを一個づつ
パッケージしており、そのため、実装密度に限界があっ
た。2. Description of the Related Art Conventionally, semiconductor devices have been packaged one chip at a time, and therefore, there has been a limit to the packaging density.
【０００３】そこで、実装密度を高めるために、半導体
素子としての機能を有する複数のチップを単一のパッケ
ージに収納して、１パッケージ当たりの機能を高めて、
実装密度の向上をはかった半導体装置があり、かかるパ
ッケージでは、内部のチップは略同一平面上に併置した
状態で配置されている。Therefore, in order to increase the packaging density, a plurality of chips having a function as a semiconductor element are housed in a single package, and the function per package is enhanced.
There is a semiconductor device for which the mounting density has been improved, and in such a package, the internal chips are arranged side by side on a substantially same plane.
【０００４】[0004]
【発明が解決しようとする課題】ところが、上述した複
数の半導体素子を収納したパッケージでは、パッケージ
内部の半導体素子が平面的に配置されているため、機能
の大きさに対する上記パッケージの平面積が大きくなっ
て実装に要する面積が大きくなり、実装密度を充分に高
めることができなかった。However, in a package containing a plurality of semiconductor elements as described above, since the semiconductor elements inside the package are arranged in a plane, the plane area of the package relative to the size of the function is large. As a result, the area required for mounting is increased, and the mounting density cannot be sufficiently increased.
【０００５】[0005]
【課題を解決するための手段】そこで、本発明では、大
型の半導体装置のパッケージの下面に凹部を形成し、同
凹部に小型の電子部品を挿入・固着して一体に構成した
ことを特徴とする複合半導体装置を提供せんとするもの
である。Accordingly, the present invention is characterized in that a concave portion is formed on the lower surface of a package of a large semiconductor device, and a small electronic component is inserted and fixed in the concave portion to be integrally formed. To provide a composite semiconductor device.
【０００６】また、次のような特徴を併せ有するもので
ある。Further, the present invention has the following features.
【０００７】大型の半導体装置のパッケージの下面に凹
部を形成し、同凹部に小型の半導体装置を挿入・固着し
て一体に構成したこと。A concave portion is formed on the lower surface of a package of a large semiconductor device, and a small semiconductor device is inserted and fixed in the concave portion to be integrally formed.
【０００８】[0008]
【発明の実施の形態】大型の半導体装置の下面に凹部を
形成し、同凹部に小型の半導体装置や、抵抗器等半導体
装置以外の電子部品を収納・固着して、一体の複合半導
体装置を形成することにより、複合半導体装置の機能の
大きさに対する実装基板上に占める面積の割合を小さく
して、実装密度を高めるようにしている。DESCRIPTION OF THE PREFERRED EMBODIMENTS A concave portion is formed on the lower surface of a large semiconductor device, and a small semiconductor device or an electronic component other than the semiconductor device such as a resistor is housed and fixed in the concave portion to form an integrated semiconductor device. By forming, the ratio of the area occupied on the mounting substrate to the size of the function of the composite semiconductor device is reduced, and the mounting density is increased.
【０００９】[0009]
【実施例】本発明の実施例について図面を参照して説明
する。Embodiments of the present invention will be described with reference to the drawings.
【００１０】図１は、本発明に係る複合半導体装置A1の
第１実施例を示しており、この実施例では、同複合半導
体装置A1は、ＱＦＰパッケージ（クヮッド フラット
パッケージ）の大型の半導体装置11と、上記大型の半導
体装置11の下方に配置した小型の半導体装置13とで構成
されている。FIG. 1 shows a first embodiment of a composite semiconductor device A1 according to the present invention. In this embodiment, the composite semiconductor device A1 is a QFP package (quad flat).
A large semiconductor device 11 of a package) and a small semiconductor device 13 disposed below the large semiconductor device 11.
【００１１】大型の半導体装置11と小型の半導体装置13
とは、大きさが異なるだけでほぼ同一構成であるが、そ
れぞれ別個に製造されており、半導体装置としての機能
を有するチップt1,t2 を、それぞれ、ボンデイングワイ
ヤｂを介してリード14,15 に接続し、これらの外周をそ
れぞれ合成樹脂ｒでモールドしてＱＦＰパッケージを形
成している。Large semiconductor device 11 and small semiconductor device 13
Are substantially the same configuration except for the size, but are manufactured separately, and chips t1 and t2 having a function as a semiconductor device are respectively connected to leads 14 and 15 via bonding wires b. The QFP package is formed by connecting them and molding their outer periphery with synthetic resin r.
【００１２】そして、大型の半導体装置11の下面に、下
方から見て略正方形又は略矩形状の凹部12を形成し、同
凹部12にＱＦＰパッケージの小型の半導体装置13を挿入
し、大型の半導体装置11と小型の半導体装置13を固着し
て、一体の複合半導体装置A1を形成している。A substantially square or substantially rectangular concave portion 12 is formed on the lower surface of the large semiconductor device 11 when viewed from below, and a small semiconductor device 13 of a QFP package is inserted into the concave portion 12 to form a large semiconductor device. The device 11 and the small semiconductor device 13 are fixed to form an integrated semiconductor device A1.
【００１３】上述した大型の半導体装置11と小型の半導
体装置13との固着には、接着等の手段があり、要は、上
記固着時に半導体装置11と小型の半導体装置13とに歪み
が生ずるような外力が作用せず、実装時のハンダ付けの
際の温度に耐え得る耐熱性を有する固着手段であれば良
い。The large semiconductor device 11 and the small semiconductor device 13 are fixed to each other by means such as bonding. In other words, the semiconductor device 11 and the small semiconductor device 13 may be distorted during the fixing. Any fixing means may be used as long as it does not exert any external force and has heat resistance enough to withstand the temperature of soldering during mounting.
【００１４】上記のように、大型の半導体装置11の下方
に小型の半導体装置13が位置していることから、各パッ
ケージ内のチップt1,t2 は上下に配置されていることに
なり、更に、大型の半導体装置11のリード14の内側に小
型の半導体装置13のリード15が位置していることにな
る。As described above, since the small semiconductor device 13 is located below the large semiconductor device 11, the chips t1 and t2 in each package are arranged vertically. The leads 15 of the small semiconductor device 13 are located inside the leads 14 of the large semiconductor device 11.
【００１５】したがって、複数の半導体装置を平面的に
配置したものに対してはもちろん、複数のチップを平面
的に配置して単一のパッケージに収納したものに比べ
て、機能に対する複合半導体装置A1の占有面積が小さく
て済み、プリント基板等への実装密度を高めることがで
きる。Therefore, the composite semiconductor device A1 for the function is not only compared to a device in which a plurality of semiconductor devices are arranged in a plane but also a device in which a plurality of chips are arranged in a plane and stored in a single package. Occupies a small area, and the mounting density on a printed circuit board or the like can be increased.
【００１６】また、複合半導体装置A1を外部の回路に接
続する端子としての大型の半導体装置11のリード14の下
端と、小型の半導体装置13のリード15の下端とを、それ
ぞれ、略同一平面上に配置して、プリント基板等への実
装作業を容易にしている。The lower ends of the leads 14 of the large-sized semiconductor device 11 and the lower ends of the leads 15 of the small-sized semiconductor device 13 as terminals for connecting the composite semiconductor device A1 to an external circuit are substantially coplanar. To facilitate mounting on a printed circuit board or the like.
【００１７】図２は、第２実施例の複合半導体装置A2を
示しており、この実施例では、ＱＦＰパッケージの大型
の半導体装置21の下面に、下方から見て略正方形又は略
矩形状の凹部22を複数形成し、各凹部22にＱＦＰパッケ
ージの小型の半導体装置23,23 を挿入し、前記と同様に
接着等の手段で固着して、一体の複合半導体装置A2を形
成しており、大型の半導体装置21の下方に複数の小型の
半導体装置23が位置していることから、各パッケージ内
のチップは上下に配置されていることになり、機能に対
するの複合半導体装置A2占有面積が小さくて済み、プリ
ント基板等への実装密度を高めることができる。FIG. 2 shows a composite semiconductor device A2 according to a second embodiment. In this embodiment, a substantially square or substantially rectangular concave portion as viewed from below is formed on the lower surface of a large semiconductor device 21 of a QFP package. A plurality of small semiconductor devices 23, 23 of a QFP package are inserted into each of the recesses 22 and fixed by means of bonding or the like in the same manner as described above to form an integrated composite semiconductor device A2. Since the plurality of small semiconductor devices 23 are located below the semiconductor device 21, the chips in each package are arranged vertically, and the area occupied by the composite semiconductor device A2 for the function is small. Thus, the mounting density on a printed circuit board or the like can be increased.
【００１８】更に、大型の半導体装置21の端子24の下端
と、小型の半導体装置23のリード25の下端とを、それぞ
れ、略同一平面上に位置させて、プリント基板等に容易
に実装できるようにしている。Further, the lower ends of the terminals 24 of the large-sized semiconductor device 21 and the lower ends of the leads 25 of the small-sized semiconductor device 23 are respectively located on substantially the same plane so that they can be easily mounted on a printed circuit board or the like. I have to.
【００１９】図３は、第３実施例の複合半導体装置A3を
示しており、この実施例では、ＰＬＣＣパッケージ（プ
ラスチック リードレス チップ キャリア パッケー
ジ）の大型の半導体装置31の下面に、下方から見て略正
方形又は略矩形状の凹部32を形成し、同凹部32にＢＧＡ
パッケージ（ボール グリッド アレイ パッケージ）
の小型の半導体装置33を挿入し、接着等の手段で固着し
て、一体の複合半導体装置A3を形成している。FIG. 3 shows a composite semiconductor device A3 according to a third embodiment. In this embodiment, the bottom surface of a large semiconductor device 31 of a PLCC package (plastic leadless chip carrier package) is viewed from below. A substantially square or substantially rectangular recess 32 is formed, and BGA is formed in the recess 32.
Package (Ball Grid Array Package)
The small semiconductor device 33 is inserted and fixed by means such as adhesion to form an integrated semiconductor device A3.
【００２０】したがって、大型の半導体装置31のチップ
と小型の半導体装置33のチップとを上下に配置している
ことになり、機能に対する複合半導体装置A3の占有面積
が小さくて済み、プリント基板等への実装密度を高める
ことができる。Therefore, the chip of the large semiconductor device 31 and the chip of the small semiconductor device 33 are vertically arranged, so that the area occupied by the composite semiconductor device A3 for the function can be small, and the chip can be mounted on a printed circuit board or the like. Mounting density can be increased.
【００２１】更に、大型の半導体装置31の端子34の下端
と、小型の半導体装置33のボール35の下端とを、それぞ
れ、略同一平面上に位置させて、プリント基板等に容易
に実装できるようにしている。Further, the lower ends of the terminals 34 of the large semiconductor device 31 and the lower ends of the balls 35 of the small semiconductor device 33 are respectively positioned on substantially the same plane so that they can be easily mounted on a printed circuit board or the like. I have to.
【００２２】図４は、第４実施例の複合半導体装置A4を
示しており、この実施例では、ＱＦＰパッケージの半導
体装置41の下面に下方から見て略正方形又は略矩形状の
凹部42を形成し、同凹部42にチップ型抵抗器やコンデン
サ等、半導体装置以外の電子部品43を挿入し、接着等の
手段で固着して、一体の複合半導体装置A4を形成してい
る。FIG. 4 shows a composite semiconductor device A4 according to a fourth embodiment. In this embodiment, a substantially square or substantially rectangular recess 42 is formed on the lower surface of a semiconductor device 41 of a QFP package as viewed from below. Then, an electronic component 43 other than the semiconductor device, such as a chip-type resistor and a capacitor, is inserted into the concave portion 42 and fixed by means such as adhesion to form an integrated composite semiconductor device A4.
【００２３】上記のように、半導体装置41のチップと、
電子部品43とを上下に配置しているので、機能に対する
複合半導体装置A4の占有面積が小さくて済み、プリント
基板等への実装密度を高めることができる。As described above, the chip of the semiconductor device 41
Since the electronic component 43 and the electronic component 43 are arranged vertically, the area occupied by the composite semiconductor device A4 for the function can be small, and the mounting density on a printed circuit board or the like can be increased.
【００２４】なお、図４において、電子部品43のリード
45を、プリント基板等のスルーホール等を挿通して裏面
のランドに導通させるために、半導体装置41の端子45よ
りも下方に延出させているが、同電子部品43のリード45
との下端を、半導体装置41の端子45と略同一平面上に位
置させて、プリント基板等に容易に実装できるようにす
ることもできる。In FIG. 4, the leads of the electronic component 43 are shown.
45 extends below the terminal 45 of the semiconductor device 41 in order to pass through a through hole or the like of a printed board or the like to a land on the back surface.
The lower end of the semiconductor device 41 may be positioned on substantially the same plane as the terminal 45 of the semiconductor device 41 so that the terminal can be easily mounted on a printed circuit board or the like.
【００２５】また、図１〜図４で示した以外の半導体装
置若しくは電子部品等との組み合わせも可能であり、要
は、大型の半導体装置の下面に凹部を形成し、同凹部に
小型の半導体装置又は半導体装置以外の電子部品を挿入
・固着することで、実装密度を高めることができ、更
に、これらの端子の下端を同一平面上に位置させること
で、プリント基板等への実装作業を容易にすることがで
きる。Further, a combination with a semiconductor device or an electronic component other than those shown in FIGS. 1 to 4 is also possible. In short, a concave portion is formed on the lower surface of a large semiconductor device, and a small semiconductor device is formed in the concave portion. The mounting density can be increased by inserting and fixing electronic components other than the device or the semiconductor device. Further, by positioning the lower ends of these terminals on the same plane, the mounting work on a printed circuit board or the like is facilitated. Can be
【００２６】更に、前述した複合半導体装置A1,A2,A2,A
4 において、上下に配置したチップt1,t2 、又は、チッ
プと電子部品43との間の浮遊容量や、誘導や、輻射によ
る悪影響を防止するために、大型半導体装置11,21,31,4
1 と小型半導体装置13,23,33又は電子部品43との間に、
上記悪影響を防止するためのシールドを設けることが望
ましく、上記シールドには、例えば、導電性の接着剤を
用いて大型半導体装置11,21,31,41 と小型半導体装置1
3,23,33又は電子部品43とを固着し、同接着剤をグラン
ドに導通させたものや、大型半導体装置11,21,31,41 と
小型半導体装置13,23,33又は電子部品43との間に、グラ
ンドに導通した金属箔を介在させたものがある。Further, the aforementioned composite semiconductor devices A1, A2, A2, A
4, in order to prevent the stray capacitance between the chips t1 and t2 disposed above and below, or the chip and the electronic component 43, and the adverse effects of induction and radiation, the large semiconductor devices 11, 21, 31 and 4
1 and between the small semiconductor device 13, 23, 33 or the electronic component 43,
It is desirable to provide a shield for preventing the above-mentioned adverse effects. For example, the shield is made of a large semiconductor device 11, 21, 31, 41 and a small semiconductor device 1 using a conductive adhesive.
3, 23, 33 or the electronic component 43, and the adhesive is conducted to the ground, or the large semiconductor device 11, 21, 31, 41 and the small semiconductor device 13, 23, 33 or the electronic component 43 In some cases, a metal foil connected to the ground is interposed.
【００２７】[0027]
【発明の効果】本発明によれば次のような効果を得るこ
とができる。According to the present invention, the following effects can be obtained.
【００２８】請求項１記載の発明では、大型の半導体装
置のパッケージの下面に凹部を形成し、同凹部に小型の
電子部品を挿入・固着して、一体の複合半導体装置を構
成したことによって、複合半導体装置の機能の大きさに
比較して占有面積を小さくでき、実装密度を高めること
ができる。According to the first aspect of the present invention, a concave portion is formed in the lower surface of the package of the large semiconductor device, and a small electronic component is inserted and fixed in the concave portion to form an integrated semiconductor device. The occupied area can be reduced as compared with the size of the function of the composite semiconductor device, and the mounting density can be increased.
【００２９】請求項２記載の発明では、大型の半導体装
置のパッケージの下面に凹部を形成し、同凹部に小型の
半導体装置を挿入・固着して、一体の複合半導体装置を
構成したことによって、複合半導体装置の機能に対する
占有面積が小さくなり、実装密度を高めることができ
る。According to the second aspect of the present invention, a concave portion is formed in the lower surface of the package of the large semiconductor device, and the small semiconductor device is inserted and fixed in the concave portion to form an integrated semiconductor device. The area occupied by the functions of the composite semiconductor device is reduced, and the mounting density can be increased.
【図１】本発明に係る複合半導体装置の断面説明図（第
１実施例）。FIG. 1 is an explanatory cross-sectional view of a composite semiconductor device according to the present invention (first embodiment).
【図２】本発明に係る複合半導体装置の断面説明図（第
２実施例）。FIG. 2 is an explanatory cross-sectional view of a composite semiconductor device according to the present invention (second embodiment).
【図３】本発明に係る複合半導体装置の断面説明図（第
３実施例）。FIG. 3 is an explanatory sectional view of a composite semiconductor device according to the present invention (third embodiment);
【図４】本発明に係る複合半導体装置の断面説明図（第
４実施例）。FIG. 4 is an explanatory sectional view of a composite semiconductor device according to the present invention (fourth embodiment).
A1,A2,A3,A4 複合半導体装置 11,21,31,41 大型の半導体装置 13,23,33 小型の半導体装置 43 電子部品 A1, A2, A3, A4 Composite semiconductor device 11,21,31,41 Large semiconductor device 13,23,33 Small semiconductor device 43 Electronic components
Claims (2)
凹部を形成し、同凹部に小型の電子部品を挿入・固着し
て一体に構成したことを特徴とする複合半導体装置。1. A composite semiconductor device, wherein a concave portion is formed on a lower surface of a package of a large semiconductor device, and a small electronic component is inserted and fixed into the concave portion to form an integrated structure.
部を形成し、同凹部に小型の半導体装置を挿入・固着し
て一体に構成したことを特徴とする複合半導体装置。2. A composite semiconductor device, wherein a concave portion is formed on a lower surface of a package of a large semiconductor device, and a small semiconductor device is inserted and fixed in the concave portion to be integrated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10044078A JPH11243175A (en) | 1998-02-25 | 1998-02-25 | Composite semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10044078A JPH11243175A (en) | 1998-02-25 | 1998-02-25 | Composite semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11243175A true JPH11243175A (en) | 1999-09-07 |
Family
ID=12681599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10044078A Pending JPH11243175A (en) | 1998-02-25 | 1998-02-25 | Composite semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11243175A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010058586A (en) * | 1999-12-30 | 2001-07-06 | 마이클 디. 오브라이언 | semiconductor package and mounting method using it |
| KR20030001032A (en) * | 2001-06-28 | 2003-01-06 | 동부전자 주식회사 | Mount structure of multi stack type package |
| KR20030057186A (en) * | 2001-12-28 | 2003-07-04 | 동부전자 주식회사 | semiconductor package and its manufacturing method |
| JP2004363126A (en) * | 2003-05-30 | 2004-12-24 | Seiko Epson Corp | Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device |
| JP2005539403A (en) * | 2002-09-17 | 2005-12-22 | チップパック，インク． | Semiconductor multi-package module having wire bond interconnections between stacked packages |
| JP2006502596A (en) * | 2002-10-08 | 2006-01-19 | チップパック，インク． | Stacked semiconductor multi-package module with second package turned upside down |
| KR100646474B1 (en) * | 2000-03-25 | 2006-11-14 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and manufacturing method |
| US7638363B2 (en) | 2002-09-17 | 2009-12-29 | Chippac, Inc. | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
| US7682873B2 (en) | 2002-09-17 | 2010-03-23 | Chippac, Inc. | Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages |
| US7732254B2 (en) | 2002-09-17 | 2010-06-08 | Chippac, Inc. | Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages |
| US8143100B2 (en) | 2002-09-17 | 2012-03-27 | Chippac, Inc. | Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages |
-
1998
- 1998-02-25 JP JP10044078A patent/JPH11243175A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010058586A (en) * | 1999-12-30 | 2001-07-06 | 마이클 디. 오브라이언 | semiconductor package and mounting method using it |
| KR100646474B1 (en) * | 2000-03-25 | 2006-11-14 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and manufacturing method |
| KR20030001032A (en) * | 2001-06-28 | 2003-01-06 | 동부전자 주식회사 | Mount structure of multi stack type package |
| KR20030057186A (en) * | 2001-12-28 | 2003-07-04 | 동부전자 주식회사 | semiconductor package and its manufacturing method |
| JP2005539403A (en) * | 2002-09-17 | 2005-12-22 | チップパック，インク． | Semiconductor multi-package module having wire bond interconnections between stacked packages |
| US7638363B2 (en) | 2002-09-17 | 2009-12-29 | Chippac, Inc. | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
| US7682873B2 (en) | 2002-09-17 | 2010-03-23 | Chippac, Inc. | Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages |
| US7732254B2 (en) | 2002-09-17 | 2010-06-08 | Chippac, Inc. | Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages |
| US8143100B2 (en) | 2002-09-17 | 2012-03-27 | Chippac, Inc. | Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages |
| JP2006502596A (en) * | 2002-10-08 | 2006-01-19 | チップパック，インク． | Stacked semiconductor multi-package module with second package turned upside down |
| JP2004363126A (en) * | 2003-05-30 | 2004-12-24 | Seiko Epson Corp | Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device |
| US7436061B2 (en) | 2003-05-30 | 2008-10-14 | Seiko Epson Corporation | Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device |
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