JPH11249614A - Driving circuit for matrix type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the driving circuit of a matrix type dislay device which is capable of preventing the reduction of luminance due to saturations of phosphers and also is capable of making secular changes of cells smaller. SOLUTION: In a display panel 10, cells are arranged in a matrix shape. A video signal is delayed by one or more rows by a data multiphase making circuit 50 and video signals before and after delays are swictched in one field. Rows scanning the display panel 10 are switched by switching scanning pulses to be outputted from a shift register 9 by a scan multiphase making circuit 60. Thus, respective rows of cells are made to be scanned by being dispersed in display periods of (n) times in one field and other rows are made to be scanned for non-display periods among the display periods of the (n) times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a matrix type display device such as a display device using an electron emission source such as a cold cathode electron emission device or an electroluminescence (hereinafter abbreviated as EL) display device. .

[0002]

2. Description of the Related Art As a matrix type display device, a one-row simultaneous display type display device such as a display device using a cold cathode electron-emitting device or an EL display device is known. In a one-row simultaneous display type display device, display is performed simultaneously in one-row units, and generally, line-scanning is performed from top to bottom, and display of each row is performed simultaneously for all columns during a scanning period.

[0003] More specifically, the one-line simultaneous display type is a display device in which when an arbitrary line is displayed, another line is not displayed. For example, a plasma display panel, a TFT liquid crystal display device, and the like perform line-sequential driving. However, this is not the case because a cell has a memory function and a plurality of rows are displayed simultaneously. However,
When the display device is completely divided into a plurality of wiring blocks, if there is no simultaneous display period of a plurality of rows in each block, the display device is a one-row simultaneous display type display device.

FIG. 7 is a block diagram showing a driving circuit of a conventional one-row simultaneous display type matrix type display device. 7, a display panel 10 is a display panel using, for example, cold cathode electron-emitting devices. As an example, as shown in FIG. 8, a plurality of row wirings connected to scanning electrodes L1 to LM and data electrodes D1 to D1 are provided. The cells 10s forming the pixels are arranged in a matrix by a plurality of column wirings connected to the DN. The cell 10s includes an electron-emitting device that is an electron-emitting source and a phosphor that receives electron irradiation from the electron-emitting device.

[0005] The video signal input to the terminal 1 is written to the shift register 2. 1 in shift register 2
After the data for the row is written, the data is latched by the latch circuit 3, and the data is input to the modulation circuit 4. The modulation circuit 4 outputs pulses corresponding to the magnitude of the data to the display panel 10.
To the data electrodes D1 to DN.

[0006] The synchronization signal input to the terminal 7 is input to the timing control circuit 8. The timing control circuit 8 supplies a shift clock to the shift register 2 and a latch clock to the latch circuit 3. The timing control circuit 8 also supplies a pulse of one line width to the shift register 9. The shift register 9 sequentially inputs the pulses as scan pulses to the scan electrodes L1 to LM of the display panel 10 from the first row.

Further, the operation when driving the matrix type display device shown in FIG. 7 will be described in detail. As described above, the scan pulse is sequentially applied to the scan electrodes L1 to LM of the display panel 10 by the shift register 9. As an example, a pulse that has been subjected to pulse width (PWM) modulation by the modulation circuit 4 according to data corresponding to the selected line is applied to the data electrodes D1 to DN of the display panel 10.

That is, a voltage is applied to the data electrode Dj for the data in the i-th row and the j-th column while the scanning electrode Li is selected. When the modulation circuit 4 performs PWM modulation, the gradation is
It is represented by the application time (pulse width) of the pulse applied to the data electrodes D1 to DN. The modulation method of the modulation circuit 4 is PWM.
The method is not limited to the method, and any method that can express the intensity of light emission such as voltage modulation may be used.

FIG. 9 is a waveform diagram showing an operation for displaying the j-th column as an example, and shows a scan pulse applied to the scan electrode and a pulse applied to the data electrode.
Here, a case is shown in which the video signal is black at the i-th row and j-th column, gray at the i + 1-th row and the j-th column, and white at the i + 2 row and the j-th column. As shown in FIG. 9, in the horizontal scanning period H0 of the i-th row, the voltage −Vs is applied to the scan electrode Li of the i-th row, and no voltage is applied to the other scan electrodes. At this time, since the display in the i-th row and the j-th column is black, the data electrode Dj in the j-th column is always at the 0 potential.

Next, in the horizontal scanning period H1 of the (i + 1) -th row, the voltage -Vs is applied to the scanning electrode L (i + 1) of the (i + 1) -th row.
And no voltage is applied to the other scan electrodes. At this time, since the display in the (i + 1) -th row and the j-th column is gray, the voltage + Vd is applied to the data electrode Dj in the j-th column only for about a half of the horizontal scanning period H1, and the potential is 0 in the subsequent half. . Further, in the horizontal scanning period H2 of the i + 2 row, the voltage −Vs is applied to the scan electrodes L (i + 2) of the i + 2 row, and no voltage is applied to the other scan electrodes. At this time, since the display at the (i + 2) row and the jth column is white, the voltage + Vd is applied to the data electrode Dj at the jth column during the entire horizontal scanning period H2.

Meanwhile, in the case of the display panel 10 using the cold cathode electron emitting device, the electron emitting device has a threshold value for emitting electrons. Then, the scanning electrodes L1 to L
When the difference between the voltage applied to M and the voltage applied to the data electrodes D1 to DN is equal to or larger than the threshold value, the display state is set. In this example, both the voltage Vd and the voltage Vs are smaller than the threshold value Vth, and the voltage (Vd + Vs)
Is set to be larger than the threshold value Vth. That is, light emission does not occur only when a voltage is applied to only one of the data electrodes D1 to DN and the scan electrodes L1 to LM, and light is emitted only when both are applied.

Here, only the display process from the i-th row to the (i + 2) -th row has been described.
0 scanning electrodes L1 to LM are sequentially arranged from row 1 to row M.
A scan pulse is applied, and a PWM-modulated pulse is applied to the data electrodes D1 to DN in accordance with the scan timing. In the case of displaying 480 rows × 640 columns of effective pixels, 480 scanning electrodes and 6 data electrodes are used.
There are 40 data electrodes and 1920 data electrodes in the case of color display of the RGB stripe structure.

With the above configuration and operation, the display timing of each row in one field is as shown in FIG. Here, the case where the scanning electrodes are 480 rows is shown, and a portion indicated by a thick solid line is a display period. FIG.
As shown in (1), display is performed sequentially from the first line to the 480th line in one field.

[0014]

In the above-described one-row simultaneous display type matrix display device, one row is used for each row.
The display is concentrated only in one horizontal scanning period in the field.
For this reason, a change with time (burn-in) occurs in the electron-emitting device and the phosphor (that is, the cell 10s) due to the continuous electron emission. Also, due to the saturation phenomenon of the phosphor, the pulse width (emission time) and the luminance (emission intensity) do not become proportional to each other.
As shown in FIG. 1, having a gentle gamma characteristic causes a decrease in luminance efficiency. Incidentally, when the pulse width x, the emission intensity and y, characteristics shown in FIG. 11 can be expressed as y = x ^r, with 0 <r <1, typically, 0.7 <r <0.
It is about 9.

[0015] The light emission of the phosphor is such that, when electrons existing in the phosphor are excited to a higher level by irradiation of an electron beam, the energy of the difference is emitted as visible light when returning to the original level. It is. If electrons are radiated one after another before the excited state of the phosphor is restored, the ratio of emission of visible light to the amount of irradiated electrons decreases. This is called phosphor saturation. Having the gamma characteristic as shown in FIG. 11 due to the saturation phenomenon of the phosphor means that the luminance does not double even if the pulse width is doubled. Luminance reduction was a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a matrix type display device which can prevent a decrease in luminance due to saturation of a phosphor and can reduce a change with time in cells. It is an object to provide a driving circuit.

[0017]

According to the present invention, there is provided a display panel in which cells are arranged in a matrix by a plurality of rows and a plurality of columns. Scan and display line by line,
Further, in a driving circuit of a matrix type display device which performs display so that display periods in a plurality of rows are not overlapped with each other, each row of the cell is n times in one field (where n is an integer of 3 or more). A driving circuit for a matrix-type display device, characterized in that the driving circuit is provided with means for scanning while being dispersed in a display period.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a driving circuit of a matrix type display device according to the present invention will be described with reference to the accompanying drawings. 1 and 2 are block diagrams showing first and second embodiments of a driving circuit of a matrix type display device of the present invention, respectively. FIG. 3 is an operation of the first embodiment of a driving circuit of a matrix type display device of the present invention. FIG. 4 is a diagram for explaining display timing according to the first embodiment of the drive circuit of the matrix type display device of the present invention, and FIG. 5 is a diagram of the drive circuit of the matrix type display device of the present invention. FIG. 6 is a waveform diagram for explaining the operation of the second embodiment, and FIG. 6 is a diagram for explaining display timing according to the second embodiment of the drive circuit of the matrix type display device of the present invention. 1 and 2, the same parts as those in FIG. 7 are denoted by the same reference numerals.

<First Embodiment> In FIG. 1, a display panel 10 is a display panel using, for example, cold cathode electron-emitting devices, and the specific configuration is as described with reference to FIG. The video signal input to the terminal 1 is transmitted to the shift register 2
Is written to. After one row of data is written in the shift register 2, the data is latched by the latch circuit 3. The data output from the latch circuit 3 is input to a data multiphase circuit 50 newly added according to the present invention. In the present embodiment, the data multi-phase conversion circuit 50 converts data into four phases, for example.

The data multi-phase circuit 50 is connected to the display panel 10.
D flip-flops (hereinafter abbreviated as DFFs) 551 to 55N provided according to the number of data electrodes
Similarly, four contact switches 561 to 56 including contacts a to d provided according to the number of data electrodes of the display panel 10
N. Contact a of switches 561 to 56N
Receives the output of the latch circuit 3 and switches 561 to
The contacts b to d of 56N have DFFs 551 to 5 respectively.
5N first to third stage DFF outputs are input. The switches 561 to 56N selectively output these. The data output from the data polyphase circuit 50 is input to the modulation circuit 4. Modulation circuit 4
Inputs, for example, a PWM-modulated pulse to the data electrodes D1 to DN of the display panel 10 according to the magnitude of the data.

The synchronization signal input to the terminal 7 is input to the timing control circuit 8. The timing control circuit 8 supplies a shift clock to the shift register 2 and a latch clock to the latch circuit 3. The timing control circuit 8 also supplies a pulse of one line width to the shift register 9. The shift register 9 inputs the pulse to the scan polyphase circuit 60 newly added according to the present invention. The scan polyphasing circuit 60 multiplies the input pulse as described later and inputs the pulse to the scan electrodes L1 to LM of the display panel 10 as a scan pulse.
In the present embodiment, the scan multi-phase circuit 50 converts the scan pulse into four phases, for example. Therefore, the scan pulse supplied to the display panel 10 is
The output pulse of one line width is divided into four.

The scan multi-phase circuit 60 is connected to the display panel 1.
Four contacts a to d provided according to the number of scanning electrodes of zero
It is composed of contact switches 621 to 62M. The four adjacent outputs of the shift register 9 are input to the switches 621 to 62M, respectively, and these are selectively output. Therefore, the number of output terminal stages of the shift register 9 is three more than in FIG. That is, if there are M rows, there are M + 3 stages. The scan pulses output from the switches 621 to 62M are input to the scan electrodes L1 to LM of the display panel 10. The timing control circuit 8
Further, the switches 561 to 56 of the data polyphase circuit 50
N and switches 621 to 62 of scan multiphase circuit 60
Control to switch M.

Here, the operation of the drive circuit shown in FIG.
This will be described in detail with reference to FIG. FIG. 3 also shows an operation when displaying the j-th column as an example, and shows a scan pulse applied to the scan electrode and a pulse applied to the data electrode. Here, the video signal is white on the i-3 row and j column, black on the i-2 row and j column, gray on the i-1 row and j column, i-row j
Column is white, i + 1 row and j column is black, i + 2 row and j column is gray, i
+3 rows and j columns show the case of white.

When the shift register 9 outputs a scan pulse from the i-th terminal, the latch circuit 3 outputs i
All data on the line are output at the same time. At this time, the switches 561 to 56N and 621 to 62M of the data polyphase conversion circuit 50 and the scan polyphase conversion circuit 60 are controlled by the control signal from the timing control circuit 8 to perform the horizontal scanning period H0.
In the first quarter period H0a, the contact is connected to the contact a, in the next quarter period H0b, the contact b is connected, and in the next quarter period H0c, the contact is connected to the contact c. 1 /
In the period H0d of 4, the connection is controlled to be connected to the contact d.

Switches 561-56N, 621-62M
Are the first 1 / of the horizontal scanning period H0 connected to the contact point a.
In the period H0a of 4, the data polyphase circuit 50 outputs the output from the latch circuit 3 as it is, so that the data in the i-th row is input to the modulation circuit 4. Further, a scan pulse from the i-th terminal of the shift register 9 is applied to the scan electrode Li on the i-th row of the display panel 10.

Switches 561-56N, 621-62M
Is the next 1/4 of the horizontal scanning period H0 in which
In the period H0b, the data polyphase conversion circuit 50
Since the output of the first stage DFF of 1 to 55N is output, i
The data in the -1st row is input to the modulation circuit 4. The scan pulse from the ith terminal of the shift register 9 is applied to the scan electrode L of the (i-1) th row of the display panel 10.
(I-1).

Switches 561-56N, 621-62M
Is connected to the contact point c, in the next quarter period H0c of the horizontal scanning period H0, the data polyphase circuit 50
Since the outputs of the second stage DFFs of F551 to 55N are output, the data in the (i-2) th row is input to the modulation circuit 4. The scan pulse from the i-th terminal of the shift register 9 is applied to the scan electrode L (i-2) on the (i-2) th row of the display panel 10.

Switches 561-56N, 621-62M
Is the last 1 / of the horizontal scanning period H0 connected to the contact d.
In the period H0d, the data polyphase conversion circuit 50
Since the output of the third stage DFF of 51 to 55N is output,
The data in the (i-3) th row is input to the modulation circuit 4. Also, the scan pulse from the i-th terminal of the shift register 9 is applied to the scan electrode L of the (i-3) th row of the display panel 10.
(I-3).

That is, the first quarter of one horizontal scanning period H0
In the period H0a, the scan of the i-th row of the display panel 10 is performed, and in the next quarter H0b, the display panel 1 is scanned.
The scan of the (i-1) th row of 0 is performed. The next 1 /
In the fourth period H0c, the scan on the (i-2) th row of the display panel 10 is performed, and in the last 期間 period H0d, the i-th row is scanned.
The scanning of the third row is performed.

Then, in the next horizontal scanning period H1, scanning shifts to the (i + 1) th terminal in the shift register 9, and the data of the (i + 1) th row is output from the latch circuit 3. Here, the switches 561 to 56N and 621 to 62M of the data polyphase circuit 50 and the scan polyphase circuit 60 are controlled by the control signal from the timing control circuit 8.
In the first quarter period H1a of the horizontal scanning period H1, it is connected to the contact a, in the next quarter period H1b it is connected to the contact b, and in the next quarter period H1c it is connected to the contact c. Then, in the last quarter period H1d, control is performed so as to connect to the contact point d.

Switches 561-56N, 621-62M
Are the first 1 / of the horizontal scanning period H1 connected to the contact point a.
In the period H1a of 4, the data polyphase conversion circuit 50 outputs the output from the latch circuit 3 as it is, so that the data in the (i + 1) th row is input to the modulation circuit 4. Further, the scan pulse from the (i + 1) th terminal of the shift register 9 is applied to the (i + 1) th scan electrode L (i +
1).

Switches 561-56N, 621-62M
Is the next ４ of the horizontal scanning period H1 connected to the contact b.
In the period H1b, the data polyphase conversion circuit 50
Since the output of the first stage DFF of 1 to 55N is output, i
The data in the row is input to the modulation circuit 4. In addition, the scan pulse from the (i + 1) th terminal of the shift register 9 is applied to the scan electrode Li on the i-th row of the display panel 10.

Switches 561-56N, 621-62M
Are connected to the contact point c, in the next quarter period H1c of the horizontal scanning period H1, the data polyphase circuit 50
Since the outputs of the DFFs in the second stage of F551 to 55N are output, the data in the (i-1) th row is input to the modulation circuit 4. Also, the scan pulse from the (i + 1) th terminal of the shift register 9 is applied to the scan electrode L (i-1) on the (i-1) th row of the display panel 10.

Switches 561-56N, 621-62M
Last 1 / of the horizontal scanning period H1 connected to the contact d.
In the period H1d, the data multi-phase conversion circuit 50 outputs the DFF5
Since the output of the third stage DFF of 51 to 55N is output,
The data in the (i-2) th row is input to the modulation circuit 4. Further, the scan pulse from the (i + 1) th terminal of the shift register 9 is applied to the scan electrode L (i-2) on the (i-2) th row of the display panel 10.

That is, the first quarter of one horizontal scanning period H1
In the period H1a, the scan of the (i + 1) th row of the display panel 10 is performed, and in the next quarter period H1b, the scan of the i-th row of the display panel 10 is performed. The next 1 /
In the period H1c of period 4, the scan of the (i-1) -th row of the display panel 10 is performed.
The scanning of the second row is performed.

Hereinafter, the same processing is repeated in the horizontal scanning periods H2, H3,.

Thus, for example, for the display of the i-th row, the first 1/4 period H0a of the horizontal scanning period H0 during which the shift register 9 performs the i-th scan,
The second 1/4 period H1b of the horizontal scanning period H1 during which the shift register 9 performs the (i + 1) -th scan, and the third 1/1 period of the horizontal scanning period H2 during which the shift register 9 performs the (i + 2) -th scan. 4 and H3d, which is the last quarter of the horizontal scanning period H3 during which the shift register 9 performs the (i + 3) th scanning. These series of processes are similarly performed on all rows.

As described above, according to the driving circuit of the present invention, one row of the display panel 10 is displayed four times. Therefore, if one horizontal scanning period (1H) is divided into quarters, the pulse width for one PWM modulation by the modulation circuit 4 is 1/4 as compared with FIG.
The pulse width of the scan pulse applied to the 0 scan electrodes L1 to LM is also １ ／ of that in FIG. Note that 100
When% white is displayed (255 data in 8-bit representation), the pulse width of the PWM modulation from the modulation circuit 4 is substantially equal to the scan pulse width.

In the example of FIG. 3, the i-3th row is 100%
(White), the i-2th row is 0 (black), the i-1th row is 50%
(Gray), i-th row is 100% (white), i + 1-th row is 0
(Black), the i + 2 line is 50% (gray), and the i + 3 line is 100% (white), so the output from the modulation circuit 4 is
The first 1/4 period H0a of the horizontal scanning period H0 is a pulse having a scan pulse width, the next 1/4 period H0b is a pulse having a half (1/8 of 1H) the scan pulse width, and the next 1/4 period. Period H0c is always 0, and the last 1/4 period H
0d is a pulse having a scan pulse width.

In the next horizontal scanning period H1, the output from the modulation circuit 4 is the first H period 水平 of the horizontal scanning period H1.
1a is always 0, the next ４ period H1b is a pulse of the scan pulse width, the next 期間 period H1c is a pulse of half the scan pulse width (１ ／ of 1H), and the last 1
The pulse H1d is always 0 during the period / 4.

As shown in the i-th row in this example, even if 100% of the data is input, the display is performed in the periods H0a and H1.
Since b, H2c, and H3d are dispersed four times, and the pulse width of one pulse can be reduced to 1/4 of 1H at the maximum, the burn-in phenomenon of the cell 10s can be reduced. In addition, by dispersing four times, a non-display period is provided between the four displays. Therefore, the excitation state of the phosphor is stopped by the pause in the non-display period, and the phosphor is restored to the initial state. Therefore, four times the luminance can be obtained with four pulses, and a decrease in luminance due to the saturation of the phosphor is prevented. Can be.

In the present embodiment, an example has been shown in which one row of the display panel 10 is displayed while being distributed over four display periods.
The number is not limited to four, but may be three or five. When the horizontal scanning period is divided into n (n is an integer of 3 or more), the DFFs 551 to 55 in the data polyphase circuit 50 are used.
The number of stages of N is n−1, the switches 561 to 56N are n contacts, and the scan polyphase circuit 60 switch 62
1 to 62M are n contacts.

The mitigation of the decrease in the saturation of the phosphor by dispersing n times can be explained as follows. When the emission intensity (y) is proportional to the pulse width (x) to the power of r, y = x
^r . However, if the pulse is divided into n and the phosphor is completely recovered during the non-display period (pause period) as in the present invention, the emission intensity is n · (x / n) ^r .
Therefore, the effect of the n division is n · (x / n) ^r / x ^r = n · (1 / n) ^r .

If the relationship between the pulse width x and the light emission intensity y has a gamma characteristic proportional to the 0.9 power, the luminance is increased by about 15% in the case of four divisions (n = 4). Becomes In the case of 32 divisions (n = 32), the luminance increases by about 41%. Further, in the case of being proportional to the 0.8th power, the luminance increases by about 32% in the 4-split display, and 100% in the 32-split display.
% Increase in luminance. The cell 10 of the display panel 10
Since the current supplied to s is the same as that of the related art, the luminance efficiency increases by this luminance increase. Note that, as can be understood from the above description, it is more effective that the pulse division is as evenly distributed as possible.

FIG. 4 is a block diagram showing a configuration according to the configuration of FIG. 1 described above.
This is the display timing of each line in the field. As shown in FIG. 4, the display of each row is divided into four with a non-display period having a width of 1H, and in this non-display period, display is performed for each quarter of the other four rows in this display period. I have.
As can be seen from FIG. 4, also in the present invention, the display periods of a plurality of rows do not overlap each other, and the display is performed in units of one row. In this embodiment, the non-display periods are all set to a fixed time, but are not limited to the fixed time.

<Second Embodiment> In FIG. 2, the display panel 10 is, for example, a display panel using cold cathode electron-emitting devices, and the specific configuration is as described with reference to FIG. The video signal input to the terminal 1 is transmitted to the shift register 2
Is written to. After one row of data is written in the shift register 2, the data is latched by the latch circuit 3. The data output from the latch circuit 3 is input to a data multiphase circuit 51 newly added according to the present invention.

The data multi-phase circuit 51 is connected to the display panel 10.
D flip-flops (hereinafter abbreviated as DFFs) 571 to 57N provided in accordance with the number of data electrodes, and two contacts a and b provided also in accordance with the number of data electrodes of the display panel 10. It comprises switches 581-58N. The outputs of the latch circuit 3 and the outputs of the DFFs 571 to 57N are input to the switches 581 to 58N.
These are selectively output. The data output from the data polyphase circuit 51 is input to the modulation circuit 4. The modulation circuit 4 inputs, for example, a PWM-modulated pulse to the data electrodes D1 to DN of the display panel 10 according to the magnitude of the data.

The synchronization signal input to the terminal 7 is input to the timing control circuit 8. The timing control circuit 8 supplies a shift clock to the shift register 2 and a latch clock to the latch circuit 3. The timing control circuit 8 also supplies a pulse of one line width to the shift register 9. The shift register 9 inputs the pulse to the scan polyphase circuit 61 newly added according to the present invention. The scan polyphasing circuit 61 multiplies the input pulse as described later and inputs the pulse to the scan electrodes L1 to LM of the display panel 10 as a scan pulse.
In this embodiment, the scan multi-phase circuit 51 converts a scan pulse into four phases, for example. Therefore, the scan pulse supplied to the display panel 10 is
The output pulse of one line width is divided into four.

The scan multi-phase circuit 61 is connected to the display panel 1.
Contact points a and b provided according to the number of scanning electrodes of 0
It is composed of contact switches 631-63M. Two adjacent outputs of the shift register 9 are input to the switches 631 to 63M, respectively, and these are selectively output. Therefore, the number of output terminal stages of the shift register 9 is one more than in the conventional FIG. That is, if there are M rows, there are M + 1 stages. The scan pulses output from the switches 631 to 63M are input to the scan electrodes L1 to LM of the display panel 10. The timing control circuit 8
Further, the switches 581 to 58 of the data polyphase conversion circuit 51
N and switches 631 to 63 of scan polyphase circuit 61
Control to switch M.

Here, the operation of the drive circuit shown in FIG.
This will be described in detail with reference to FIG. FIG. 5 also shows an operation when displaying the j-th column as an example, and shows a scan pulse applied to the scan electrode and a pulse applied to the data electrode. Here, the video signal is gray in the i-1 row and j column, white in the i row and j column, black in the i + 1 row and j column, and i + 2 row j
The column is gray and the i + 3 row and j column are white.

When the shift register 9 is outputting a scan pulse from the ith terminal, the latch circuit 3 outputs
All data on the line are output at the same time. At this time, the switches 581 to 58N and 631 to 63M of the data multi-phase circuit 51 and the scan multi-phase circuit 61 are controlled by the control signal from the timing control circuit 8 so that the horizontal scanning period H0
Is connected to the contact a in the first quarter period H0a, is connected to the contact b in the next quarter period H0b, and is further connected to the contact a in the next quarter period H0c. 1 /
In the period H0d of 4, the connection is controlled to be connected to the contact b.

Switches 581-58N, 631-63M
Are the first 1 / of the horizontal scanning period H0 connected to the contact point a.
In the fourth period H0a and the third quarter period H0c, the data polyphase conversion circuit 51 outputs the output from the latch circuit 3 as it is, so that the data in the i-th row is input to the modulation circuit 4. Become. Further, a scan pulse from the i-th terminal of the shift register 9 is applied to the scan electrode Li on the i-th row of the display panel 10.

Switches 581-58N, 631-63M
Is the second 1 in the horizontal scanning period H0 connected to the contact b.
In the period H0b of / 4 and the last period H0d of １ ／, the data polyphase conversion circuit 51 outputs the outputs of the DFFs 571 to 57N. Become. Further, the scan pulse from the i-th terminal of the shift register 9 is applied to the scan electrode L (i-1) on the (i-1) th row of the display panel 10.

That is, the first quarter of one horizontal scanning period H0
In the period H0a and the third quarter period H0c, the scan of the i-th row of the display panel 10 is performed, and the second
In the period H0b of 4 and the last period H0d of 1/4, scanning of the (i-1) th row of the display panel 10 is performed.

Then, in the next horizontal scanning period H1, scanning shifts to the (i + 1) th terminal in the shift register 9, and the data of the (i + 1) th row is output from the latch circuit 3. Also in this case, the switches 581 to 58N and 631 to 63M of the data polyphase circuit 51 and the scan polyphase circuit 61 are controlled by the control signal from the timing control circuit 8.
In the first 期間 period H1a and the third 期間 period H1c of the horizontal scanning period H1, it is connected to the contact a, and the second 1
In the period H1b of and the last period H1d of ４, control is performed to connect to the contact point b.

Switches 581-58N, 631-63M
Are the first 1 / of the horizontal scanning period H1 connected to the contact point a.
In the fourth period H1a and the third quarter period H1c, the data polyphase conversion circuit 51 outputs the output from the latch circuit 3 as it is, so that the data in the (i + 1) th row is input to the modulation circuit 4. Become. Also, i + 1 of the shift register 9
The scan pulse from the terminal is
This is applied to the (+1) th row scanning electrode Li.

Switches 581-58N, 631-63M
Is the second 1 in the horizontal scanning period H1 connected to the contact b.
In the period H1b of and the last period H1d of １ ／, the data polyphase conversion circuit 51 outputs the outputs of the DFFs 571 to 57N, so that the data in the i-th row is input to the modulation circuit 4. In addition, the scan pulse from the (i + 1) th terminal of the shift register 9 is applied to the scan electrode Li on the i-th row of the display panel 10.

That is, the first quarter of one horizontal scanning period H1
In the period H1a and the third quarter period H1c, the scan of the (i + 1) th row of the display panel 10 is performed. In the second quarter period H1b and the last quarter period H1d,
The i-th row of the display panel 10 is scanned.

Thereafter, the same processing is repeated in the horizontal scanning periods H2, H3,.

In this way, for example, for the display of the i-th row, the first 1/4 period H0a and the third 1/4 of the horizontal scanning period H0 during which the shift register 9 performs the i-th scan are performed. During the period H0c, the shift register 9
2 in the horizontal scanning period H1 in which the + 1st scan is being performed
The first quarter period H1b and the last quarter period H1
This is performed four times with d. These series of processes are similarly performed on all rows.

As described above, according to the driving circuit of the present invention, one row of the display panel 10 is displayed four times. Therefore, if one horizontal scanning period (1H) is divided into quarters, the pulse width for one PWM modulation by the modulation circuit 4 is 1/4 as compared with FIG.
The pulse width of the scan pulse applied to the 0 scan electrodes L1 to LM is also １ ／ of that in FIG. Note that 100
When% white is displayed (255 data in 8-bit representation), the pulse width of the PWM modulation from the modulation circuit 4 is substantially equal to the scan pulse width.

In the example of FIG. 5, the (i-1) -th row is 50% (gray), the i-th row is 100% (white), and the (i + 1) -th row is 0.
(Black), the i + 2 line is 50% (gray), and the i + 3 line is 100% (white), so the output from the modulation circuit 4 is
The first 1/4 period H0a of the horizontal scanning period H0 is a pulse having a scan pulse width, the next 1/4 period H0b is a pulse having a half (1/8 of 1H) the scan pulse width, and the next 1/4 period. Period H0c is a pulse having a scan pulse width, and the last quarter period H0d is a half (1) of the scan pulse width.
H (１ ／ of H).

In the next horizontal scanning period H1, the output from the modulation circuit 4 is the first 1/4 period H of the horizontal scanning period H1.
1a is always 0, the next 期間 period H1b is a pulse having a scan pulse width, the next 期間 period H1c is always 0, and the last 期間 period H1d is a scan pulse width pulse.

As shown in the i-th row in this example, even if 100% of the data is input, the display is performed during the periods H0a, H0.
Since the pulse width is divided into four times c, H1b, and H1d, and the pulse width for one time can be reduced to 1/4 of 1H at the maximum, the burn-in phenomenon of the cell 10s can be reduced. In addition, by dispersing four times, a non-display period is provided between the four displays. Therefore, the excitation state of the phosphor is stopped by the pause in the non-display period, and the phosphor is restored to the initial state. Therefore, four times the luminance can be obtained with four pulses, and a decrease in luminance due to the saturation of the phosphor is prevented. Can be.

In the present embodiment, an example has been shown in which one row of the display panel 10 is displayed while being distributed over four display periods.
The number is not limited to four, but may be three or five. When the horizontal scanning period is divided into n (n is an integer of 3 or more), the switches 581 to 5 in the data polyphase circuit 51 are divided.
Switch 63 in 8N and scan multiphase circuit 61
The number of times of switching between the contacts a and b of 1 to 63M is set to the number corresponding to n.

FIG. 6 shows one example of the configuration according to FIG. 2 described above.
This is the display timing of each line in the field. As shown in FIG. 6, the display of each row is divided into four parts with a non-display period in two scanning periods. In this non-display period, display of one quarter of each of the other four rows is performed in this display period. Have been done. As can be seen from FIG. 6, in the present invention,
The display periods of a plurality of rows do not overlap each other, and the display is performed in units of one row. In this embodiment, the non-display periods are all set to a fixed time, but are not limited to the fixed time.

The second embodiment shown in FIG. 2 is similar to the first embodiment shown in FIG.
As compared with the embodiment, there is an advantage that the number of DFFs of the DFFs 571 to 57N may be one, and the number of contacts of the switches 581 to 58N and the switches 631 to 63M is small. However, the non-display period in the second embodiment is shorter than the non-display period in the first embodiment. Therefore, from the viewpoint of preventing a decrease in luminance due to saturation of the phosphor, the first example can be said to be a more preferable embodiment.

As described above, according to the present invention, the display panel 10
The scanning electrodes L1 to LM are not simply scanned from top to bottom, but as shown in FIGS. 4 and 6, each row is divided into n phases and displayed. And
There are various methods for dispersing the n-times distributed display, and a delay unit for delaying the data of the video signal by one or more rows,
It is necessary to provide a switching unit for switching data before and after the delay and a switching unit for switching a row for scanning the scan electrodes L1 to LM of the display panel 10 at a timing synchronized with the switching.

[0069]

As described above in detail, the driving circuit of the matrix type display device according to the present invention is provided with the means for scanning each row of the cells by dispersing them in one field for n display periods. With such a configuration, it is possible to prevent a decrease in luminance due to saturation of the phosphor, thereby improving luminous efficiency. Further, the change with time of the cell can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a waveform chart for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a diagram for explaining display timing according to the first embodiment of the present invention.

FIG. 5 is a waveform chart for explaining the operation of the second embodiment of the present invention.

FIG. 6 is a diagram for explaining display timing according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a conventional example.

FIG. 8 is a diagram illustrating a configuration of a display panel of a matrix display device.

FIG. 9 is a waveform chart for explaining the operation of the conventional example.

FIG. 10 is a diagram for explaining display timing according to a conventional example.

FIG. 11 is a diagram showing a relationship between a pulse width and a light emission intensity according to a conventional example.

[Explanation of symbols]

1, 7 terminal 2 shift register 3 latch circuit 4 modulation circuit 8 timing control circuit 9 shift register 10 display panel 50, 51 data polyphase circuit 60, 61 scan polyphase circuit 561-56N, 581-58N, 621-62M , 6
31-63M switch (switching means) 571-57N, 581-58ND D flip-flop (delay means)

Claims (7)

[Claims] A display panel in which cells are arranged in a matrix by a plurality of rows and a plurality of columns;
In a driving circuit of a matrix type display device, which scans and displays in a row unit, and performs display so that display periods in a plurality of rows do not overlap each other, each row of the cells is n times in one field. (Where n is an integer of 3 or more). A driving circuit for a matrix display device, comprising: means for scanning while being dispersed in a display period. 2. A non-display period between the n display periods,
2. The driving circuit for a matrix type display device according to claim 1, further comprising means for scanning at least one other row. 3. A means for scanning by dispersing the display signal into n display periods, a delay means for delaying a video signal by one or more rows, and a video signal and a video signal delayed by the delay means in one field. 3. A driving circuit for a matrix type display device according to claim 1, further comprising switching means for switching to a mode. 4. The driving circuit according to claim 2, wherein said means for scanning one or more other rows is switching means for switching a row to scan said display panel. . 5. The driving circuit for a matrix type display device according to claim 1, wherein the gradation expression in the display period is performed by pulse width modulation or voltage modulation. 6. The matrix-type display device according to claim 1, wherein a display period in one row of said cells is substantially equally divided to be said n display periods. Drive circuit. 7. The device according to claim 1, wherein the matrix type display device is an electroluminescence display device.
7. The driving circuit for a matrix type display device according to any one of items 6 to 6.