JPH1124993A - Write instruction processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a processing cycle time without interrupting an instruction processing and to improve the performance of a write instruction when the write instructions are continuously issued in a cache. SOLUTION: A cache system is provided with a main pipe 3 for retrieving an address array 4 in accordance with a write instruction received from a processor 1 and obtaining access information of a data array 6; a write instruction buffer 7 which temporarily holds the write instruction obtaining access information which the main pipe 3 transmits; a sub-pipe 5 for updating the data array 6 independent of the main pipe 3 in accordance with the write instruction obtaining access information; and a request mediation part 2 for identifying the instruction received from the processor 1 and the write instruction which the write instruction buffer 7 holds, for transmitting the instructions to the main pipe 3 and for transmitting the write instructions to the sub-pipe 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write instruction processing device, and more particularly to a write instruction processing device for improving the performance of a cache system.

[0002]

2. Description of the Related Art Conventionally, in a memory device of a computer, improvement of performance of a write instruction to a cache has been a major problem.

FIG. 5 is a block diagram showing an example of a conventional cache system. In FIG.
1 issues a write instruction and a read instruction to the cache. The request arbitration unit 52 arbitrates instructions from the processor 51 and the write instruction buffer 56 in accordance with the priority order, and selects an instruction. The main pipe 53 carries information on the instruction selected by the request arbitration unit 52, receives index data for an instruction that indexes the address array 54, and determines a cache hit or cache miss of the instruction. The address array 54 receives a write instruction and a read instruction in accordance with the instruction selected by the request arbitration unit 52, performs the respective operations, and passes the indexed data to the main pipe 53 in the case of a read. The data array 55 performs a write operation and a read operation in accordance with the instruction selected by the request arbitration unit 52, similarly to the address array 54. The write instruction buffer 56 stores the write instruction from the processor 51 until the request arbitration unit 52 selects the write instruction when the result of indexing the address array 54 by the main pipe unit 53 is a cache hit.

FIG. 6 is a time chart showing an operation example of the above cache system.

Referring to FIG. 5 and FIG.
, The request arbitration unit 52 performs arbitration. As a result of the arbitration, when the write instruction P1 from the processor 51 is selected, the information of the write instruction P1 is passed to the main pipe 53. At the same time, a read instruction is output to the address array 54 to check whether data at the same address as the write instruction P1 is held in the cache.

In the request arbitration unit 52, when there is no instruction from another request source, an instruction from the processor 51 can be continuously selected.

[0007] The main pipe 53 carries information of the write instruction P 1 and receives index data from the address array 54. If the data from the address array 54 is compared with the information of the write instruction P1 in the main pipe and a cache hit is found, the information of the write instruction P1 carried by the main pipe 53 is compared and a cache hit is found. In this case, the information of the write instruction P1 carried by the main pipe 53 is stored in the write instruction buffer 56 by the write instruction W1.
Set as Similarly, if the subsequent write instructions P2 and P3 from the processor 51 also hit the cache, they are similarly set in the write instruction buffer 56 as write instructions W2 and W3.

The stored write instruction W1 in the write instruction buffer 56 makes a request request to the request arbitration unit 52 again in order to update the data in the data array 55. In the request arbitration unit 52, the write instruction Pn from the processor 51 and the write instruction W1 from the write instruction buffer 56 compete with each other, but if the normal write instruction buffer has higher priority, the write instruction buffer 56 The instruction W1 is selected and the main pipe 5
3 while passing the information of the write instruction W1 to the data array 55.

Similarly, write instructions W2 and W3 stored in write instruction buffer 56 also compete with interrupted write instruction Pn from processor 51, but W2 and W3 in write instruction buffer 56 have priority. Is updated, and the data in the data array 55 is updated. And
When all the instructions in the write instruction buffer 56 are selected and processed by the request arbitration unit 52, the process of the write instruction Pn from the processor 51 is resumed, and the same write operation is repeated.

If a write instruction from the processor is a cache miss, it is not directly related to the present invention.
Description is omitted.

[0011]

In the above-described write instruction processing device in the conventional cache system, when a write instruction is continuously issued from the processor, the request arbitration unit performs the instruction arbitration unit when processing the instruction in the write instruction buffer. Conflicts with instructions, and instructions from the processor must wait. Therefore, there is a disadvantage that the processing of the instruction from the processor is interrupted, and the processing capability is reduced.

The reason is that in the request arbitration unit,
This is because only one instruction can be selected. Then, the main pipe stores information of the instruction selected by the request arbitration unit as 1
This is because you can't go around for a while.

[0013] It is an object of the present invention to provide a write instruction processing apparatus which improves the performance of a write instruction by improving a processing cycle without interrupting instruction processing when a write instruction is continuously issued to a cache. Is to do.

[0014]

According to the present invention, there is provided a write instruction processing apparatus, comprising: a cache system including a data array for storing data to be processed and an address array for holding an address of the data array; Processes the write instruction in the main pipe when indexing the address array, processes the write instruction in the subpipe when the write instruction updates the data array, and the main pipe and the subpipe buffer each other. It is configured to carry out the revolving processing independently of each other.

Further, in the write instruction processing device according to the present invention, the main pipe and the sub-pipe are configured to simultaneously carry and process information of two instructions.

Further, in a cache system including a data array for storing data to be processed and an address array for holding an address of the data array, the write instruction processing apparatus according to the present invention provides the address array according to a write instruction received from a processor. A main pipe for retrieving the access information of the data array, a write instruction buffer for temporarily storing a write instruction for acquiring the access information transmitted by the main pipe, and the main pipe according to the write instruction for acquiring the access information. The sub-pipe for updating the data array independently of the pipe, the instruction received from the processor and the write instruction held by the write instruction buffer are identified, the instruction is sent to the main pipe, and the write instruction is sent to the sub-pipe. Suri Constructed and a Est arbitration unit.

Further, in the write instruction processing device of the present invention, the request arbitration unit identifies a processor request and a write instruction buffer request and sends a main pipe valid signal and a sub pipe valid signal, and the request arbitration circuit. A data selection circuit for inputting instruction information of the write instruction buffer and instruction information of the processor instructed by a circuit, sending main pipe carry information to the main pipe, and sending sub pipe carry information to the sub pipe, and the request arbitration circuit A write / read instruction generating circuit for inputting instruction information of the write instruction buffer and instruction information of the processor, and identifying each instruction information to send a write instruction signal or a read instruction signal to a data array and an address array. Configured to include a.

That is, in the write instruction processing device according to the present invention, information of an instruction that accesses only the data array, such as an instruction from the write instruction buffer, is carried around by the subpipe. Therefore, it is possible to separately carry information of instructions from the two request sources selected by the arbitration unit in both the main pipe and the sub pipe. Further, arbitration allows instructions from two request sources to be selected simultaneously. Therefore, different information can be simultaneously passed to the main pipe and the sub pipe.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, a write instruction processing apparatus according to the present invention includes a processor 1 in a cache system including a data array 6 for storing data to be processed and an address array 4 for holding an address of the data array.
A main pipe 3 for searching the address array in accordance with the write instruction received from the main pipe and acquiring access information of the data array, a write instruction buffer 7 for temporarily storing a write instruction for acquiring the access information transmitted by the main pipe, The sub-pipe 5 updates the data array independently of the main pipe in accordance with the write instruction that has obtained the access information, and identifies the instruction received from the processor and the write instruction held by the write instruction buffer, and A request arbitration unit 2 for sending the write instruction to the pipe and sending the write instruction to the sub-pipe.

The processor 1 issues a write instruction and a read instruction to the cache unit, and passes the instructions to the request arbitration unit 2.

The request arbitration unit 2 receives an instruction from the processor 1 or the write instruction buffer 7, arbitrates according to the priority order, selects an instruction, passes information of the selected instruction to the main pipe 3 or the sub-pipe 5, and transmits an address array. 4 and the data array 6.

The main pipe 3 carries information of the instruction selected by the request arbitration unit 2 and, in the case of an instruction for indexing the address array 4, receives the read data and makes a cache hit or cache miss of the instruction. Make a judgment.

The address array 4 includes the request arbitration unit 2
According to the instruction selected in step (1), a write instruction and a read instruction are received, and the respective operations are performed. In the case of a read, indexed data is passed to the main pipe 3.

When the request arbitration unit 2 selects the write instruction buffer 7, the subpipe 5 receives information on the instructions in the write instruction buffer via the request arbitration unit 2 and carries it around. At this time, the information carried around in the sub-pipe 5 is only the information necessary for the write operation and the information necessary for the fault handling.

The data array 6 receives a write instruction and a read instruction according to the instruction selected by the request arbitration unit 2 and performs each operation. In addition, in the rotation information for the instruction at that time, when the sub-pipe 5 is valid, the operation is performed in accordance with the information in the sub-pipe 5, and otherwise, the operation is performed in accordance with the information in the main pipe 3.

The write instruction buffer 7 stores the write instruction when the result of indexing the address array 4 by the write instruction from the processor 1 being carried around the main pipe 3 is a cache hit. The stored write instruction is used to update data in the data array 6.
The request is made to the request arbitration unit 2 again, and is stored in the buffer until it is selected.

FIG. 2 is a block diagram showing the configuration of the request arbitration unit 2 in the above-mentioned write instruction processing device. In FIG. 1, the request arbitration unit 2 includes a request arbitration circuit 21, a data selection circuit 22, and a write / read instruction generation circuit 23.

The request arbitration circuit 21
It receives instructions from the write instruction buffer 7 and performs arbitration in accordance with the priority order, passes the arbitration result to the data selection circuit 22 and the write / read instruction generation circuit 23, and outputs a valid signal to the main pipe 3 and the sub-pipe 5.

FIG. 3 shows the standard of the request arbitration method.
Referring to FIG. 11, when only one of processor 1 and write instruction buffer 7 outputs an instruction, only the request source outputting the request is selected. When both the processor 1 and the write instruction buffer 7 output an instruction and compete with each other, when an instruction from the processor 1 accesses the data array 6 for writing or reading, only the write instruction buffer 7 is selected. . Conversely, when no instruction from the processor 1 accesses the data array 6, both the processor 1 and the instruction in the write instruction buffer 7 are selected.

The data selection circuit 22 receives instruction information from the processor 1 and the write instruction buffer 7, selects information on each request source according to the result of the request arbitration circuit 21,
The selected information is output to.

The write / read instruction generating circuit 23 receives instruction information from the processor 1 and the write instruction buffer 7, and issues a write instruction and a read instruction to each of the address array 4 and the data array 6 according to the result of the request arbitration circuit 21. Judge and output it.

FIG. 4 is a time chart showing an example of the operation of the above-mentioned write command processing device. In the figure, when the write instruction P1 is issued from the processor 1, the request arbitration unit 2 arbitrates. In this case, since it is only the instruction from the processor 1, the write instruction P1 of the processor 1 is selected (see FIG. 3), and the information of the write instruction P1 from the processor 1 is passed to the main pipe 3. At the same time, the request arbitration unit 2 outputs a read instruction to the address array 4 in order to check whether or not the cache holds data at the address of the write instruction P1 from the processor 1.

Since the write operation is a continuous write operation, the processor 1 issues subsequent write instructions P2, P3,. These instructions are successively similarly selected by the request arbitration unit 2, pass information of each write instruction to the main pipe 3, and output a read instruction to the address array 4.

The main pipe 3 carries the information of the write instruction P 1 from the processor 1, receives the data indexed from the address array 4, and compares it with the information of the write instruction P 1 carried around in the main pipe 3. As a result of the comparison,
If it is determined that there is a cache hit, the information of the write instruction P1 carried around in the main pipe 3 is stored in the write instruction buffer 7 as the write instruction W1.

The subsequent write instructions P2, P3... Pn-1 successively issued from the processor 1 are stored in the write instruction buffer 7 as write instructions W2, W3.

The stored write instruction W1 makes a request request to the request arbitration unit 2 again to update the data in the data array 6. At this time, in the request arbitration unit 2, the write instruction Pn from the processor 1 and the write instruction W1 from the write instruction buffer 7 compete with each other. However, the write instruction Pn from the processor 1
Indicates that the data array 6 is read only by reading the address array 4.
Since there is no access to the request, the request arbitration unit 2 selects write instructions from both request sources (see FIG. 3).

Two selected write instructions Pn and W1
Respectively, a write instruction Pn from the processor 1 passes information carried to the main pipe 3 and outputs a read instruction to the address array 4, and a write instruction W1 from the write instruction buffer 7 passes information carried to the sub-pipe 5 to pass data A write instruction is output to the array 6.

The main pipe 3 and the sub pipe 5 operate independently. The write instruction Pn passed to the main pipe 3 is the write instruction P
1 to Pn-1, receives index data from the address array 4, determines a cache hit or a cache miss, and if there is a cache hit, writes the information of the write instruction Pn into the write instruction buffer 7 to write the instruction. Stored as Wn. Then, a request request is made to the request arbitration unit 2 again, and a conflict occurs with the write instruction Pn + n from the processor 1, and similarly, both the write instruction Wn and the write instruction Pn + n are selected by arbitration.

Write instruction W1 passed to subpipe 5
Performs a write operation to the data array 6, and the write instruction P1 from the processor 1 ends. Subsequently, in the request arbitration unit 2, the write instruction P
Competition occurs one after another, such as a competition between the n + 1 and the write instruction buffer W2 and a competition between the write instruction Pn + 2 and the write instruction W3, but arbitration is performed without interrupting the write instruction from the processor 1 and the main pipe 3 And the inside of the sub pipe 5 are operated simultaneously.

If all consecutive write instructions from the processor 1 hit the cache, the conventional technique uses the main pipe 3 twice for one instruction and interrupts the subsequent write instruction from the processor 1. In the present invention, 1
Since the main pipe 3 is used only once for an instruction, a subsequent write instruction from the processor 1 is not interrupted. Therefore, in the case of a cache hit in successive write instructions, the processing cycle is reduced to half, and the processing performance of the write instruction is greatly improved.

[0042]

As described in detail above, according to the present invention, successive write instructions from the processor are processed continuously without interruption. As a result, it is possible to improve the performance twice as long as the cycle time of the write instruction. The reason is that a subpipe is provided for writing to the data array at the time of a cache hit in a write instruction, and the main pipe can be used by an instruction from the processor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a request arbitration unit.

FIG. 3 is an explanatory diagram showing arbitration criteria of a request arbitration unit.

FIG. 4 is a time chart showing an operation example of the present invention.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a time chart showing the operation of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor 2 Request arbitration unit 3 Main pipe 4 Address array 5 Subpipe 6 Data array 7 Write instruction buffer 21 Request arbitration circuit 22 Data selection circuit 23 Write / read instruction generation circuit

Claims (4)

[Claims] In a cache system including a data array for storing data to be processed and an address array for holding an address of the data array, when a write instruction received from a processor indexes the address array, the write instruction is sent to a main pipe. The write instruction is carried around, and when the write instruction updates a data array, the carry instruction is carried out in a subpipe, and the main pipe and the subpipe carry out carryover processing independently without buffering each other. Write instruction processing unit. 2. The write instruction processing device according to claim 1, wherein said main pipe and said sub-pipe simultaneously carry out and process information of two instructions. 3. In a cache system including a data array for storing data to be processed and an address array for holding an address of the data array, the address array is searched according to a write command received from a processor, and access information of the data array is retrieved. And a write instruction buffer for temporarily storing a write instruction that has acquired the access information sent by the main pipe, and the data array that is independent of the main pipe according to the write instruction that has acquired the access information. A subpipe to be updated, and a request arbitration unit that identifies an instruction received from the processor and a write instruction held by the write instruction buffer, sends the instruction to the main pipe, and sends the write instruction to the subpipe. Features and Write instruction processor. 4. The write instruction processing device according to claim 3, wherein the request arbitration unit identifies a processor request and a write instruction buffer request, and sends a main pipe valid signal and a sub pipe valid signal. A data selection circuit for instructing a request arbitration circuit to input instruction information of the write instruction buffer and instruction information of the processor, transmit main pipe revolving information to the main pipe, and transmit subpipe revolving information to the subpipe; A write / read instruction generating circuit which receives instruction information of the write instruction buffer and instruction information of the processor instructed by the arbitration circuit, identifies each instruction information, and sends a write instruction signal or a read instruction signal to a data array and an address array. When A write instruction processing device comprising: