JPH1125675A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce current consumption of a device in write operation by detecting that at least one column address strobe signal is activated during writing operation, generating a signal having the prescribed pulse width, and controlling an I/O gate means performing input/output of data to/from a bit line by logical product of this signal and a column decoder signal. SOLUTION: An enable-pulse circuit WE-GEN 200 generating an enable-pulse signal WE for making writing enable-signals WE1 and WE2 as input and making rising edges of each signal as triggers is added, and further, an output of a two input logical product gate 201 for making the enable-pulse signal WE and an output of a column decoder Y-DEC 40 as inputs is connected to CL. Thereby, as an enable-period of CL is shorter than a conventional example, such a period that DC current flows in sense amplifiers SA 20, 27-29 is shortened, current consumption of the device can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having a multi-CAS function.

[0002]

2. Description of the Related Art In order to simplify the description, 2CA
The description will be limited to a semiconductor memory device having the S function.
FIG. 7 is a configuration diagram of a conventional semiconductor memory device having a multi-CAS function. Here, / is (superscript bar:
−N).

In FIG. 1, a cell array 30 (CEL)
L-ARRAY) has a plurality of memory cells regularly arranged along a bit line and a word line, and has the same bit lines BL11, / BL11 to BL22, / BL.
22 is connected to a sense amplifier (SA)
20, 27-29 and column switch (SW) 10, 1
The sub data bus (hereinafter, referred to as SDB) 11 and / SDB 11 to SDB 22 and / SDB 22 are connected via 3 to 15.

[0004] Further, SDB is a selector (SEL) 5
0, 56 to 58, are connected to data buses (hereinafter, referred to as DBs) DB1, / DB1 and DB2, / DB2, and are connected to input buffers (WB) 64, 66 and output buffers (RA) 65, 67. Connected to. The SA which amplifies a small signal from the memory cell by the sense amplifier activating signals S and / S includes NMOSs 21 and 22 whose gates and drains are cross-coupled to each other.
2 and PMOSs 23 and 24. NMOS2
The sources of NMOSs 1 and 22 are connected to a common node / SL, and the NMOSs 2 have the sense amplifier activation signal S as a gate input.
6, the signal is pulled down to the ground level.

The sources of the PMOSs 23 and 24 are connected to the common node SL, and are pulled up to the power supply level by the PMOS 25 having the gate input of the sense amplifier activating signal / S. The sense amplifier activation signals S and / S are connected to terminal 1
Address strobe signal / RAS input from
(Hereinafter referred to as / RAS), and is generated by a row control circuit (RAS-Con) 60.

The SW controlling the data transfer between the bit line and the SDB by the signal CL connected to the output of the column decoder (Y-DEC) 40 has a gate connected to the signal CL, a source connected to the bit line, It comprises NMOSs 11 and 12 whose drains are connected to the SDB. Y-DEC4
0 is an address signal ADD input to the terminal 2 (hereinafter referred to as an address signal ADD).
Column address buffer circuit (YADD-Buffer) 61 for amplifying and temporarily storing ADD).
Is decoded.

The SEL has an NMOS 5 having AY as a gate input, a source connected to SDB, and a drain connected to DB.
4, 55 and the write control signal WE1 as the first input,
The output of a two-input AND gate 53 having AY as a second input is connected to the gate, the source is connected to the SDB, and the drain is connected to the DB.
WB is controlled by the write enable signal WE1.
Input data DQ1 (hereinafter referred to as input data) input from the input / output terminal 6
DQ1) is amplified, temporarily stored, and written on DB1. The RA amplifies and temporarily stores the data on DB1 under the control of the read enable signal RE1, and outputs the data to the input / output terminal 6.

An input / output control circuit (I / O-Con) 62
Is the first column address strobe signal / CAS1 (hereinafter referred to as / CAS1) input to the terminal 3 and the terminal 4
In response to a read / write control signal / WE (hereinafter, referred to as / WE) input to the read / write controller, a read enable signal RE1 and a write enable signal WE1 are generated. An input / output control circuit (I / O-Con) 63 relating to a second column address strobe signal / CAS2 (hereinafter referred to as / CAS2) input to a terminal 5, a read enable signal RE2, and write enable signals WE2 and WB6.
6. Since the control relationship of RA67 is the same as the relationship of / CAS1 described above, its description is omitted here.

Next, the write operation will be described with reference to the timing chart of FIG. When / RAS falls to an active state, data read from the cell array 30 is read to each bit line. Also, the row control circuit 60 lowers / S a predetermined time after / RAS transitions to the "L" level, activates the SA connected to each bit line, and amplifies the minute signal on the bit line. .

Next, when the signal output AY of the column address buffer circuit 61 is decoded and a predetermined CL rises, a predetermined bit line and SDB are connected by SW, and information on the bit line is transferred to SDB. Then, / CAS1
When / WE2 and / WE further fall, write enable signals WE1 and WE2 rise and WB6
4. WB66 is activated. Activated WB64,
The WB 66 pulls down one of DB1, / DB1 and DB2, / DB2 to the ground level and pulls up the other to the power supply level based on the input data of the input / output terminals 6 and 7. SE selected by AY at the same time
Through L, SDB11, / SDB11 and SDB2
1, the write data is transferred to the / SDB 21.

Further, via SW selected from CL,
B latched to ground level and power supply level in SA
The potentials of L11, / BL11 and BL21, / BL21 are inverted, and data is written to predetermined memory cells in the cell array 30 connected to each bit line.

[0012]

By the way, when the write enable signals WE1 and WE2 fall,
Alternatively, when the selection is not made by AY, the output of the 2-input AND gate 53 in the SEL goes to “H” level, so that in the write operation described above, the SDB21, / SDB21 and SDB22,
/ SDB22 is the NMOS 51 in the non-selected SEL,
As a result, the potential is pulled up to a potential lower than the power supply level by the threshold value of the NMOS.

On the other hand, the SA latches the potential of the bit line pair to the ground level and the power supply level, so that SDB21, / S connected to the bit line at the ground level potential.
A DC current flows through the SA via the DB21 and one of the SDB22 and / SDB22 (idc). Since this current flows during the period when CL rises, there is a problem in that the current consumption of the device during the write operation increases.

An object of the present invention is to provide a semiconductor memory device which eliminates the above problems and can reduce the current consumption of a device during a write operation.

[0015]

In order to achieve the above object, the present invention provides: [1] a plurality of bit lines and a plurality of word lines, and regularly arranged along the bit lines and the word lines; A memory cell array including a plurality of memory cells, a column decoder for decoding an externally input address signal, and controlled by an output of the column decoder, connected to each of the bit lines and connected to these bit lines. In a semiconductor memory device having I / O gate means for inputting / outputting data and controlling data input / output with a plurality of column address strobe signals, at least one column address strobe signal is activated during a write operation. Pulse generating means for generating a signal having a predetermined pulse width by detecting that the The I / O gate means is controlled by an output of an AND gate which takes a logical AND with a signal generated by the pulse generating means.

[2] A memory cell array including a plurality of bit lines and a plurality of word lines, and a plurality of memory cells regularly arranged along the bit lines and the word lines, and an externally input address Column decoder means for decoding signals; I / O gate means controlled by the output of the column decoder means, connected to each of the bit lines, for inputting and outputting data to and from these bit lines; In a semiconductor memory device having a function of controlling input / output of data with a strobe signal, a plurality of means for detecting that a column address strobe signal is activated during a write operation and generating a write enable pulse signal are inputted. The output of the column decoder means and the plurality of write operations are provided for each of the column address strobe signals. In the taking of each logical product of the signal generated from the means for generating an enable pulse AND gate output, in which so as to control the I / O gate means.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram of a semiconductor memory device having a multi-CAS function according to a first embodiment of the present invention. Elements and parts common to those in the conventional example shown in FIG. 7 are described in the same manner as in the conventional example, and here, only the circuit configuration of a part different from the conventional example will be described.

In this embodiment, a write enable pulse circuit (WE-GEN) which receives write enable signals WE1 and WE2 as inputs, writes data using a rising edge of each signal as a trigger, and generates an enable pulse signal WE.
200 is added, the first input is a write enable pulse signal WE, and the output of a two-input AND gate 201 whose second input is the output of Y-DEC is connected to CL.

In the conventional example, the write enable signals WE1 and WE2 input to the SEL are changed to the write enable pulse signal WE. Hereinafter, the operation of the semiconductor memory device having the multi-CAS function according to the first embodiment of the present invention will be described. Here, only the operation related to the problem to be solved by the invention will be described.

FIG. 2 shows a write enable pulse circuit (W
E-GEN) is shown. As shown in this figure,
A first input of the two-input OR gate 405 is connected to an output of the delay circuit 401 having WE1 as an input, by an inverter 403.
The inverted output is connected at, and the second input is WE1
Is connected. A first input of the two-input OR gate 406 is connected to an output obtained by inverting an output of the delay circuit 402 having WE2 as an input by an inverter 404, and a second input is connected to WE2.

The output of the two-input OR gate 405 and the output of the two-input OR gate 406 are input to a two-input AND gate 407, respectively, and the output is connected to the node Na to become the gate input of the NMOS 409. . NMO
The drain of S409 is a PMOS4 whose gate is grounded.
08 as well as to the node Nb. The first input of the AND gate 411 is connected to the output of the delay circuit 410 having Nb as an input, and the second input is connected to Nb.

Next, the operation of this circuit will be described with reference to FIG. As shown in this figure, when WE1 rises, Na goes to the “H” level during a predetermined delay time generated in the delay circuit 401, so that the NMOS 409 is turned on and N
b is pulled down to the “L” level during this period. Also,
When Nb is once pulled down to the “L” level, the output of the 2-input AND gate 411 becomes the “H” level, and changes the “H” level during the period corresponding to the sum of the delay times generated in the delay circuits 401 and 410. Maintain, then fall to "L" level.

The above is the description of the operation in the case of operating with the rising edge trigger of WE1, but the same applies to the case of operating with the rising edge trigger of WE2.
Next, the write operation of the first embodiment of the present invention will be described with reference to the timing chart of FIG. As shown in the figure, as described above, when / CAS1 and / CAS2 and further / WE fall, the write enable signals WE1 and WE2 rise, and the rising edge of each write enable signal is used as a trigger, as described above. The circuit (WE-GEN) 200 enables the write enable pulse signal WE during a predetermined period.

Next, when the WB 64 and the WB 66 are activated, the DBs based on the input data of the input / output terminals 6 and 7 are used.
One of / 1, DB1 and DB2, / DB2 is pulled down to the ground level, and the other is pulled up to the power supply level. At the same time, SDB11, / SDB11 and SDB21, / SD via the SEL selected by AY.
The write data is transferred to B21.

Further, the CL connected to the output of the Y-DEC 40 and the output of the 2-input AND gate 201 having two inputs of the write enable pulse signal WE is also enabled during the enable period of the write enable pulse signal WE. BL11, / BL11 and BL21, / BL21 latched to the ground level and power supply level by SA
Cell array 3 connected to each bit line
Data is written to a predetermined memory cell within 0.

During the enable period of the write enable pulse signal WE, the activated WB 64 and W
B66 is sensed by SA and BL11, / BL11 and BL2 latched at the ground level and the power supply level.
A period until the potential of 1, BL21 is inverted is sufficient. Because the SA latches the inverted data, once the WB inverts the data of the bit line, the SA can write data to a predetermined memory cell in the cell array 30 connected to each bit line. It is.

With this configuration, according to the first embodiment, when the column address strobe signal / CAS is used for a wide purpose during the active period, the enable period of CL is shorter than that of the conventional example. SDB21, / SDB21 and SD connected to the bit line side at the ground level potential by the SW selected from the unselected SEL.
The period in which the DC current flows through SA through one of B22 and / SDB22 is shortened, and the current consumption of the device can be reduced.

Next, a second embodiment of the present invention will be described. FIG. 5 is a configuration diagram of a semiconductor memory device having a multi-CAS function according to a second embodiment of the present invention. Note that elements and common parts common to the conventional example are described in the same manner as the conventional example, and here, only the circuit configuration of a part different from the conventional example will be described.

In this embodiment, as shown in the figure, the first input is a write enable pulse signal WE1 and the second input is
Is an output of Y-DEC, its output is a two-input AND gate 300 connected to CL1, the first input is a write enable pulse signal WE2, and the second input is Y-DEC.
−DEC output, and a 2-input AND gate 301 whose output is connected to CL2 is added. SW
The control of SW10 and SW13 is changed to CL1, and the control of SW14 and SW15 is changed to CL2.

Next, the write operation of the second embodiment of the present invention will be described with reference to the timing chart of FIG. As shown in FIG. 6, when / CAS1 and / CAS2 and / WE fall, write enable signals WE1 and WE2 rise. Next, when the WB 64 and the WB 66 are activated, the DB based on the input data of the input / output terminals 6 and 7 is used.
One of / 1, DB1 and DB2, / DB2 is pulled down to the ground level, and the other is pulled up to the power supply level. At the same time, SDB11, / SDB11 and SDB21, / SD via the SEL selected by AY.
The write data is transferred to B21.

Further, CL1 connected to the output of the Y-DEC 40 and the output of the two-input AND gate 300 having two inputs of the write enable signal WE1 is also enabled during the enable period of the write enable signal WE1. Similarly, the CL2 connected to the output of the Y-DEC 40 and the output of the 2-input AND gate 301 having the write enable signal WE2 as two inputs is also connected to the write enable signal W.
Since it is enabled during the enable period of E2, SA
BL1 latched at the ground level and the power supply level at
1, / BL11 and BL21, / BL21 are inverted, and data is written to predetermined memory cells in the cell array 30 connected to the respective bit lines.

With such a configuration, according to the second embodiment, when the active periods of the plurality of column address strobe signals / CAS are used for different purposes,
Since the CL active period is determined independently for each of the column address strobe signals / CAS, the total active width of the CL is shorter than that of the conventional example. , / SDB21 and SDB22, /
A period in which a DC current flows through SA through one of the SDBs 22 is shortened, and current consumption of the device can be reduced.

It should be noted that the present invention is not limited to the above-described embodiment, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0034]

As described above, according to the present invention, the following effects can be obtained. [A] According to the first aspect of the present invention, when the column address strobe signal / CAS is used for a wide purpose during the active period, the enable period of the CL is shorter than that of the conventional example, so that it is shorter than the unselected SEL. Depending on the selected SW, S connected to the bit line side at the ground level potential
DB21, / SDB21 and SDB22, / SDB22
Through either of the above, the period during which the DC current flows to the SA is shortened, and the current consumption of the device can be reduced.

[B] According to the second aspect of the present invention, when the active periods of the plurality of column address strobe signals / CAS are used for different purposes, the column address strobe signals / CAS are independent of each other. CL
Since the active period is determined, the total active width of CL is shorter than that of the conventional example, so that the unselected SEL
S connected to the bit line side at a higher ground level potential
DB21, / SDB21 and SDB22, / SDB22
Through either of the above, the period during which the DC current flows to the SA is shortened, and the current consumption of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device having a multi-CAS function according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a write enable pulse circuit (WE-GEN) of the semiconductor memory device having a multi-CAS function according to the first embodiment of the present invention.

FIG. 3 is a timing chart illustrating a circuit operation of a write enable pulse circuit (WE-GEN) of the semiconductor memory device having the multi-CAS function according to the first embodiment of the present invention.

FIG. 4 is a timing chart during a write operation of the semiconductor memory device having the multi-CAS function according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a semiconductor memory device having a multi-CAS function according to a second embodiment of the present invention.

FIG. 6 is a timing chart at the time of a write operation of a semiconductor memory device having a multi-CAS function according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional semiconductor memory device having a multi-CAS function.

FIG. 8 is a timing chart of a conventional semiconductor memory device having a multi-CAS function during a write operation.

[Explanation of symbols]

30 cell array 200 write enable pulse circuit (WE-GE
N) 201, 300, 301, 407 2-input AND gate 401, 402, 410 Delay circuit 403, 404 Inverter 405, 406 2-input OR gate 408 PMOS 409 NMOS 411 2-input NOT AND gate

Claims (2)

[Claims] 1. A memory cell array including a plurality of bit lines and a plurality of word lines, and a plurality of memory cells regularly arranged along the bit lines and the word lines, and an externally input address signal. Column decoder means for decoding the data, controlled by an output of the column decoder means,
I / O gate means connected to each of the bit lines for inputting and outputting data to and from these bit lines, and a semiconductor memory device having a function of controlling input and output of data with a plurality of column address strobe signals. In operation, it has pulse generating means for detecting that at least one column address strobe signal has been activated and generating a signal of a predetermined pulse width, wherein the signal is generated by the output of the column decoder means and the pulse generating means. A semiconductor memory device, wherein the I / O gate means is controlled by an output of a logical product gate which takes a logical product with a signal. 2. A memory cell array including a plurality of bit lines and a plurality of word lines, and a plurality of memory cells regularly arranged along the bit lines and the word lines, and an externally input address signal. Column decoder means for decoding the data, controlled by an output of the column decoder means,
I / O gate means connected to each of the bit lines for inputting and outputting data to and from these bit lines, and a semiconductor memory device having a function of controlling input and output of data with a plurality of column address strobe signals. In operation, a means for detecting that a column address strobe signal is activated and generating a write enable pulse signal is provided for each of a plurality of input column address strobe signals, and an output of the column decoder means is provided. A semiconductor memory device, wherein the I / O gate means is controlled by an output of a logical product gate which takes a logical product with each of the signals generated by the means for generating the plurality of write enable pulses.