JPH11260830A - Bipolar semiconductor device and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To provide a bipolar semiconductor device and a method of manufacturing the same, which have a sufficiently low base resistance and can sufficiently suppress a decrease in current amplification factor and a deterioration in high-frequency characteristics. I do. SOLUTION: A semiconductor thin film to be an emitter region and a base extraction region is formed using different mask materials by different lithography steps, and diffusion layers forming the respective regions are formed in a self-aligned manner with each other. This enables a structure in which the emitter region and the base extraction region are close to the base width or less. Furthermore, by introducing impurities into the base extraction region before introducing impurities into the base and the emitter that define the base width, the impurity profile of the emitter region and the base region and the setting of the base width can be ideally formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral bipolar semiconductor device formed by using a semiconductor thin film and a method of manufacturing the same.

[0002]

2. Description of the Related Art A so-called lateral bipolar transistor is different from a so-called stacked bipolar transistor in which base, emitter and collector regions are stacked.
There is an advantage that the parasitic capacitance between the terminals can be reduced. References disclosing such a lateral type bipolar transistor include, for example, Japanese Patent Application No. 63-19 / 1988.
No. 8173 can be mentioned.

FIG. 16 is a schematic explanatory view showing a planar structure of a lateral type bipolar transistor disclosed in the document. That is, the bipolar transistor 100 includes a first conductivity type collector region 125 a formed laterally in a semiconductor thin film stacked on the insulating substrate 121,
Conductive emitter region 123 and collector region 125a
And a second conductivity type base region 124 a having a predetermined base width W sandwiched between the emitter region 123 and the emitter region 123. Further, a second conductive type base extraction region 124b connected to the base region 124a is provided. here,
n-type emitter region 123 and p-type base region 124a
And the n-type collector region 125a are provided in parallel on the same plane.

In this conventional example, in order to eliminate the drawbacks of the stacked bipolar transistor, an emitter region and a base lead region are formed on the same plane, thereby simplifying the transistor manufacturing process and reducing the cost. In addition, the reliability of the operation is improved. Further, at this time, the emitter region and the base extraction region formed on the same plane are designed so that a parasitic diode that leads to a reduction in current amplification factor is not formed between them.

That is, a second conductivity type impurity forming base region 124a and a first conductivity type impurity forming emitter region 123 are formed.
The conductive type impurities are diffused in a self-aligned manner using the same mask material so that the base width W is defined. Emitter region 123 and base extraction region 12
4b are connected only via the base region 124a below the mask material without interposing a parasitic diode therebetween.

Also, in the manufacturing method, the parasitic diodes are separated by the simultaneously formed resist pattern so as not to form a parasitic diode between the emitter 123 and the base extraction region 124b.

[0007]

However, in the above conventional example, the emitter region 123 and the base extraction region 12 are not provided.
The distance to 4b can be reduced only to the minimum pattern due to the margin of lithography alignment. As a result, it is difficult to sufficiently reduce the base resistance, and it is difficult to improve the high frequency characteristics. In order to solve this, it is necessary to diffuse the second conductivity type impurities contained in the base extraction region 124b in the lateral direction by heat treatment and extend them. However, at this time, the impurities of the second conductivity type forming the base region 124a formed earlier also diffuse, and as a result, the predetermined base width W changes,
The characteristics of the transistor change. Specifically, a steep impurity profile can no longer be obtained due to an increase in the number of heat treatment steps, so that the base width W is broadened due to the deformation of the impurity profile in the base region, the current amplification rate is reduced due to the deformation of the impurity profile in the emitter region, and the high frequency This causes a problem of characteristic deterioration.

[0008] The present invention has been made in view of the above problems. That is, an object of the present invention is to provide a bipolar semiconductor device and a method of manufacturing the same, which have a sufficiently low base resistance and can sufficiently suppress a decrease in current amplification factor and a deterioration in high-frequency characteristics.

[0009]

According to the present invention, a semiconductor thin film to be an emitter region and a base extraction region is formed by using different mask materials by different lithography steps, and each region is formed by using different mask materials. The diffusion layers to be formed are self-aligned with each other. This enables a structure in which the emitter region and the base extraction region are close to the base width or less. Furthermore, by introducing impurities into the base extraction region before introducing impurities into the base and the emitter that define the base width, the impurity profile of the emitter region and the base region and the setting of the base width can be ideally formed.

That is, a bipolar semiconductor device according to the present invention includes an insulator and a semiconductor thin film selectively laminated on the insulator, wherein the semiconductor thin film has a collector region of a first conductivity type. A first conductivity type emitter region, a second conductivity type base region sandwiched between the collector region and the emitter region and having a predetermined base width, and a second conductivity type base lead connected to the base region. Region, and the base region and the emitter region are separated from an end of the same mask by an impurity of the first conductivity type and a second region.
The predetermined base width is determined by a difference in diffusion distance between the first conductivity type impurity and the second conductivity type impurity, and wherein the predetermined base width is determined by a diffusion distance between the first conductivity type impurity and the second conductivity type impurity. The emitter region and the base extraction region are provided at a distance equal to or less than the predetermined base width, and the base resistance can be sufficiently reduced.

Further, a bipolar semiconductor device according to the present invention comprises an insulator and a semiconductor thin film selectively laminated on the insulator, wherein the semiconductor thin film has a first conductivity type collector region. A first conductivity type emitter region, a second conductivity type base region sandwiched between the collector region and the emitter region and having a predetermined base width, and a second conductivity type base lead connected to the base region. Region on the same plane, the base region and the emitter region,
An impurity of the first conductivity type and an impurity of the second conductivity type are introduced from an end portion of the same mask by a self-alignment process. The semiconductor thin film further has a first conductivity type emitter extraction region connected to the first conductivity type emitter region, which is determined by a difference in diffusion distance between the second conductivity type impurity and the second conductivity type impurity. Is characterized by having a first portion and a second portion provided between the first portion and the emitter region, recovering the crystallinity of the high-concentration emitter region, and improving the emitter resistance. Can be maintained at a sufficiently low value.

Further, the emitter resistance can be further reduced by forming a silicide film on the emitter extraction region.

On the other hand, the base extraction region is provided on both sides of the base region. Each of the base extraction regions has a junction with the collector region on both sides of the collector region. In order to prevent the collector region from being depleted by a depletion layer extending from each of them, the collector region is configured to have a non-constant interval so that a neutral region of the collector region is secured and degradation of transistor characteristics is eliminated. be able to.

Further, the semiconductor thin film further includes a collector extraction region adjacent to the collector region and having a higher impurity concentration than the collector region, and a current path from the collector extraction region to the base region includes By configuring the current path from the collector extraction region to the base extraction region so as to be effectively the same as or shorter than the current path, a sufficient base-collector breakdown voltage can be ensured.

On the other hand, in the method of manufacturing a bipolar semiconductor device according to the present invention, a semiconductor thin film having a predetermined pattern is selectively provided on an insulator, and the semiconductor thin film is formed of a first semiconductor thin film.
A collector region of a conductivity type, an emitter region of a first conductivity type, a base region of a second conductivity type having a predetermined base width sandwiched between the collector region and the emitter region, and a second region connected to the base region. A method of manufacturing a bipolar semiconductor device having a two-conductivity-type base extraction region on the same plane, wherein the collector region introduces a first-conductivity-type impurity into a semiconductor layer provided on an insulating layer. The base extraction region is formed by forming a first mask on the semiconductor layer, forming a side wall on a side surface of the first mask, and adding a second conductivity type impurity outside the side wall. The semiconductor thin film formed by the introduction and having the predetermined pattern shape is formed on the semiconductor layer by the first thin film.
Forming a second mask so as to intersect with the first mask, selectively etching the semiconductor layer while being formed on the semiconductor layer together with the first mask, and further comprising an isotropic etching method. The side surface of the semiconductor layer is formed to be recessed from the end of the first mask and the end of the second mask by side etching the semiconductor layer, and the base region is formed by the second mask. Is formed under the second mask by introducing an impurity of the second conductivity type on one side of the semiconductor thin film and raising the temperature to diffuse the impurity along the in-plane direction of the semiconductor thin film. An impurity profile of the base region is formed by introducing a first conductivity type impurity into one side of the second mask, and the base extraction region is formed first. It is possible to eliminate a decrease in current amplification factor and a deterioration in high-frequency characteristics due to an increase in the base width W due to the deformation and a deterioration in the impurity profile of the emitter region. Is not introduced into unnecessary parts when introducing.

Alternatively, in the method of manufacturing a bipolar semiconductor device according to the present invention, a semiconductor thin film having a predetermined pattern is selectively provided on an insulator, wherein the semiconductor thin film has a collector region of a first conductivity type; A first conductivity type emitter region, a second conductivity type base region having a predetermined base width sandwiched between the collector region and the emitter region, and a second conductivity type base lead region connected to the base region Wherein the collector region is formed by introducing a first conductivity type impurity into a semiconductor layer provided on an insulating layer; and In the lead region, a first mask is formed on the semiconductor layer, a side wall is formed on a side surface of the first mask, and a second conductivity type impurity is introduced outside the side wall. Form I, a semiconductor thin film having the predetermined pattern, the first on the semiconductor layer
A second mask is formed so as to intersect each other with the mask, and the semiconductor layer is selectively etched while being formed on the semiconductor layer together with the first mask, and the base region is formed by: A second mask is provided on one side of the second mask.
An impurity of a conductivity type is introduced, the temperature is increased, and the impurity is diffused along an in-plane direction of the semiconductor thin film, thereby forming the impurity under the second mask. Providing a third mask covering an end portion of the semiconductor thin film on one side of the semiconductor thin film, and introducing a first conductivity type impurity into the semiconductor thin film between the second mask and the third mask. Characterized by forming
By promoting recrystallization of the introduction region surrounded on both sides by the single crystal region, the emitter resistance can be effectively reduced.

Alternatively, in the method of manufacturing a bipolar semiconductor device according to the present invention, a semiconductor thin film having a predetermined pattern is selectively provided on an insulator, wherein the semiconductor thin film has a collector region of a first conductivity type; An emitter region of a first conductivity type, a base region of a second conductivity type sandwiched between the collector region and the emitter region and having a predetermined base width;
A method of manufacturing a bipolar semiconductor device, comprising: a base region of conductivity type; and a base connection region of a second conductivity type connecting the base region and the base region on the same plane. A first conductive type impurity is introduced into a semiconductor layer provided on the insulating layer, and the base extraction region forms a first mask on the semiconductor layer; A side wall is formed on a side surface of the mask, and a second conductive type impurity is formed outside the side wall. The semiconductor thin film having the predetermined pattern is formed on the semiconductor layer by the first mask. Forming a second mask so as to intersect with each other, and selectively etching the semiconductor layer while being formed on the semiconductor layer together with the first mask; Second on one side of said second mask
A conductive type impurity is introduced, the temperature is increased, and the impurity is diffused along an in-plane direction of the semiconductor thin film, thereby forming the impurity under the second mask.
On one side of the second mask, an impurity of the second conductivity type is formed in the semiconductor thin film by obliquely ion-implanting the main surface of the semiconductor thin film, and the emitter region is formed in the second region. On one side of the mask is formed by introducing an impurity of the first conductivity type into the semiconductor thin film, by forming a base connecting region, to reliably connect the base region and the base lead region, Base resistance can be reduced.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing a bipolar semiconductor device of the present invention. That is, FIG.
1A is a plan view showing the semiconductor layer of the bipolar semiconductor device with the semiconductor layer exposed, and FIGS. 1B to 1D are each a plan view of FIG.
FIG. 3A is a sectional view taken along line AA ′, line BB ′, and line CC ′ in FIG. FIG. 1E shows a BiCMOS (bipolar).
FIG. 4 is a cross-sectional view in the gate length direction of a MOS transistor portion when a (CMOS) structure is formed.

In the bipolar semiconductor device of the present invention, a single-crystal silicon layer 2 as a semiconductor thin film is laminated on an insulating substrate 1 to a required thickness and patterned into a predetermined shape. Specifically, as shown in FIG. 1A, a first rectangular pattern extending in the AA ′ direction and a second rectangular pattern extending in the BB ′ direction are substantially perpendicular to each other. It has a cross shape.

In the overlapping portions of these rectangular patterns,
N ⁻ -type collector region 5a and p-type base region 4a are formed adjacent to each other. In the single-crystal silicon layer 2 other than the overlapping portion, an n ⁺ -type collector lead-out region 5b is formed adjacent to the n ⁻ -type collector region 5a, and an n ⁺ -type emitter region 3a is formed adjacent to the p-type base region 4a. And connected to the n ⁺ -type emitter extraction region 3b. The p-type base region 4a sandwiched between the n ⁺ -type emitter region 3a and the n − -type collector region 5a is extremely narrow (100
(about nm or less).

Furthermore, on the outside of the single-crystal silicon layer 2 of the overlapping portion of the rectangular pattern, adjacent to the p-type base region 4a p ⁺ -type base extraction region 4b is formed, and characteristic of the, n ⁺ Type emitter region 3a and this p ⁺
The mold base extraction regions 4b are formed in a self-aligned manner with each other using a mask of a rectangular pattern extending in the vertical direction or a mask of a rectangular pattern extending in the horizontal direction in FIG. It is a point. That is, a pn junction is formed near the overlapping portion of these rectangular patterns via the p-type base region 4a having the base width W as shown in the figure or directly. With such a configuration, the mask is formed close to the base width W or less with good controllability without “misalignment” of the mask, thereby minimizing the base resistance.

Here, the range of each conductivity type region extends to the tail portion where the impurity concentration falls to about the concentration in the n ⁻ -type collector region. Practically, the impurity concentration is often in the range of about 1E16 cm ^-3 or more.

Further, the n ⁺ type emitter extraction region 3b, P
^{The +} type base extraction region 4b and the n ⁺ type collector extraction region 5b are respectively provided with an emitter electrode 6E and a base electrode 6B via contact holes formed in an interlayer insulating film (not shown) deposited on the single crystal silicon layer 2. , And collector electrode 6C.

In the MOS transistor portion shown in FIG. 1E, the gate electrode polycrystalline silicon 104 and the gate electrode silicide are interposed in the device region separated by the device isolation insulating film 102 via the gate insulating film 103. 1
06, a gate electrode upper layer insulating film 108 is formed.

Next, a description will be given of a method of manufacturing the bipolar semiconductor device having the above structure. 2 to 10 are schematic process sectional views illustrating a method for manufacturing the bipolar semiconductor device of FIG. Here, each figure (a) is a plan view of the bipolar semiconductor device at each stage, and (b) to (d) respectively show the AA ′ line, BB ′ line, and C in (a). −
C 'line sectional view, and (e) is a BiCMOS (bipolar C
FIG. 4 is a cross-sectional view in the gate length direction of a MOS transistor portion when a (MOS) structure is formed.

In this method, first, as shown in FIG. 2, a first mask is formed on an SOI substrate. Specifically, first, up to the gate electrode of the MOS transistor is first formed on the SOI substrate. This SOI substrate is a substrate in which a single-crystal silicon layer 2 as a semiconductor thin film is laminated on an insulating substrate 1 to a predetermined thickness.
It can be obtained by various methods such as a SIMOX substrate or a Unibond substrate supplied from a substrate maker. MOS
After forming the gate electrode, the process moves to the manufacture of a bipolar transistor.

First, a required amount of n-type impurities such as phosphorus (P) or arsenic (As) is added to the silicon layer 2 to perform annealing, and then a low-concentration n-type impurity to be an n ⁻ -type collector region 5a is formed. Form an area. Next, a stopper film 11 is formed on the n-type impurity region, and the first mask 12 is patterned and formed into a predetermined shape such as a horizontally long rectangle through the stopper film 11. As a material of the first mask 12, for example, polycrystalline silicon is used, and the stopper film 11 is used.
For example, a film in which three layers of a thin silicon oxide film / a thin silicon nitride film / a thin silicon oxide film are stacked can be used. Since the silicon oxide film has a selectivity of several tens or more with respect to the anisotropic etching of polycrystalline silicon, the first mask 12 is processed by the stopper film 11
Can be stopped by the thin silicon oxide film on the top layer.

Next, as shown in FIG. 3, a side wall is provided on the first mask. Specifically, a sidewall film 13 is formed on the side surface of the first mask 12, and ion implantation is performed using at least the first mask 12 and the sidewall film 13 as masks. For example, a required amount of a p-type impurity such as boron (B) is added, annealing is performed if necessary, and p-type impurities are added to the first mask 12, that is, a horizontally long rectangular pattern in a self-aligned manner.
^A p ⁺ -type diffusion layer serving as the ⁺ -type base extraction region 4b is formed. According to this method, depending on the thickness of the sidewall film 13 and the conditions of the heat process, the p ⁺ -type base extraction region 4b is formed independently of the concentration profile of the intrinsic region usually formed by a low-temperature or short-time heat process. The p ⁺ type diffusion layer can be set at a desired position in a self-aligned manner with respect to the first mask 12. Then, by adjusting the thickness of the side wall film 13 and the conditions of the heat treatment step, as shown in FIG. 1, the base extraction region 4b is securely formed with respect to the base region 4a formed with the width of the base width W. Can be connected to That is, according to the present invention, by such a self-aligning process, the interval between the base extraction region 4b and the emitter region 3a can be formed to be smaller than the base width W. As a result, the base resistance can be significantly reduced, and the high-frequency characteristics of the transistor can be significantly improved.

Here, as the material of the side wall film 13, it is desirable to use polycrystalline silicon which can be processed with a high selectivity with respect to the stopper film 11. However, in this case, the first
If polycrystalline silicon is used for the mask 12, a thin oxide film or the like is deposited on the entire surface of the wafer to form a stopper film 11 'as shown in FIG. At the time of anisotropic etching for forming the side wall film 13, the first mask 12 can be prevented from disappearing due to over-etching.

Next, as shown in FIG. 4, a mask material serving as a second mask is deposited. Specifically, first, the sidewall film 13 is removed by isotropic etching using the stopper film 11 'as a stopper, and then the stopper film 11' is removed. The step of removing the stopper film 11 'is not always essential. However, as in the present embodiment, the first mask 12
If a non-insulating film such as polycrystalline silicon is used for
In order to ensure the stability of the transistor operation, it is necessary to finally peel off the first mask 12. In this embodiment, it is assumed that the stopper film 11 ′ is removed. In this case, it is desirable that the stopper film 11 ′ be removed here so that the first mask 12 is easily peeled off in a later step.
In the case where the stopper film 11 'is formed of a silicon oxide film as in this embodiment, an HF solution, an NH4F solution, or the like is used to form a polycrystalline silicon film as the first mask 12 thereunder and as the stopper film 11. Only the uppermost thin oxide film of the thin oxide film / thin nitride film / thin oxide film is removed to make the stopper film 11 ″ thinner, so that the stopper film 11 ′ can be removed at a high selectivity close to infinity. .

Thereafter, a film 14 serving as a second mask is deposited on the entire surface of the wafer. As the second mask material, a material capable of selectively performing anisotropic etching on the first mask material is preferable. For example, a silicon nitride film can be used.

Next, as shown in FIG. 5, the second mask is patterned. Specifically, a rectangular resist mask extending in the vertical direction is formed, and the mask material 14 is patterned to form the second mask 14. At this time, the first mask 12 and the exposed semiconductor thin film 2 are partially etched by over-etching, but there is no problem if at least the entirety is not etched. Thus, the first mask 12 having a horizontally long rectangular pattern
And a second mask 14 having a vertically long rectangular pattern are formed to intersect.

Next, as shown in FIG.
Is patterned. More specifically, the semiconductor thin film 2 is etched using the first mask 12 and the second mask 14 as masks to form the semiconductor thin film 2 having a substantially cross-shaped pattern. At this time, in this embodiment in which polycrystalline silicon is used as the material of the first mask 12, the first mask 12 is etched at substantially the same etching rate when etching single crystal silicon as the semiconductor thin film 2, and disappears. Sometimes. However, the stopper film 11 ″ thereunder serves as a stopper, and the semiconductor thin film thereunder is not etched.

In this step, first, the first mask 12 and the side wall film 13 are used to form a p ⁺ -type base extraction region 4b formed in a self-aligned manner with respect to a horizontally long rectangle.
Are cut out and ideally patterned so as to remain only in a vertically long rectangular pattern. Thereafter, a process of removing damage due to anisotropic etching is performed.
The damaged semiconductor thin film layer 2 is etched in the lateral direction, and the semiconductor thin film 2 has a receded shape as indicated by an arrow in the figure. At this time, by adding an etching step for intentionally retreating, a portion of a vertically long rectangular pattern is mainly used for ion implantation into the p-type base region 4a or the n ⁺ -type emitter region 3a in the subsequent process. The impurity may be prevented from being injected obliquely to the side surface of the semiconductor thin film 2.

Next, as shown in FIG. 7, a p-type region is formed. Specifically, a p-type impurity such as boron (B) is introduced into a part of the horizontally long rectangular pattern of the semiconductor thin film 2 by ion implantation or the like using the second mask 14 and the resist as a mask, and a heat treatment step is performed. By performing the diffusion in the lateral direction, a p-type diffusion layer serving as the p-type base region 4 a is formed below the second mask 14.

Prior to this, as shown in FIG. 3, single crystal silicon as the semiconductor thin film 12 or the first mask 1 is used.
It is desirable to form a thin sidewall oxide film by an oxidation process on the exposed sidewalls of the polycrystalline silicon as No. 2 to form the protective film 15. Due to the retreat of these layers shown in FIG. 6 and the presence of the protective film 15, the ions obliquely incident upon the ion implantation can be shut out, and the impurities are directly introduced into the vertically elongated rectangular semiconductor thin film 2. Can be prevented. In this manner, the p-type base region 4a having good controllability can be formed by the p-type impurity diffusion layer diffused in the lateral direction from the horizontally long rectangular portion.

Next, as shown in FIG. 8, an emitter region is formed. Specifically, using the second mask 14 and the resist as masks, a horizontally long rectangular portion of the semiconductor thin film 2 is formed.
For example, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced by ion implantation or the like, and if necessary, a heat treatment step is added to form the n ⁺ -type emitter region 3a. Due to the recession of the semiconductor thin film 2 and the protective film 15, the impurity can be selectively introduced only into a desired portion of the horizontally long rectangular semiconductor thin film 2 in this case as well.

Here, the p-type base region 4 shown in FIG.
Although it is possible to use a resist pattern having an opening similar to that of the step a, the ion implantation region is limited to a region as small as possible in FIG. This is for the following reason. That is, in the ion implantation for the n ⁺ -type emitter region 3a, the same applies to the p-type base region 4a.
Since it is important to have a uniform impurity profile in the depth direction of the semiconductor thin film 2 and to perform a uniform bipolar operation over the entire thickness direction, impurities are also present in a deep region in the film thickness direction. It is necessary to select the conditions of ion implantation so as to be implanted. That is, it is necessary to implant impurities at a higher acceleration energy than usual. But in this case,
In particular, when As having a large atomic weight is ion-implanted at a high concentration, the ion implantation of the n ⁺ -type emitter region 3a may cause the film in the ion-implanted region to be disturbed throughout the depth direction and become amorphous. is there. If the recrystallization using the single crystal silicon layer as the nucleus of the semiconductor thin film 2 in the non-ion-implanted region adjacent in the lateral direction as a nucleus does not sufficiently occur in the subsequent thermal process, the resultant will be polycrystallized, and This causes a problem that the resistance increases to about one digit. This significantly reduces the high frequency performance of the bipolar transistor.

On the other hand, as in this embodiment, the ion-implanted region of the n ⁺ -type emitter region 3a is limited as much as possible, so that the high-resistance semiconductor region is narrowed and recrystallized from both sides. In this way, single crystallization can be sufficiently easily caused, and as a result, an increase in resistance can be prevented.

Next, as shown in FIG. 9, an emitter extraction region and a collector extraction region are formed. Specifically, using the second mask 14 and the resist as a mask, an n-type impurity such as phosphorus (P) or arsenic (As) is doped by ion implantation or the like, and if necessary, annealed by n ⁺ The type emitter extraction region 3b and the n ⁺ type collector extraction region 5b are formed. In this case,
Since it is sufficient to simply form a low-resistance diffusion layer, ions may be implanted in the vicinity of the surface layer of the semiconductor thin film 2, and the above-described problem of polycrystallization does not occur. The combination and order of ion implantation of the n ⁺ -type emitter region 3a, the n ⁺ -type emitter extraction region 3b, and the n ⁺ -type collector extraction region 5b can be changed.

At this point, basically, the basic portion of the bipolar semiconductor device is completed, and then the first and second masks 12 and 14 of the MOS transistor portion are removed to form a source / drain in advance. If not, a source / drain is formed by a desired method, an interlayer insulating film is deposited, and a wiring process is performed.

First, as shown in FIG. 10, the first mask and the second mask are removed. That is, in the present embodiment, since the polycrystalline silicon film has been used as the first mask 12, as described with reference to FIG.
It is desirable to remove the non-insulating film together with the second mask 14 in order to avoid a structure adjacent to the surface of the transistor. Here, a nitride film is used as the second mask 14, but according to isotropic dry etching,
Both the nitride film and the polycrystalline silicon film can be etched at a selectivity of several tens or more with respect to the oxide film.
Therefore, the first mask 12 and the second mask 14 can be completely removed by using the oxide film as the protective film 15 and the oxide film of the stopper film 11 or 11 ″ as the stopper.

In addition, by this removing step, for example, FIG.
As shown in FIG.
It can be easily removed with an H4F solution or the like. Also, the remaining stopper film 11 or 11 ″ can be removed by an NH 4 F solution and the nitride film can be removed by hot phosphoric acid or the like.

By forming a single-plate-shaped semiconductor thin film 2 having a substantially cruciform pattern shape and having no step, a desired interlayer insulating film and a wiring process (not shown) are performed to form a bipolar transistor. To complete.

According to the present manufacturing method, at least on the upper surface of the semiconductor thin film 2, the stopper film 1 formed first is formed.
1 until the end of the main process, and as a result,
A structure having no steps can be formed on the upper surface of the semiconductor thin film without any processing damage other than ion implantation. Therefore, a high-performance transistor can be realized without deteriorating the mobility of carriers near the surface.

Here, in the bipolar transistor having the above-described structure, the p-type base region 4a and the p ⁺ -type base extraction region 4b are brought closer to a horizontally long rectangle until they are directly connected. Here, if you get too close,
In particular, when the width of the horizontally long rectangular pattern is narrow, the width (vertical direction) of the neutral region in the n ⁻ -type collector region 5a is reduced by the depletion layer extending from the p ⁺ -type base extraction region 4b into the n ⁻ -type collector region 5a. This narrows the carrier path from the emitter through the base to the collector. As a result, there is a possibility that problems such as deterioration of carrier transmission efficiency due to being drawn into the base and so-called Kirk effect tend to occur due to an increase in current density. In other words, there is actually an optimum value for the position of the p ⁺ -type base extraction region 4b and the width of the horizontally long rectangular pattern, including the width of the horizontally long rectangular pattern.
At this time, a configuration in which the p ⁺ -type base region 4b is directly connected to the p-type base region 4a may not always be desirable.

In such a case, for example, after the mask shown in FIG. 5 is formed, as shown in FIG. 11, a p-type impurity such as boron (B) is By doing so, it is possible to form the p-type base connection region 4c and prevent the offset between the p ⁺ -type base extraction region 4b and the p-type base region 4a to be formed later.

In the embodiment described above, the length of the n ⁻ -type collector region 5a is determined by the formation of the n ⁺ -type collector lead-out region 5b. Accompanying this, characteristics tend to fluctuate. In particular, the breakdown voltage between the emitter and the collector, the current amplification factor, and the like fluctuate.

FIG. 12 is a process sectional view showing a manufacturing method for solving this problem. The process in the figure corresponds to FIG. 9 described above. That is, as shown in FIG. 8, p-type base region 4a and n ⁺
After forming the mold emitter region 3a, a side wall film 13 'such as, for example, polycrystalline silicon, an oxide film or a nitride film is formed. In this state, arsenic (As) or arsenic (As) is exposed through a resist mask exposing a horizontally long rectangular portion. An n-type impurity such as phosphorus (P) is ion-implanted. In this case, the n ⁺ -type collector lead-out region 5b is formed simultaneously with the n ⁺ -type emitter lead-out region. In practice, lithography is not always necessary.

Thus, the width of the vertically long rectangle and the side wall film 1
The length of the n ⁻ -type collector region 5a can be set by the film thickness of 3 ′, and characteristics without fluctuation can be realized. Even when polycrystalline silicon is used as the sidewall film, it can be simultaneously removed by the peeling step shown in FIG.

In the method shown in FIG.
When 3 'is formed of an oxide film or a nitride film, the side wall film 1
It is also possible to selectively form a low-resistance silicide film by a salicide process on the n ⁺ -type diffusion layers on the emitter side and the collector side exposed by the formation of 3 ′. As a result, the emitter and collector resistance can be significantly reduced, and the high frequency characteristics are improved.

In the embodiments described so far, the element region is formed by the vertically long, rectangular pattern and the horizontally long rectangular pattern, but both need not necessarily be rectangular patterns.

FIG. 13 is a schematic view illustrating a pattern shape that can be used in the present invention. That is,
As shown in the figure, the width of the horizontally long rectangular pattern may be widened on the collector side. As a result, FIG.
P ⁺ type base extraction region 4b as described in FIG.
From the n ^- there is overhang of the depletion layer to type collector region 5a also n ^- -type collector region 5a of the neutral region can be reliably secure, it is possible to suppress deterioration of characteristics.

FIG. 14 is a schematic view illustrating another pattern that can be used in the present invention. That is,
As shown in the figure, a structure may be adopted in which the width of the horizontally long rectangular pattern is increased on the collector side outside the p ⁺ -type base extraction region 4b and narrowed again to an arbitrary width. According to this structure, the effective distance (A in the figure) from the p ⁺ -type base lead-out region 4b to the n ⁺ -type collector lead-out region 5b is determined by the distance from the p-type base region 4a to the n ⁺ -type collector lead-out region 5b (see FIG. It is possible to secure a value equal to or greater than B) in FIG. Conversely, in a normal horizontally long rectangular pattern, the effective distance A is likely to be smaller than the distance B. Generally, the base
Since the junction breakdown voltage BVcbo between the collectors is determined by the minimum length of the n ⁻ -type collector region 5a, if the distance is determined on the A side where the distance is smaller, the original breakdown voltage is degraded. Here, generally, BVcbo and the emitter-collector breakdown voltage BV
CEO has the following relationship. BVceo-BVcbo / (h _fe ) ^{n / 2}

Where (h _fe ) is the current amplification factor,
Several tens to several hundreds, and n is empirically said to be 3-5. That is, as can be seen from the above equation, BVc
Even if bo is slightly deteriorated, BVceo will be considerably deteriorated. Therefore, n which determines BVcbo
The structure shown in FIG. 14 in which the length of the − type collector region 5a can be made equal everywhere is very important for obtaining stable device characteristics.

FIG. 15 is a schematic view illustrating another pattern that can be used in the present invention. That is,
The figure shows an example in which a vertically long rectangular pattern is modified. In this case, the width of the vertically long rectangular pattern is reduced near the intrinsic region intersecting with the horizontally long rectangular pattern, and the width is increased outside the intrinsic region. By reducing the width in the intrinsic region, the p ⁺ type base extraction region 4b and the n−
By reducing the junction capacitance with the collector region 5a and expanding it outside, the base resistance of the p ⁺ -type base extraction region 4b can be reduced, and the high-frequency characteristics can be further improved.

The embodiment of the invention has been described with reference to examples. However, the present invention is not limited to these specific examples.

For example, with respect to each of the vertically and horizontally long patterns described above, their actual dimensions may be freely changed, and they may be arbitrarily combined.

In the specific examples described above, an npn-type transistor has been described as an example, but the present invention can be similarly applied to a pnp-type transistor. Further, the layout of each region of the bipolar transistor can be appropriately changed without departing from the gist of the present invention, and is not limited to the illustrated embodiment.

[0060]

The present invention is embodied in the form described above, and has the following effects. First, according to the present invention, the semiconductor thin film to be the emitter region and the base extraction region is formed using different mask materials by different lithography steps, and the diffusion layers forming the respective regions are mutually separated. It is formed in a self-aligned manner. As a result, a structure in which the emitter region and the base extraction region are close to the base width or less is possible. Accordingly, the characteristics of the bipolar transistor can be remarkably improved by greatly reducing the base resistance as compared with the related art.

Further, the impurity introduction into the base extraction region is performed before the impurity introduction into the base and the emitter defining the base width, so that the impurity profile and the base width of the emitter region and the base region are ideally set. Can be formed. As a result, various characteristics including high-frequency characteristics can be improved, and such a high-performance bipolar transistor can be reliably and stably manufactured.

Further, according to the present invention, even if impurities are introduced into the emitter region at a high concentration, the crystallinity can be sufficiently recovered, and the emitter resistance can be reduced.

Further, according to the present invention, the depletion of the collector region can be effectively prevented.
A sufficient collector breakdown voltage can be ensured.

As described above, according to the present invention, a high-performance bipolar semiconductor device can be manufactured reliably and easily, and the industrial advantage is great.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a bipolar semiconductor device of the present invention. That is, FIG. 1A is a plan view in which the semiconductor layer of the bipolar semiconductor device is exposed, and FIG.
(B) to (d) respectively show AA ′ in FIG.
FIG. 3 is a sectional view taken along line BB ′ and line CC ′. Also,
FIG. 1E is a sectional view in the gate length direction of the MOS transistor portion when a BiCMOS (bipolar CMOS) structure is formed.

FIG. 2 is a schematic process sectional view illustrating a method for manufacturing the bipolar semiconductor device of FIG. Here, FIG. 2A is a plan view in the middle of the manufacturing process, and FIGS. 2B to 2D are cross sections taken along line AA ′, line BB ′, and line CC ′ in FIG. FIG. 1E is a cross-sectional view in the gate length direction of a MOS transistor portion when a BiCMOS (bipolar CMOS) structure is formed.

FIG. 3 is a schematic sectional view for explaining the method of manufacturing the bipolar semiconductor device in FIG. 1;

FIG. 4 is a schematic cross-sectional view for explaining the method of manufacturing the bipolar semiconductor device in FIG. 1;

FIG. 5 is a schematic cross-sectional view for explaining the method of manufacturing the bipolar semiconductor device in FIG. 1;

FIG. 6 is a schematic process sectional view illustrating the method for manufacturing the bipolar semiconductor device of FIG.

FIG. 7 is a schematic cross-sectional view for explaining the method of manufacturing the bipolar semiconductor device in FIG. 1;

FIG. 8 is a schematic process sectional view illustrating the method for manufacturing the bipolar semiconductor device of FIG.

9 is a schematic process sectional view illustrating the method for manufacturing the bipolar semiconductor device of FIG.

10 is a schematic process sectional view illustrating the method of manufacturing the bipolar semiconductor device in FIG. 1;

11 is a schematic process sectional view illustrating the method of manufacturing the bipolar semiconductor device in FIG. 1;

12 is a schematic process sectional view illustrating the method for manufacturing the bipolar semiconductor device of FIG.

FIG. 13 is a schematic view illustrating a pattern shape that can be used in the present invention.

FIG. 14 is a schematic view illustrating a pattern shape that can be used in the present invention.

FIG. 15 is a schematic view illustrating a pattern shape that can be used in the present invention.

FIG. 16 is a schematic diagram illustrating a planar structure of a conventional lateral bipolar transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating layer 2 Semiconductor layer 3a, 123 Emitter region 3b Emitter extraction region 4a, 124a Base region 4b, 124b Base extraction region 5a, 125a Collector region 5b, 125b Collector extraction region 6E, 126E Emitter electrode 6B, 126B Base electrode 6C, 126C Collector electrode 11 Stopper film 12 First mask 13, 13 ′ Side wall 14 First mask 15 Oxide film fence 102 Element isolation insulating film 104 Gate electrode polycrystalline silicon 106 Gate electrode silicide 108 Gate electrode upper layer insulating film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shin Yoshimi, Komukai Toshiba-cho, Koyuki-ku, Kawasaki-shi, Kanagawa 1 Inside Toshiba R & D Center (72) Inventor Tsuneaki Fuse, Koyuki-ku, Kawasaki-shi, Kanagawa Muka Toshiba 1 Inside the Toshiba R & D Center (72) Inventor Mamoru Terauchi 1 Komukai Toshiba-cho 1 in Saiwai-ku, Kawasaki City, Kanagawa Prefecture Inside the Toshiba R & D Center (72) Inventor Kazumi Ino Kanagawa 1 Tokoba, Komukai Toshiba-cho, Saiwai-ku, Kawasaki

Claims (6)

[Claims] A first conductive type collector region; a first conductive type collector region; a first conductive type collector region; a first conductive type collector region;
A conductive type emitter region, a second conductive type base region having a predetermined base width sandwiched between the collector region and the emitter region, and a second conductive type base extraction region connected to the base region. The base region and the emitter region are formed by introducing a first conductivity type impurity and a second conductivity type impurity from an end of the same mask by a self-alignment process; The predetermined base width is determined by a difference in diffusion distance between the first conductivity type impurity and the second conductivity type impurity, and the base extraction region is a distance from the emitter region equal to or less than the predetermined base width. A bipolar type semiconductor device, wherein the bipolar type semiconductor device is provided with a space therebetween. 2. A semiconductor device comprising: an insulator; and a semiconductor thin film selectively laminated on the insulator, wherein the semiconductor thin film has a first conductivity type collector region,
A conductive type emitter region, a second conductive type base region having a predetermined base width sandwiched between the collector region and the emitter region, and a second conductive type base extraction region connected to the base region. The base region and the emitter region are formed by introducing a first conductivity type impurity and a second conductivity type impurity from an end of the same mask by a self-alignment process; The predetermined base width is determined by a difference in a diffusion distance between the first conductivity type impurity and the second conductivity type impurity, and the semiconductor thin film is further connected to the first conductivity type emitter region. A first conductivity type emitter lead-out region, wherein the emitter lead-out region is a first portion of a first conductivity type and a second portion provided between the first portion and the emitter region. Bipolar semiconductor device characterized by having a portion. 3. The base extraction region is provided on both sides of the base region. Each of the base extraction regions has a junction with the collector region on both sides of the collector region. 3. The bipolar semiconductor device according to claim 1, wherein an interval between the junctions is not constant so that the collector region is not depleted by a depletion layer extending from each of them. 4. 4. A semiconductor thin film having a predetermined pattern shape is selectively provided on an insulator, and said semiconductor thin film is a first semiconductor thin film.
A collector region of a conductivity type, an emitter region of a first conductivity type, a base region of a second conductivity type having a predetermined base width sandwiched between the collector region and the emitter region, and a second region connected to the base region. A method for manufacturing a bipolar semiconductor device having a two-conductivity-type base extraction region on the same plane, wherein the collector region introduces a first-conductivity-type impurity into a semiconductor layer provided on an insulating layer. The base extraction region forms a first mask on the semiconductor layer, forms a side wall on a side surface of the first mask, and forms a second conductive layer on the semiconductor layer outside the side wall. A second mask is formed on the semiconductor layer so as to intersect with the first mask, wherein the second mask is formed by introducing a type impurity. Serial selectively etching the semiconductor layer in a state that is formed on the first mask with the semiconductor layer, further, the etching method isotropic,
By side-etching the semiconductor layer, a side surface of the semiconductor layer is formed to be receded from end portions of the first mask and the second mask, and the base region is formed on one side of the second mask. Forming an impurity under the second mask by introducing an impurity of the second conductivity type, and raising the temperature to diffuse the impurity along an in-plane direction of the semiconductor thin film; 2. A method for manufacturing a bipolar semiconductor device, comprising: forming a first conductive type impurity on one side of a second mask. 5. A semiconductor thin film having a predetermined pattern shape is selectively provided on an insulator, and said semiconductor thin film is a first thin film.
A collector region of a conductivity type, an emitter region of a first conductivity type, a base region of a second conductivity type having a predetermined base width sandwiched between the collector region and the emitter region, and a second region connected to the base region. A method for manufacturing a bipolar semiconductor device having a two-conductivity-type base extraction region on the same plane, wherein the collector region introduces a first-conductivity-type impurity into a semiconductor layer provided on an insulating layer. The base extraction region forms a first mask on the semiconductor layer, forms a side wall on a side surface of the first mask, and forms a second conductive layer on the semiconductor layer outside the side wall. A second mask is formed on the semiconductor layer so as to intersect with the first mask, wherein the second mask is formed by introducing a type impurity. The semiconductor layer is selectively etched while being formed on the semiconductor layer together with the first mask, and the base region is doped with a second conductivity type impurity on one side of the second mask. Forming an emitter region under the second mask by raising the temperature and diffusing the impurity along an in-plane direction of the semiconductor thin film; and forming the emitter region on one side of the second mask. A third mask covering an end of the semiconductor thin film is provided, and the semiconductor thin film is formed by introducing a first conductivity type impurity into the semiconductor thin film between the second mask and the third mask. Of manufacturing a bipolar semiconductor device. 6. A semiconductor thin film having a predetermined pattern shape is selectively provided on an insulator, wherein said semiconductor thin film is a first semiconductor thin film.
A collector region of a conductivity type, an emitter region of a first conductivity type, a base region of a second conductivity type sandwiched between the collector region and the emitter region and having a predetermined base width;
A method for manufacturing a bipolar semiconductor device, comprising: a base region of a conductivity type; and a base connection region of a second conductivity type connecting the base region and the base region on the same plane. A first conductive type impurity is introduced into a semiconductor layer provided on the insulating layer, and the base extraction region forms a first mask on the semiconductor layer, A side wall is formed on a side surface of the mask, and a second conductive type impurity is introduced into the semiconductor layer outside the side wall. The base connecting region is formed on the semiconductor layer by the first mask and the first mask. Forming a second mask so as to cross each other,
A semiconductor thin film having a predetermined pattern shape formed by obliquely ion-implanting a second conductivity type impurity into the semiconductor thin film on the one side of the second mask with respect to a main surface of the semiconductor thin film; Is formed by selectively etching the semiconductor layer in a state where the first mask and the second mask are both formed on the semiconductor layer, and the base region is formed of the second mask. Introducing an impurity of the second conductivity type on one side, raising the temperature and diffusing the impurity along the in-plane direction of the semiconductor thin film to form an impurity under the second mask, A method for manufacturing a bipolar semiconductor device, comprising forming a semiconductor thin film on one side of a second mask by introducing an impurity of a first conductivity type into the semiconductor thin film.